341 lines
12 KiB
C
341 lines
12 KiB
C
#ifndef _TXW81X_DEF_H_
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#define _TXW81X_DEF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "typesdef.h"
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/* ------------------------- Interrupt Number Definition ------------------------ */
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enum IRQn
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{
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/****** Peripheral Interrupt Numbers *********************************************************/
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USB20DMA_IRQn = 0,
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USB20MC_IRQn = 1,
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UART0_IRQn = 2,
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UART1_IRQn = 3,
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LCD_IRQn = 4,
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QSPI_IRQn = 5,
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SPI0_IRQn = 6,
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SPI1_IRQn = 7,
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SPI2_IRQn = 8,
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OSPI_IRQn = 9,
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TIM0_IRQn = 10,
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TIM1_IRQn = 11,
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TIM2_IRQn = 12,
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TIM3_IRQn = 13,
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SCALE1_IRQn = 14,
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AUDIO_SUBSYS0_IRQn = 15, //ALAW & HS & VAD
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AUDIO_SUBSYS1_IRQn = 16, //ADC
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AUDIO_SUBSYS2_IRQn = 17, //DAC
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SDIO_IRQn = 18,
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SDIO_RST_IRQn = 19,
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SDHOST_IRQn = 20,
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LMAC_IRQn = 21,
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GMAC_IRQn = 22,
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M2M0_IRQn = 23,
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M2M1_IRQn = 24,
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CORET_IRQn = 25, //CPU TIMER
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SPACC_PKA_IRQn = 26, //SHA/SYS_AES
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CRC_IRQn = 27,
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ADKEY01_IRQn = 28,
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PD_TMR_IRQn = 29,
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WKPND_IRQn = 30,
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PDWKPND_IRQn = 31,
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LVD_IRQn = 32,
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WDT_IRQn = 33,
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SYS_ERR_IRQn = 34,
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IIS0_IRQn = 35,
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IIS1_IRQn = 36,
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GPIOABCE_IRQn = 37,
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//GPIODE_IRQn = 38,
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DVP_IRQn = 39,
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MJPEG01_IRQn = 40,
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//CSI2_IRQn = 41,
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VPP_IRQn = 42,
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PRC_IRQn = 43,
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STMR012345_IRQn = 44,
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PDM_IRQn = 45,
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LED_TMR_IRQn = 46,
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SCALE2_IRQn = 47,
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GFSK_IRQn = 48,
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CMPOUT01_IRQn = 49,
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UART45_IRQn = 50,
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SCALE3_IRQn = 51,
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//SPI5_IRQn = 52,
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//SPI6_IRQn = 53,
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//LED_IRQn = 54,
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//SUPTMR3_IRQn = 55,
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//SUPTMR4_IRQn = 56,
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//SUPTMR5_IRQn = 57,
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USB20PHY_RTC_IRQn = 58,
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//TK_IRQn = 59,
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//CPU0_SPINLOCK_IRQn = 60,
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//CPU0_SEND_MAIL_IRQn = 61,
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//CPU0_RECV_MAIL_IRQn = 62,
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//AUDIO_SUBSYS_IRQn = 63,
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SHA_VIRTUAL_IRQn = 64,
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AES_VIRTUAL_IRQn = 65,
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UART4_IRQn = 66,
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UART5_IRQn = 67,
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GPIOA_IRQn = 68,
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GPIOB_IRQn = 69,
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GPIOC_IRQn = 70,
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GPIOE_IRQn = 71,
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AUVAD_IRQn = 72,
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AUHS_IRQn = 73,
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AUALAW_IRQn = 74,
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IRQ_NUM,
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};
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/* ================================================================================ */
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/* ================ Processor and Core Peripheral Section ================ */
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/* ================================================================================ */
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/* -------- Configuration of the CK803 Processor and Core Peripherals ------- */
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#define __CK803_REV 0x0000U /* Core revision r0p0 */
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#define __MPU_PRESENT 0 /* MGU present or not */
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#define __VIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
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#include "csi_core.h" /* Processor and core peripherals */
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#include "stdint.h"
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////////
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/** @addtogroup Peripheral_registers_structures
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup Peripheral_memory_map
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* @{
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*/
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#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
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#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
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#define SRAM_END_ADDR ((uint32_t)0x20044000) /*!< SRAM end address in the alias region */
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#define PSRAM_BASE ((uint32_t)0x38000000) /*!< SRAM base address in the alias region */
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#define PSRAM_END_ADDR (PSRAM_BASE + 16*1024*1024) /*!< SRAM end address in the alias region */
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#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
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/*!< Peripheral memory map */
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#define APB0_BASE PERIPH_BASE
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#define APB1_BASE (PERIPH_BASE + 0x10000)
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#define AHB_BASE (PERIPH_BASE + 0x20000)
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#define QSPI_BASE (APB0_BASE + 0x0000)
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#define HG_OSPI_BASE (APB0_BASE + 0x1000)
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#define HG_SCHED_BASE (APB0_BASE + 0x2000)
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#define HG_UART0_BASE (APB0_BASE + 0x4000)
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#define HG_UART1_BASE (APB0_BASE + 0x4100)
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#define HG_UART2_BASE (APB0_BASE + 0x4200)
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#define HG_UART3_BASE (APB0_BASE + 0x4300)
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#define HG_UART4_BASE (APB0_BASE + 0x4b70)
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#define HG_UART5_BASE (APB0_BASE + 0x4b90)
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#define SPI0_BASE (APB0_BASE + 0x4400)
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#define SPI1_BASE (APB0_BASE + 0x4500)
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#define SPI2_BASE (APB0_BASE + 0x4600)
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#define SPI3_BASE (APB0_BASE + 0x4700)
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#define SPI4_BASE (APB0_BASE + 0x4800)
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#define SPI5_BASE (APB0_BASE + 0x4b20)
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#define SPI6_BASE (APB0_BASE + 0x4b38)
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#define HG_LED_BASE (APB0_BASE + 0x4b50)
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#define IIC1_BASE (APB0_BASE + 0x4500)
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#define IIC2_BASE (APB0_BASE + 0x4600)
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#define IIC3_BASE (APB0_BASE + 0x4700)
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#define IIC4_BASE (APB0_BASE + 0x4800)
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#define HG_IIS0_BASE (APB0_BASE + 0x80C0)
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#define HG_IIS1_BASE (APB0_BASE + 0x80E0)
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#define HG_PDM_BASE (APB0_BASE + 0x8110)
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#define PRC_BASE (APB0_BASE + 0x5000)
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#define OF_BASE (APB0_BASE + 0x5020)
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#define DVP_BASE (APB0_BASE + 0x5040)
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#define VPP_BASE (APB0_BASE + 0x5080)
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#define JPG0_BASE (APB0_BASE + 0x5100)
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#define JPG1_BASE (APB0_BASE + 0x5200)
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#define MJPEG0_TAB_BASE (APB0_BASE + 0x5180)
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#define MJPEG1_TAB_BASE (APB0_BASE + 0x5280)
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#define CSI2_HOST_BASE (APB0_BASE + 0x5700)
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#define TK_BASE (APB0_BASE + 0x6000)
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#define SCALE0_BASE (APB0_BASE + 0x7000)
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#define SCALE1_BASE (APB0_BASE + 0x7100)
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#define LCDC_BASE (APB0_BASE + 0x7000)
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#define SCALE2_BASE (APB0_BASE + 0x71A0)
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#define SCALE3_BASE (APB0_BASE + 0x7200)
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#define AUDIO_BASE (APB0_BASE + 0x8000)
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#define COMP_BASE (APB0_BASE + 0x9000)
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#define EFUSE_BASE (APB0_BASE + 0xa000)
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#define HG_SYSAES_BASE (APB1_BASE + 0x2000)
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//#define RFADCDIG_BASE (APB1_BASE + 0x4000)
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#define HG_SHA_BASE (APB1_BASE + 0x4000)
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#define WDT_BASE (APB1_BASE + 0x5000)
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#define TIMER_ALL_BASE (APB1_BASE + 0x5128)
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#define TIMER0_BASE (APB1_BASE + 0x5100)
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#define TIMER1_BASE (APB1_BASE + 0x5200)
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#define TIMER2_BASE (APB1_BASE + 0x5300)
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#define TIMER3_BASE (APB1_BASE + 0x5400)
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#define TIMER4_BASE (APB1_BASE + 0x5500)
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//#define TIMER5_BASE (APB1_BASE + 0x5600)
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//#define TIMER6_BASE (APB1_BASE + 0x5700)
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//#define TIMER7_BASE (APB1_BASE + 0x5800)
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#define SUPTMR_BASE (APB1_BASE + 0x5600)
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#define SIMPLE_TIMER0_BASE (APB1_BASE + 0x5B00)
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#define SIMPLE_TIMER1_BASE (APB1_BASE + 0x5B10)
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#define SIMPLE_TIMER2_BASE (APB1_BASE + 0x5B20)
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#define SIMPLE_TIMER3_BASE (APB1_BASE + 0x5B30)
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#define SIMPLE_TIMER4_BASE (APB1_BASE + 0x5B40)
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#define SIMPLE_TIMER5_BASE (APB1_BASE + 0x5B50)
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//#define HG_RTC_BASE (APB1_BASE + 0x8050)
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#define HG_CRC32_BASE (APB1_BASE + 0x7000)
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#define PMU_BASE (APB1_BASE + 0x8000)
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#define LVD_BASE (APB1_BASE + 0x8000)
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#define RFDIG_BASE (APB1_BASE + 0x9000)
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#define ADKEY_BASE (APB1_BASE + 0xa000)
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#define ADKEY1_BASE (APB1_BASE + 0xa00c)
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#define ZH_RFSPI_BASE (APB1_BASE + 0xb000)
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#define RFDIGCAL_BASE (APB1_BASE + 0xd000)
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#define HG_SYSCTRL_BASE (AHB_BASE + 0x0000)
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#define HG_GPIOA_BASE (AHB_BASE + 0x0a00)
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#define HG_GPIOB_BASE (AHB_BASE + 0x0b00)
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#define HG_GPIOC_BASE (AHB_BASE + 0x0c00)
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#define HG_GPIOD_BASE (AHB_BASE + 0x0d00)
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#define HG_GPIOE_BASE (AHB_BASE + 0x0e00)
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#define HG_GPIOF_BASE (AHB_BASE + 0x0f00)
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#define HG_GPIOG_BASE (AHB_BASE + 0x1000)
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#define HG_GPIOH_BASE (AHB_BASE + 0x1100)
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#define M2M_DMA_BASE (AHB_BASE + 0x1200)
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#define M2M_DMA0_BASE (AHB_BASE + 0x1200)
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#define M2M_DMA1_BASE (AHB_BASE + 0x121C)
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#define SYS_MNT_BASE (AHB_BASE + 0x1300)
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#define SDHOST_BASE (AHB_BASE + 0x1400)
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#define LED_TIMER0_BASE (PMU_BASE + 0x000d0)
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#define LED_TIMER1_BASE (PMU_BASE + 0x000d4)
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#define LED_TIMER2_BASE (PMU_BASE + 0x000d8)
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#define LED_TIMER3_BASE (PMU_BASE + 0x000dc)
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#define HG_SUPTMR_COMM_BASE (SUPTMR_BASE )
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#define HG_SUPTMR0_BASE (APB1_BASE + 0x5B00)
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#define HG_SUPTMR1_BASE (APB1_BASE + 0x5B10)
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#define HG_SUPTMR2_BASE (APB1_BASE + 0x5B20)
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#define HG_SUPTMR3_BASE (APB1_BASE + 0x5B30)
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#define HG_SUPTMR4_BASE (APB1_BASE + 0x5B40)
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#define HG_SUPTMR5_BASE (APB1_BASE + 0x5B50)
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#define HG_SDIO20_SLAVE_BASE (AHB_BASE + 0x20000)
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#define MODEM_BASE (AHB_BASE + 0x40000)
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#define LMAC_BASE (AHB_BASE + 0x42000)
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#define HG_GMAC_BASE (AHB_BASE + 0x51000)
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#define HG_USB20_DEVICE_BASE (AHB_BASE + 0xd0000)
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typedef enum {
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HG_AHB_PT_ALL,
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HG_AHB_PT_GPIOA_DEBUNCE,
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HG_AHB_PT_GPIOB_DEBUNCE,
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HG_AHB_PT_GPIOC_DEBUNCE,
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HG_AHB_PT_M2M_DMA,
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HG_AHB_PT_SYS_MNT,
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HG_AHB_PT_SDMMC,
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HG_AHB_PT_SDIO,
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HG_AHB_PT_MODEM,
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HG_AHB_PT_LMAC,
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HG_AHB_PT_GMAC,
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HG_AHB_PT_USB20,
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HG_APB0_PT_ALL,
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HG_APB0_PT_QSPI,
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HG_APB0_PT_OSPI,
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HG_APB0_PT_UART0,
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HG_APB0_PT_UART1,
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HG_APB0_PT_UART4,
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HG_APB0_PT_UART5,
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HG_APB0_PT_SPI0,
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HG_APB0_PT_SPI1,
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HG_APB0_PT_SPI2,
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HG_APB0_PT_SPI3,
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HG_APB0_PT_SPI5,
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HG_APB0_PT_SPI6,
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HG_APB0_PT_LED,
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HG_APB0_PT_IIC0,
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HG_APB0_PT_IIC1,
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HG_APB0_PT_IIC2,
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HG_APB0_PT_IIC3,
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HG_APB0_PT_IIS0,
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HG_APB0_PT_IIS1,
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HG_APB0_PT_PDM,
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HG_APB0_PT_JPEG,
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HG_APB0_PT_DVP,
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HG_APB0_PT_CMP,
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HG_APB0_PT_EFUSE,
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HG_APB1_PT_ALL,
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HG_APB1_PT_AES,
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HG_APB1_PT_WDT,
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HG_APB1_PT_TMR0,
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HG_APB1_PT_TMR1,
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HG_APB1_PT_TMR2,
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HG_APB1_PT_TMR3,
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HG_APB1_PT_STMR,
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HG_APB1_PT_SUPTMR,
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HG_APB1_PT_CRC,
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HG_APB1_PT_PMU,
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HG_APB1_PT_LVD,
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HG_APB1_PT_ADKEY,
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} HG_Peripheral_Type;
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/**
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* @}
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*/
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enum phy_rf_mode {
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INT_PHY_EXT_RF_MODE = 1, //for ext-rf case
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PHY_RF_NORMAL_MODE = 2, //tx4001 ic normal case
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INT_RF_EXT_PHY_MODE = 3, //for transceiver case
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};
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#define EFUSE_OFFSET 3
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#define OSC_CLK 32000000UL
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#define M2M_DMA
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#define IS_DCACHE_ADDR(addr) ((uint32)(addr) >= 0x38000000 && (uint32)(addr) < 0x38f00000) //psram
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#define IS_PSRAM_ADDR(addr) ((uint32)(addr) >= 0x38000000 && (uint32)(addr) < 0x38f00000) //psram
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#ifdef __cplusplus
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}
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#endif
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#endif
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