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pure sdk for main

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This commit is contained in:
divadiow
2025-08-27 09:51:58 +01:00
parent f0d033f1c9
commit 0571416e7c
3283 changed files with 1577720 additions and 1 deletions
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sdk/driver/timer/hgtimer_v4.c
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sdk/driver/timer/hgtimer_v4_hw.h
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#ifndef _HGTIMER_V4_HW_H
#define _HGTIMER_V4_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/***** TIMERx CON Register *****/
/*! Timer IR selection whether lsb first send (for TIMER1/2 only)
*/
#define LL_TIMER_CON_IR_TMR_FST_LSB_SEL (1UL << 29)
/*! Timer IR function logic 0 PWM polarity selection (for TIMER1/2 only)
*/
#define LL_TIMER_CON_IR_ZERO_PWMPOL (1UL << 28)
/*! Timer IR function logic 1 PWM polarity selection (for TIMER1/2 only)
*/
#define LL_TIMER_CON_IR_ONE_PWMPOL (1UL << 27)
/*! Timer IR function enable (for TIMER1/2 only)
*/
#define LL_TIMER_CON_IR_EN (1UL << 26)
/*! PWM polarity selection in TIMER module
*/
#define LL_TIMER_CON_PWMPOL (1UL << 25)
/*! The polarity of capture event 1 is selected: 0 = rising edge, 1 = falling edge.
*/
#define LL_TIMER_CON_CAP1POL(n) ((n & 0x1) << 21)
/*! When the capture event 1 occurs, the value of the CNT is automatically cleared.
*/
#define LL_TIMER_CON_CTRRST1 (1UL << 17)
/*! The number of the Capture register:
* 00 : Capture data store in CAP1
* 01 : Capture data store in CAP1 CAP2
* 10 : Capture data store in CAP1 CAP2 CAP3
* 11 : Capture data store in CAP1 CAP2 CAP3 CAP4
*/
#define LL_TIMER_CON_CAP_CNT(n) (((n)&0x3) << 15)
/*! Capture selection:
* 00 : GPIO
* 01 : GPIO OR
* 10 : compare0 output
* 11 : compare1 output
*/
#define LL_TIMER_CON_CAP_SEL(n) (((n)&0x3) << 13)
/*! Output sync signal selection:
* 00 : CNT value = PRD value
* 01 : CNT value = CMP value
* 10 : Output SYNCI value to SYNCO
* 11 : PWM output is assigned to SYNCO
*/
#define LL_TIMER_CON_SYNCO_SEL(n) (((n)&0x3) << 11)
/*! Synci polarity inversion:
* 1 : Invert
* 0 : not reversed
*/
#define LL_TIMER_CON_SYNCI_POL (1UL << 10)
/*! Synci function selection
* 00 : disable
* 01 : kick start
* 10 : reset
* 11 : gating
*/
#define LL_TIMER_CON_SLAVE_MODE(n) (((n)&0x3) << 8)
/*! Timer prescaler settings:
* 000 : 0 frequency division
* 001 : 2 frequency division
* 010 : 4 frequency division
* 011 : 8 frequency division
* 100 : 16 frequency division
* 101 : 32 frequency division
* 110 : 64 frequency division
* 111 : 128 frequency division
*/
#define LL_TIMER_CON_PSC(n) (((n)&0x7) << 5)
/*! Timer counter source select bits:
* 001 : Internal high speed RC
* 010 : Internal low speed RC
* 011 : External crystal oscillator divided by 2 clocks
* 100 : timer inc pin rising
* 101 : timer inc pin falling
* 110 : timer inc pin rising and falling
* Others : system clock
*/
#define LL_TIMER_CON_INC_SRC_SEL(n) (((n)&0x7) << 2)
/*! Timer mode select bits:
* 00 : timer counter mode
* 01 : timer pwm mode
* 10 : timer capture mode
* Others : reservation
*/
#define LL_TIMER_CON_MODE_SEL(n) (((n)&0x3) << 0)
/***** TIMERx EN Register *****/
/*! TMR enable signal, active high.
*/
#define LL_TIMER_EN_TMREN (1UL << 0)
/***** TIMERx IE Register *****/
/*! Timer IR TX word done interrupt enable (for TIMER1/2 only)
*/
#define LL_TIMER_IE_IR_TX_WORD_DONE_IE (1UL << 11)
/*! Timer IR TX done interrupt enable (for TIMER1/2 only)
*/
#define LL_TIMER_IE_IR_TX_DONE_IE (1UL << 10)
/*! Dma buffer full interrupt enable.
*/
#define LL_TIMER_IE_DMA_FL_IE (1UL << 9)
/*! Dma buffer half full interrupt enable.
*/
#define LL_TIMER_IE_DMA_HF_IE (1UL << 8)
/*! The slave mode trigger mode or reset mode interrupt enable.
*/
#define LL_TIMER_IE_SLAVE_IE (1UL << 7)
/*! When the CNT value is equal to the CMP value, the interrupt is enabled and is valid only in pwm mode.
*/
#define LL_TIMER_IE_CMP_IE (1UL << 6)
/*! When the CNT value is equal to the PRD value, the interrupt is enabled and is valid only in the counter mode/PWM mode.
*/
#define LL_TIMER_IE_PRD_IE (1UL << 5)
/*! When the CNT value overflows (16'hffff), the interrupt is enabled.
*/
#define LL_TIMER_IE_OVF_IE (1UL << 4)
/*! When the capture event 1 occurs, the interrupt is enabled.
@note: none this capture event interrupt
*/
#define LL_TIMER_IE_CAP1_IE (1UL << 0)
/***** TIMERx CNT Register *****/
/*! Count register.
*/
#define LL_TIMER_CNT(n) (((n)&0xFFFFFFFF) << 0)
/***** TIMERx FLG Register *****/
/*! Timer IR TX word done interrupt flag (for TIMER1/2 only)
*/
#define LL_TIMER_IE_IR_TX_WORD_DONE_FLG (1UL << 11)
/*! Timer IR TX done interrupt flag (for TIMER1/2 only)
*/
#define LL_TIMER_IE_IR_TX_DONE_FLG (1UL << 10)
/*! Dma buffer full sign.
*/
#define LL_TIMER_IE_DMA_FL_FLG (1UL << 9)
/*! Dma buffer half full sign.
*/
#define LL_TIMER_IE_DMA_HF_FLG (1UL << 8)
/*! The slave mode flag (reset or trigger only).
*/
#define LL_TIMER_IE_SLAVE_FLG (1UL << 7)
/*! The CNT value is equal to the CMP value flag and is valid only in pwm mode.
*/
#define LL_TIMER_IE_CMP_FLG (1UL << 6)
/*! The CNT value is equal to the PRD value flag and is valid only in counter mode/PWM mode.
*/
#define LL_TIMER_IE_PRD_FLG (1UL << 5)
/*! CNT value overflow (16'hffff) flag.
*/
#define LL_TIMER_IE_OVF_FLG (1UL << 4)
/*! Capture event 1 occurs.
*/
#define LL_TIMER_IE_CAP1_FLG (1UL << 0)
/***** TIMERx CLR Register *****/
/*! Timer IR TX word done interrupt clear (for TIMER1/2 only)
*/
#define LL_TIMER_IE_IR_TX_WORD_DONE_CLR (1UL << 11)
/*! Timer IR TX done interrupt clear (for TIMER1/2 only)
*/
#define LL_TIMER_IE_IR_TX_DONE_CLR (1UL << 10)
/*! Dma buffer full sign clear.
*/
#define LL_TIMER_IE_DMA_FL_CLR (1UL << 9)
/*! Dma buffer half full sign clear.
*/
#define LL_TIMER_IE_DMA_HF_CLR (1UL << 8)
/*! The slave mode flag (reset or trigger only) clear.
*/
#define LL_TIMER_IE_SLAVE_CLR (1UL << 7)
/*! The CNT value is equal to the CMP value flag clear.
*/
#define LL_TIMER_IE_CMP_CLR (1UL << 6)
/*! The CNT value is equal to the PRD value flag clear.
*/
#define LL_TIMER_IE_PRD_CLR (1UL << 5)
/*! The CNT value overflow (16'hffff) flag is cleared.
*/
#define LL_TIMER_IE_OVF_CLR (1UL << 4)
/*! Capture event 1 occurs flag clear.
*/
#define LL_TIMER_IE_CAP1_CLR (1UL << 0)
/***** TIMERx CAP1/PR Register *****/
/*! Capture mode : capture register 1
* Timing mode/PWM mode: Count period register
*/
#define LL_TIMER_CMP1_PR(n) (((n)&0xFFFFFFFF) << 0)
/***** TIMERx CAP2/CMP Register *****/
/*! Capture mode : capture register 2
* Timing mode/PWM mode: compare register
*/
#define LL_TIMER_CMP2_CMP(n) (((n)&0xFFFFFFFF) << 0)
/***** TIMERx CAP3/PR_SD Register *****/
/*! Capture mode : capture register 3
* Timing mode/PWM mode: counting period shadow register
*/
#define LL_TIMER_CMP3_PR_SD(n) (((n)&0xFFFFFFFF) << 0)
/***** TIMERx CAP4/CMP_SD Register *****/
/*! Capture mode : capture register 4
* Timing mode/PWM mode: Compare shadow registers
*/
#define LL_TIMER_CMP4_CMP_SD(n) (((n)&0xFFFFFFFF) << 0)
/***** TIMERx DCCTL Register *****/
/*! Dma mode selection
* 0 : Single mode, after the specified dma length is completed, disable TMR.
* 1 : Loop mode, after the dma length is specified, restart from the start address.
*/
#define LL_TIMER_DMA_LPBK (1UL << 1)
/*! Dma enabled.
*/
#define LL_TIMER_DMA_EN (1UL << 0)
/***** TIMERx DADR Register *****/
/*! Dma starting address.
*/
#define LL_TIMER_DADR_STADR(n) (((n)&0xFFFF) << 0)
/***** TIMERx DLEN Register *****/
/*! Dma buffer length (32bit), if the buffer is n, the configuration is n-1;
*/
#define LL_TIMER_DLEN_LEN(n) (((n)&0xFFFF) << 0)
/***** TIMERx DCNT Register *****/
/*! The number of dma data is valid.
*/
#define LL_TIMER_DCNT_CNT(n) (((n)&0xFFFF) << 0)
/***** TIMER ALLCON Register *****/
/*! The timer3 sync count value is cleared.
*/
#define LL_TIMER_ALLCON_TMR3_SYNC (1UL << 11)
/*! The timer2 sync count value is cleared.
*/
#define LL_TIMER_ALLCON_TMR2_SYNC (1UL << 10)
/*! The timer1 sync count value is cleared.
*/
#define LL_TIMER_ALLCON_TMR1_SYNC (1UL << 9)
/*! The timer0 sync count value is cleared.
*/
#define LL_TIMER_ALLCON_TMR0_SYNC (1UL << 8)
/*! Timer3 starts counting.
*/
#define LL_TIMER_ALLCON_TMR3_KICK (1UL << 3)
/*! Timer2 starts counting.
*/
#define LL_TIMER_ALLCON_TMR2_KICK (1UL << 2)
/*! Timer1 starts counting.
*/
#define LL_TIMER_ALLCON_TMR1_KICK (1UL << 1)
/*! Timer0 starts counting.
*/
#define LL_TIMER_ALLCON_TMR0_KICK (1UL << 0)
/*! Configure the trigger path for the sync count of TIMER.
*/
#define LL_TIMER_ALLCON_SYNC_COUNT_ALL(n) (((n)&0x3F) << 8)
/*! Configure the synchronous trigger path of TIMER.
*/
#define LL_TIMER_ALLCON_KICK_ALL(n) (((n)&0x3F) << 0)
struct hgtimer_v4_hw {
__IO uint32_t TMR_CON;
__IO uint32_t TMR_EN;
__IO uint32_t TMR_IE;
__IO uint32_t TMR_CNT;
__IO uint32_t TMR_FLG;
__IO uint32_t TMR_CLR;
__IO uint32_t TMR_CAP1;
__IO uint32_t TMR_CAP2;
__IO uint32_t TMR_CAP3;
__IO uint32_t TMR_CAP4;
/* The following registers only for timer1 & timer2 */
__IO uint32_t TMR_DCTL;
__IO uint32_t TMR_DADR;
__IO uint32_t TMR_DLEN;
__IO uint32_t TMR_DCNT;
__IO uint32_t TMR_IR_BCNT;
};
#ifdef __cplusplus
}
#endif
#endif /* _HGTIMER_V4_HW_H */
sdk/driver/timer/hgtimer_v5.c
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/**
* @file hgtimer_v5.c
* @author bxd
* @brief low power led timer
* @version
* TXW80X
* @date 2023-08-02
*
* @copyright Copyright (c) 2023
*
*/
#include "typesdef.h"
#include "list.h"
#include "errno.h"
#include "dev.h"
#include "osal/irq.h"
#include "osal/string.h"
#include "hal/timer_device.h"
#include "hal/pwm.h"
#include "dev/pwm/hgpwm_v0.h"
#include "dev/timer/hgtimer_v5.h"
#include "hgtimer_v5_hw.h"
/**********************************************************************************/
/* LOW LAYER FUNCTION */
/**********************************************************************************/
#define LL_LED_TIMER_CHECK_COUNT_OV_INTERRUPT_ENABLE(p_timer) (LED_TIMER0_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 8)) : \
((LED_TIMER1_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 9)) : \
((LED_TIMER2_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 10)) : \
((LED_TIMER3_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 11)) : 0)))
static inline void hgtimer_v5_irq_config(struct hgtimer_v5 *dev, uint32 enable) {
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 pos = 0;
uint32 addr = (uint32)(&hw->LED_TMR_CON0);
//Confirm which led_timer will be enable interrupt
if (LED_TIMER0_BASE == addr) {
pos = 8;
} else if (LED_TIMER1_BASE == addr) {
pos = 9;
} else if (LED_TIMER2_BASE == addr) {
pos = 10;
} else if (LED_TIMER3_BASE == addr){
pos = 11;
}
sysctrl_unlock();
if (enable) {
SYSCTRL->SYS_CON15 |= (1 << pos);
} else {
SYSCTRL->SYS_CON15 &= ~(1 << pos);
}
sysctrl_lock();
}
/**********************************************************************************/
/* PWM FUNCTION START */
/**********************************************************************************/
static int32 hgtimer_v5_pwm_switch_func_cmd(enum hgpwm_v0_func_cmd param) {
switch (param) {
case (HGPWM_V0_FUNC_CMD_INIT):
return HGTIMER_V5_PWM_FUNC_CMD_INIT;
break;
case (HGPWM_V0_FUNC_CMD_DEINIT):
return HGTIMER_V5_PWM_FUNC_CMD_DEINIT;
break;
case (HGPWM_V0_FUNC_CMD_START):
return HGTIMER_V5_PWM_FUNC_CMD_START;
break;
case (HGPWM_V0_FUNC_CMD_STOP):
return HGTIMER_V5_PWM_FUNC_CMD_STOP;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM):
return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE):
return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE;
break;
case (HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD):
return HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD;
break;
case (HGPWM_V0_FUNC_CMD_RELEASE_IRQ):
return HGTIMER_V5_PWM_FUNC_CMD_RELEASE_IRQ;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER):
return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PRESCALER;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY;
break;
default:
return -1;
break;
}
}
static int32 hgtimer_v5_pwm_switch_period_duty(uint32 period, uint32 duty, uint32 *p_period, uint32 *p_duty) {
uint32 pmu_con0_tmp = 0;
uint32 period_us_to_reg = 0;
uint32 duty_us_to_reg = 0;
pmu_con0_tmp = PMU->PMUCON0;
/* make sure the period */
switch ((pmu_con0_tmp & (0x3 << 25)) >> 25) {
/* rc128k_pre */
case (0):
period_us_to_reg = ((128000*period) / 1000000);
duty_us_to_reg = ((128000*duty ) / 1000000);
if (period_us_to_reg && duty_us_to_reg) {
*p_period = period_us_to_reg;
*p_duty = duty_us_to_reg;
return 0;
} else {
return -1;
}
break;
/* x32m_div_clk */
case (1):
period_us_to_reg = ((32000000*period) / 1000000);
duty_us_to_reg = ((32000000*duty ) / 1000000);
if (period_us_to_reg && duty_us_to_reg) {
*p_period = period_us_to_reg;
*p_duty = duty_us_to_reg;
return 1;
} else {
return -1;
}
break;
/* rc10m_clk */
case (2):
period_us_to_reg = ((10000000*period) / 1000000);
duty_us_to_reg = ((10000000*duty ) / 1000000);
if (period_us_to_reg && duty_us_to_reg) {
*p_period = period_us_to_reg;
*p_duty = duty_us_to_reg;
return 2;
} else {
return -1;
}
break;
/* lxosc32k_clk */
case (3):
period_us_to_reg = ((32000*period) / 1000000);
duty_us_to_reg = ((32000*duty ) / 1000000);
if (period_us_to_reg && duty_us_to_reg) {
*p_period = period_us_to_reg;
*p_duty = duty_us_to_reg;
return 3;
} else {
return -1;
}
break;
default:
return -EINVAL;
break;
}
}
static inline int32 hgtimer_v5_pwm_func_init(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
uint32 period_to_reg = 0;
uint32 duty_to_reg = 0;
uint32 led_timer_con0_tmp = 0;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
if (dev->opened) {
return -EBUSY;
}
if (pin_func(dev->dev.dev.dev_id , 1) != RET_OK) {
return RET_ERR;
}
/* make sure the period & duty */
hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &duty_to_reg);
hgtimer_v5_irq_config(dev, 0);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
/* config reg */
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(1 );
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0 );
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(duty_to_reg);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
dev->opened = 1;
dev->pwm_en = 1;
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_deinit(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
if ((!dev->opened) || (!dev->pwm_en)) {
return RET_OK;
}
irq_disable(dev->irq_num);
pin_func(dev->dev.dev.dev_id , 0);
hgtimer_v5_irq_config(dev, 0);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
dev->opened = 0;
dev->pwm_en = 0;
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_start(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->pwm_en) {
return RET_ERR;
}
led_timer_con0_tmp |= LL_LED_TIMER_CON0_TMR_EN(1);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_stop(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->pwm_en) {
return RET_ERR;
}
led_timer_con0_tmp &= ~ LL_LED_TIMER_CON0_TMR_EN(1);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_ioctl_set_period_duty(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
uint32 period_to_reg = 0;
uint32 duty_to_reg = 0;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->pwm_en) {
return RET_ERR;
}
if ((p_config->duty < 0) || ((p_config->duty) > (p_config->period))) {
return RET_ERR;
}
/* make sure the period & duty */
if ((-1) == hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &duty_to_reg)) {
return -EINVAL;
};
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(duty_to_reg);
/* led timer must stop to config period & duty */
hgtimer_v5_pwm_func_stop(dev, p_config);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
hgtimer_v5_pwm_func_start(dev, p_config);
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_ioctl_set_single_incream(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
uint32 period_to_reg = 0;
uint32 none = 50; /* just for through the "func_switch_period_duty", no use */
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->pwm_en) {
return RET_ERR;
}
/* make sure the pwm step > 0 */
if (!p_config->duty) {
return -EINVAL;
}
/* make sure the period & duty */
if ((-1) == hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &none)) {
return -EINVAL;
}
/* config reg */
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(2);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(p_config->duty);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_ioctl_set_incream_decrease(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
uint32 period_to_reg = 0;
uint32 none = 50; /* just for through the "func_switch_period_duty", no use */
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->pwm_en) {
return RET_ERR;
}
/* make sure the pwm step > 0 */
if (!p_config->duty) {
return -EINVAL;
}
/* make sure the period & duty */
if ((-1) == hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &none)) {
return -EINVAL;
}
/* config reg */
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(3);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(p_config->duty);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_cmd_ioctl_set_prescaler(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->pwm_en) {
return RET_ERR;
}
led_timer_con0_tmp = (led_timer_con0_tmp &~ (LL_LED_TIMER_CON0_TMR_PSR(0xF))) | (LL_LED_TIMER_CON0_TMR_PSR(p_config->param1));
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_cmd_ioctl_set_period_duty_immediately(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config)
{
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_request_irq_period(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
if (!dev->pwm_en) {
return RET_ERR;
}
dev->_pwm_irq_hdl = p_config->irq_hdl;
dev->irq_data = p_config->irq_data;
hgtimer_v5_irq_config(dev, 1);
irq_enable(dev->irq_num);
return RET_OK;
}
static inline int32 hgtimer_v5_pwm_func_release_irq(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
if (!dev->pwm_en) {
return RET_ERR;
}
irq_disable(dev->irq_num);
dev->_pwm_irq_hdl = NULL;
dev->irq_data = 0;
hgtimer_v5_irq_config(dev, 0);
return RET_OK;
}
static int32 hgtimer_v5_pwm_config(struct hgtimer_v5 *dev, uint32 config, uint32 param) {
struct hgpwm_v0_config *p_config;
int32 hgtimer_v5_pwm_func_cmd = 0;
int32 ret_val = RET_OK;
/* Make sure the config struct pointer */
if (!config) {
return -EINVAL;
}
p_config = (struct hgpwm_v0_config*)config;
hgtimer_v5_pwm_func_cmd = hgtimer_v5_pwm_switch_func_cmd(p_config->func_cmd);
if ((-1) == hgtimer_v5_pwm_func_cmd) {
return -EINVAL;
}
switch (hgtimer_v5_pwm_func_cmd) {
case (HGTIMER_V5_PWM_FUNC_CMD_INIT):
ret_val = hgtimer_v5_pwm_func_init(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_DEINIT):
ret_val = hgtimer_v5_pwm_func_deinit(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_START):
ret_val = hgtimer_v5_pwm_func_start(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_STOP):
ret_val = hgtimer_v5_pwm_func_stop(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
ret_val = hgtimer_v5_pwm_func_ioctl_set_period_duty(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM):
ret_val = hgtimer_v5_pwm_func_ioctl_set_single_incream(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE):
ret_val = hgtimer_v5_pwm_func_ioctl_set_incream_decrease(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD):
ret_val = hgtimer_v5_pwm_func_request_irq_period(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_RELEASE_IRQ):
ret_val = hgtimer_v5_pwm_func_release_irq(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PRESCALER):
ret_val = hgtimer_v5_pwm_func_cmd_ioctl_set_prescaler(dev, p_config);
break;
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
ret_val = hgtimer_v5_pwm_func_cmd_ioctl_set_period_duty_immediately(dev, p_config);
break;
default:
ret_val = -ENOTSUPP;
break;
}
return ret_val;
}
/**********************************************************************************/
/* PWM FUNCTION END */
/**********************************************************************************/
/**********************************************************************************/
/* COUNTER FUNCTION START */
/**********************************************************************************/
static int32 hgtimer_v5_counter_switch_hal_type(struct hgtimer_v5 *dev, enum timer_type param) {
switch (param) {
case (TIMER_TYPE_ONCE):
dev->type = HGTIMER_V5_TYPE_ONCE;
return 0;
break;
case (TIMER_TYPE_PERIODIC):
dev->type = HGTIMER_V5_TYPE_PERIODIC;
return 1;
break;
default:
return -1;
break;
}
}
static int32 hgtimer_v5_counter_switch_tmo_us(uint32 tmo_us) {
uint32 pmu_con0_tmp = 0;
uint32 tmo_us_to_reg = 0;
pmu_con0_tmp = PMU->PMUCON0;
/* make sure the period */
switch ((pmu_con0_tmp & (0x3 << 25)) >> 25) {
/* rc128k_pre */
case (0):
tmo_us_to_reg = ((128000*tmo_us) / 1000000);
if (tmo_us_to_reg) {
return tmo_us_to_reg;
} else {
return -1;
}
break;
/* x32m_div_clk */
case (1):
tmo_us_to_reg = ((32000000*tmo_us) / 1000000);
if (tmo_us_to_reg) {
return tmo_us_to_reg;
} else {
return -1;
}
break;
/* rc10m_clk */
case (2):
tmo_us_to_reg = ((10000000*tmo_us) / 1000000);
if (tmo_us_to_reg) {
return tmo_us_to_reg;
} else {
return -1;
}
break;
/* lxosc32k_clk */
case (3):
tmo_us_to_reg = ((32000*tmo_us) / 1000000);
if (tmo_us_to_reg) {
return tmo_us_to_reg;
} else {
return -1;
}
break;
default:
return -EINVAL;
break;
}
}
static int32 hgtimer_v5_counter_set_psc(struct hgtimer_v5 *timer, uint32 psc)
{
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = 0;
if (!dev->counter_en) {
return RET_ERR;
}
led_timer_con0_tmp = hw->LED_TMR_CON0;
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F)) | LL_LED_TIMER_CON0_TMR_PSR(psc);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
return RET_OK;
}
static int32 hgtimer_v5_counter_func_open(struct timer_device *timer, enum timer_type type, uint32 flags) {
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = 0;
if (dev->opened) {
return -EBUSY;
}
if ((-1) == hgtimer_v5_counter_switch_hal_type(dev, type)) {
return RET_ERR;
}
irq_enable(dev->irq_num);
hgtimer_v5_irq_config(dev, 0);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
switch (dev->type) {
/* TIMER_TYPE_ONCE */
case (HGTIMER_V5_TYPE_ONCE):
/* TIMER_TYPE_PERIODIC */
case (HGTIMER_V5_TYPE_PERIODIC):
/* TIMER_TYPE_COUNTER */
case (HGTIMER_V5_TYPE_COUNTER):
//Config reg
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(0);
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0 );
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
break;
default:
return RET_ERR;
break;
}
dev->opened = 1;
dev->counter_en = 1;
return RET_OK;
}
static int32 hgtimer_v5_counter_func_close(struct timer_device *timer) {
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
if ((!dev->opened) || (!dev->counter_en)) {
return RET_OK;
}
irq_disable(dev->irq_num);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
dev->opened = 0;
dev->counter_en = 0;
return RET_OK;
}
static int32 hgtimer_v5_counter_func_start(struct timer_device *timer, uint32 period_clkpd_cnt, timer_cb_hdl cb, uint32 cb_data) {
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
int32 tmo_us_to_reg = 0;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->counter_en) {
return RET_ERR;
}
/* make sure the period */
// tmo_us_to_reg = hgtimer_v5_counter_switch_tmo_us(tmo_us);
// if ((-1) == tmo_us_to_reg) {
// return -EINVAL;
// }
tmo_us_to_reg = period_clkpd_cnt;
if (!tmo_us_to_reg || (tmo_us_to_reg > 0xFFF)) {
return RET_ERR;
}
switch (dev->type) {
/* TIMER_TYPE_ONCE */
case (HGTIMER_V5_TYPE_ONCE):
dev->counter_once_en = 1;
/* config reg */
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF)) | LL_LED_TIMER_CON0_TMR_PR(tmo_us_to_reg);
led_timer_con0_tmp |= LL_LED_TIMER_CON0_TMR_EN(1);
if (cb) {
dev->_counter_irq_hdl = cb;
dev->irq_data = cb_data;
hgtimer_v5_irq_config(dev, 1);
}
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
break;
/* TIMER_TYPE_PERIODIC */
case (HGTIMER_V5_TYPE_PERIODIC):
/* TIMER_TYPE_COUNTER */
case (HGTIMER_V5_TYPE_COUNTER):
dev->counter_period_en = 1;
/* config reg */
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF)) | LL_LED_TIMER_CON0_TMR_PR(tmo_us_to_reg);
led_timer_con0_tmp |= LL_LED_TIMER_CON0_TMR_EN(1);
if (cb) {
dev->_counter_irq_hdl = cb;
dev->irq_data = cb_data;
hgtimer_v5_irq_config(dev, 1);
}
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
break;
default:
return RET_ERR;
break;
}
return RET_OK;
}
static int32 hgtimer_v5_counter_func_stop(struct timer_device *timer) {
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
if (!dev->counter_en) {
return RET_ERR;
}
led_timer_con0_tmp &= ~ LL_LED_TIMER_CON0_TMR_EN(1);
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
return RET_OK;
}
static int32 hgtimer_v5_counter_func_ioctl(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2) {
int32 ret_val = RET_OK;
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
switch (cmd) {
case (HGPWM_V0_FUNC_CMD_MASK):
ret_val = hgtimer_v5_pwm_config(dev, param1, 0);
break;
case (TIMER_SET_CLK_PSC):
ret_val = hgtimer_v5_counter_set_psc(dev, param1);
break;
default:
ret_val = RET_ERR;
break;
}
return ret_val;
}
/**********************************************************************************/
/* COUNTER FUNCTION END */
/**********************************************************************************/
static inline void hgtimer_v5_clear_count_ov_pending(struct hgtimer_v5 *dev) {
uint32 pndclr_temp = PMU->PNDCLR;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
uint32 addr = (uint32)(&hw->LED_TMR_CON0);
//Confirm which led timer pending will be clear
if (LED_TIMER0_BASE == addr) {
pndclr_temp |= (1 << 25);
} else if (LED_TIMER1_BASE == addr) {
pndclr_temp |= (1 << 26);
} else if (LED_TIMER2_BASE == addr) {
pndclr_temp |= (1 << 27);
} else if (LED_TIMER3_BASE == addr) {
pndclr_temp |= (1 << 28);
}
pmu_reg_write((uint32)&PMU->PNDCLR, pndclr_temp);
}
static void hgtimer_v5_irq_handler(void *data) {
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)data;
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
if ((hw->LED_TMR_CON0 & LL_LED_TIMER_CON0_TMR_PENDING(1)) &&
LL_LED_TIMER_CHECK_COUNT_OV_INTERRUPT_ENABLE(&(hw->LED_TMR_CON0))) {
hgtimer_v5_clear_count_ov_pending(dev);
/* pwm mode irq */
if (dev->opened && dev->pwm_en && dev->_pwm_irq_hdl) {
dev->_pwm_irq_hdl(PWM_IRQ_FLAG_PERIOD, dev->irq_data);
}
/* counter mode irq */
if (dev->opened && dev->counter_en) {
if (dev->counter_once_en) {
dev->counter_once_en = 0;
/* close timer & interrupt */
hgtimer_v5_irq_config(dev, 0);
}
if (dev->_counter_irq_hdl) {
dev->_counter_irq_hdl(dev->irq_data, TIMER_INTR_PERIOD);
}
}
}
}
static const struct timer_hal_ops timer_v5_ops = {
.open = hgtimer_v5_counter_func_open,
.close = hgtimer_v5_counter_func_close,
.start = hgtimer_v5_counter_func_start,
.stop = hgtimer_v5_counter_func_stop,
.ioctl = hgtimer_v5_counter_func_ioctl,
};
int32 hgtimer_v5_attach(uint32 dev_id, struct hgtimer_v5 *timer) {
timer->opened = 0;
timer->_counter_irq_hdl = NULL;
timer->_pwm_irq_hdl = NULL;
timer->irq_data = 0;
timer->dev.dev.ops = (const struct devobj_ops *)&timer_v5_ops;
request_irq(timer->irq_num, hgtimer_v5_irq_handler, timer);
dev_register(dev_id, (struct dev_obj *)timer);
return RET_OK;
}
sdk/driver/timer/hgtimer_v5_hw.h
+40
View File
@@ -0,0 +1,40 @@
#ifndef _HGTIMER5_HW_H
#define _HGTIMER5_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/***** LED_TIMER TIMERx CON0 Register *****/
/*! LED_TIMER Period registers. Timer count always start at 0.
*/
#define LL_LED_TIMER_CON0_TMR_PR(n) ((n & 0xFFF) << 20)
/*! LED_TIMER PWM registers. Write this always configure same data to PWM register.
*/
#define LL_LED_TIMER_CON0_TMR_STEP(n) ((n & 0xFFF) << 8)
/*! LED_TIMER Prescaler registers.
*/
#define LL_LED_TIMER_CON0_TMR_PSR(n) ((n & 0x00F) << 4)
/*! LED_TIMER pending.
*/
#define LL_LED_TIMER_CON0_TMR_PENDING(n) ((n & 0x001) << 3)
/*! LED_TIMER Mode registers.
*/
#define LL_LED_TIMER_CON0_TMR_MODE(n) ((n & 0x003) << 1)
/*! LED_TIMER EN registers.
*/
#define LL_LED_TIMER_CON0_TMR_EN(n) ((n & 0x001) << 0)
struct hgtimer_v5_hw {
__IO uint32_t LED_TMR_CON0;
};
#ifdef __cplusplus
}
#endif
#endif /* */
sdk/driver/timer/hgtimer_v6.c
+792
View File
@@ -0,0 +1,792 @@
/**
* @file hgtimer_v6.c
* @author bxd
* @brief super timer
* @version
* TXW80X
* @date 2023-08-02
*
* @copyright Copyright (c) 2023
*
*/
#include "typesdef.h"
#include "list.h"
#include "errno.h"
#include "dev.h"
#include "osal/irq.h"
#include "osal/string.h"
#include "hal/timer_device.h"
#include "hal/pwm.h"
#include "dev/pwm/hgpwm_v0.h"
#include "dev/timer/hgtimer_v6.h"
#include "hgtimer_v6_hw.h"
/**********************************************************************************/
/* COMM FUNCTION */
/**********************************************************************************/
#define HGTIMER_V6_HW_SUPTMRCON0_BIT (\
LL_STRM_CON0_SUPTMR01_SYNC_MD_SEL(0x3) | \
LL_STRM_CON0_SUPTMR23_SYNC_MD_SEL(0x3) | \
LL_STRM_CON0_SUPTMR45_SYNC_MD_SEL(0x3) | \
LL_SUPTMR_CON0_SUPTMR_GP0_EN | \
LL_SUPTMR_CON0_SUPTMR_GP1_EN | \
LL_SUPTMR_CON0_CPMC_SEL(0x1) | \
LL_SUPTMR_CON0_LOAD_SEL(0x1) | \
LL_SUPTMR_CON0_SUPTMR0_CNT_TYPE_SEL(0x1) | \
LL_SUPTMR_CON0_SUPTMR1_CNT_TYPE_SEL(0x1) | \
LL_SUPTMR_CON0_SUPTMR2_CNT_TYPE_SEL(0x1) | \
LL_SUPTMR_CON0_SUPTMR3_CNT_TYPE_SEL(0x1) | \
LL_SUPTMR_CON0_SUPTMR4_CNT_TYPE_SEL(0x1) | \
LL_SUPTMR_CON0_SUPTMR5_CNT_TYPE_SEL(0x1) \
)
static int32 hgtimer_v6_switch_suptmr_index(struct hgtimer_v6 *dev)
{
switch ((uint32)(dev->hw_suptmrx)) {
case ((uint32)HG_SUPTMR0_BASE):
return 0;
break;
case ((uint32)HG_SUPTMR1_BASE):
return 1;
break;
case ((uint32)HG_SUPTMR2_BASE):
return 2;
break;
case ((uint32)HG_SUPTMR3_BASE):
return 3;
break;
case ((uint32)HG_SUPTMR4_BASE):
return 4;
break;
case ((uint32)HG_SUPTMR5_BASE):
return 5;
break;
default:
return -1;
break;
}
}
/**********************************************************************************/
/* PWM FUNCTION START */
/**********************************************************************************/
static int32 hgtimer_v6_pwm_switch_func_cmd(enum hgpwm_v0_func_cmd param)
{
switch (param) {
case (HGPWM_V0_FUNC_CMD_INIT):
return HGTIMER_V6_PWM_FUNC_CMD_INIT;
break;
case (HGPWM_V0_FUNC_CMD_DEINIT):
return HGTIMER_V6_PWM_FUNC_CMD_DEINIT;
break;
case (HGPWM_V0_FUNC_CMD_START):
return HGTIMER_V6_PWM_FUNC_CMD_START;
break;
case (HGPWM_V0_FUNC_CMD_STOP):
return HGTIMER_V6_PWM_FUNC_CMD_STOP;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
return HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY;
break;
case (HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE):
return HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE;
break;
case (HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD):
return HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD;
break;
case (HGPWM_V0_FUNC_CMD_RELEASE_IRQ):
return HGTIMER_V6_PWM_FUNC_CMD_RELEASE_IRQ;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER):
return HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PRESCALER;
break;
case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
return HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY;
break;
default:
return -1;
break;
}
}
static inline int32 hgtimer_v6_pwm_func_init(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if (dev->opened) {
return -EBUSY;
}
if (pin_func(dev->dev.dev.dev_id, 1) != RET_OK) {
return RET_ERR;
}
if ((p_config->duty < 0) || ((p_config->duty) > (p_config->period))) {
return RET_ERR;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
/* config regs */
switch ((uint32)(dev->hw_suptmrx)) {
case ((uint32)HG_SUPTMR0_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR0_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR1_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR1_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR2_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR2_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR3_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR3_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR4_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR4_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR5_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR5_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
default:
return RET_ERR;
break;
}
/* config PWMCON: PWMVA; PWMEN */
hw_comm->SUPTMR_PWMCON &= ~(((1) << (6 + index)) | ((0) << (0 + index)));
/* config period */
hw_suptmrx->PR = p_config->period;
/* config compare */
hw_suptmrx->CMP = p_config->duty;
/* clear current cnt */
hw_suptmrx->CNT = 0;
dev->opened = 1;
dev->pwm_en = 1;
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_deinit(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if ((!dev->opened) || (!dev->pwm_en)) {
return RET_OK;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
irq_disable(dev->irq_num);
pin_func(dev->dev.dev.dev_id, 0);
/* comm reg CON1: CNTEN; */
hw_comm->SUPTMR_CON1 &= ~((1) << (0 + index));
/* comm reg PWMCON: PWMEN; */
hw_comm->SUPTMR_PWMCON &= ~((1) << (0 + index));
hw_suptmrx->CON = 0;
/* clear current cnt */
hw_suptmrx->CNT = 0;
dev->opened = 0;
dev->pwm_en = 0;
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_start(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if (!dev->pwm_en) {
return RET_ERR;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
/* comm reg PWMCON: PWMEN*/
hw_comm->SUPTMR_PWMCON |= (1) << (0 + index);
/* comm reg CON1: CNTEN */
hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_stop(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if (!dev->pwm_en) {
return RET_ERR;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
/* comm reg PWMCON: PWMEN*/
hw_comm->SUPTMR_PWMCON &= ~((1) << (0 + index));
/* comm reg CON1: CNTEN */
hw_comm->SUPTMR_CON1 &= ~((1) << (0 + index));
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_ioctl_set_period_duty(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if (!dev->pwm_en) {
return RET_ERR;
}
if ((p_config->duty < 0) || ((p_config->duty) > (p_config->period))) {
return RET_ERR;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
/* config period */
hw_suptmrx->PR = p_config->period;
/* config compare */
hw_suptmrx->CMP = p_config->duty;
/* clear current cnt */
hw_suptmrx->CNT = 0;
/* comm reg CON1: LOADEN */
hw_comm->SUPTMR_CON1 |= (1) << (8 + index);
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_cmd_ioctl_set_prescaler(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
if (!dev->pwm_en) {
return RET_ERR;
}
hw_suptmrx->CON = (hw_suptmrx->CON &~ (LL_SUPTMRx_CON_PSC(0x3FF))) | (LL_SUPTMRx_CON_PSC(p_config->param1));
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_cmd_ioctl_set_period_duty_immediately(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if (!dev->pwm_en) {
return RET_ERR;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
/* comm reg PWMCON: PWMEN*/
hw_comm->SUPTMR_PWMCON &= ~((1) << (0 + index));
/* comm reg CON1: CNTEN */
hw_comm->SUPTMR_CON1 &= ~((1) << (0 + index));
hw_suptmrx->CNT = 0;
hw_suptmrx->PR = p_config->period;
hw_suptmrx->CMP = p_config->duty;
/* comm reg PWMCON: PWMEN*/
hw_comm->SUPTMR_PWMCON |= (1) << (0 + index);
/* comm reg CON1: CNTEN */
hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_request_irq_compare(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
if (!dev->pwm_en) {
return RET_ERR;
}
dev->_pwm_irq_hdl = p_config->irq_hdl;
dev->irq_data = p_config->irq_data;
hw_suptmrx->CON |= LL_SUPTMRx_CON_CMPA_IE;
irq_enable(dev->irq_num);
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_request_irq_period(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
if (!dev->pwm_en) {
return RET_ERR;
}
dev->_pwm_irq_hdl = p_config->irq_hdl;
dev->irq_data = p_config->irq_data;
hw_suptmrx->CON |= LL_SUPTMRx_CON_UD_IE;
irq_enable(dev->irq_num);
return RET_OK;
}
static inline int32 hgtimer_v6_pwm_func_release_irq(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
{
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
if (!dev->pwm_en) {
return RET_ERR;
}
irq_disable(dev->irq_num);
dev->_pwm_irq_hdl = NULL;
dev->irq_data = 0;
hw_suptmrx->CON &= ~(LL_SUPTMRx_CON_UD_IE | LL_SUPTMRx_CON_UD_IE);
return RET_OK;
}
static int32 hgtimer_v6_pwm_config(struct hgtimer_v6 *dev, uint32 config, uint32 param)
{
struct hgpwm_v0_config *p_config;
int32 hgtimer_v6_pwm_func_cmd = 0;
int32 ret_val = RET_OK;
/* Make sure the config struct pointer */
if (!config) {
return -EINVAL;
}
p_config = (struct hgpwm_v0_config *)config;
hgtimer_v6_pwm_func_cmd = hgtimer_v6_pwm_switch_func_cmd(p_config->func_cmd);
if ((-1) == hgtimer_v6_pwm_func_cmd) {
return -EINVAL;
}
switch (hgtimer_v6_pwm_func_cmd) {
case (HGTIMER_V6_PWM_FUNC_CMD_INIT):
ret_val = hgtimer_v6_pwm_func_init(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_DEINIT):
ret_val = hgtimer_v6_pwm_func_deinit(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_START):
ret_val = hgtimer_v6_pwm_func_start(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_STOP):
ret_val = hgtimer_v6_pwm_func_stop(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
ret_val = hgtimer_v6_pwm_func_ioctl_set_period_duty(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE):
ret_val = hgtimer_v6_pwm_func_request_irq_compare(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD):
ret_val = hgtimer_v6_pwm_func_request_irq_period(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_RELEASE_IRQ):
ret_val = hgtimer_v6_pwm_func_release_irq(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PRESCALER):
ret_val = hgtimer_v6_pwm_func_cmd_ioctl_set_prescaler(dev, p_config);
break;
case (HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
ret_val = hgtimer_v6_pwm_func_cmd_ioctl_set_period_duty_immediately(dev, p_config);
break;
default:
ret_val = -ENOTSUPP;
break;
}
return ret_val;
}
/**********************************************************************************/
/* PWM FUNCTION END */
/**********************************************************************************/
/**********************************************************************************/
/* COUNTER FUNCTION START */
/**********************************************************************************/
static int32 hgtimer_v6_counter_switch_hal_type(struct hgtimer_v6 *dev, enum timer_type param)
{
switch (param) {
case (TIMER_TYPE_ONCE):
dev->type = HGTIMER_V6_TYPE_ONCE;
return 0;
break;
case (TIMER_TYPE_PERIODIC):
dev->type = HGTIMER_V6_TYPE_PERIODIC;
return 1;
break;
default:
return -1;
break;
}
}
static int32 hgtimer_v6_counter_set_psc(struct hgtimer_v6 *timer, uint32 psc)
{
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
if (!dev->counter_en) {
return RET_ERR;
}
hw_suptmrx->CON = (hw_suptmrx->CON & ~ LL_SUPTMRx_CON_PSC(0x3FF)) | LL_SUPTMRx_CON_PSC(psc);
return RET_OK;
}
static int32 hgtimer_v6_counter_func_open(struct timer_device *timer, enum timer_type type, uint32 flags)
{
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
if (dev->opened) {
return -EBUSY;
}
if ((-1) == hgtimer_v6_counter_switch_hal_type(dev, type)) {
return RET_ERR;
}
irq_enable(dev->irq_num);
switch (dev->type) {
/* TIMER_TYPE_ONCE */
case (HGTIMER_V6_TYPE_ONCE):
/* TIMER_TYPE_PERIODIC */
case (HGTIMER_V6_TYPE_PERIODIC):
/* TIMER_TYPE_COUNTER */
case (HGTIMER_V6_TYPE_COUNTER):
/* config regs */
switch ((uint32)(dev->hw_suptmrx)) {
case ((uint32)HG_SUPTMR0_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR0_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR1_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR1_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR2_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR2_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR3_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR3_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR4_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR4_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
case ((uint32)HG_SUPTMR5_BASE):
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR5_CNT_MOD_SEL(1);
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
break;
default:
return RET_ERR;
break;
}
break;
default:
return RET_ERR;
break;
}
/* clear current cnt */
hw_suptmrx->CNT = 0;
dev->opened = 1;
dev->counter_en = 1;
return RET_OK;
}
static int32 hgtimer_v6_counter_func_close(struct timer_device *timer)
{
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if ((!dev->opened) || (!dev->counter_en)) {
return RET_OK;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
irq_disable(dev->irq_num);
/* config regs */
hw_comm->SUPTMR_CON1 &= ~(1) << (0 + index);
hw_suptmrx->CON = 0;
dev->opened = 0;
dev->counter_en = 0;
return RET_OK;
}
static int32 hgtimer_v6_counter_func_start(struct timer_device *timer, uint32 period_sysclkpd_cnt, timer_cb_hdl cb, uint32 cb_data)
{
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if (!dev->counter_en) {
return RET_ERR;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
switch (dev->type) {
/* TIMER_TYPE_ONCE */
case (HGTIMER_V6_TYPE_ONCE):
dev->counter_once_en = 1;
/* config period */
hw_suptmrx->PR = period_sysclkpd_cnt;
/* clear current cnt */
hw_suptmrx->CNT = 0;
if (cb) {
dev->_counter_irq_hdl = cb;
dev->irq_data = cb_data;
hw_suptmrx->CON |= LL_SUPTMRx_CON_OV_IE;
}
hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
break;
/* TIMER_TYPE_PERIODIC */
case (HGTIMER_V6_TYPE_PERIODIC):
/* TIMER_TYPE_COUNTER */
case (HGTIMER_V6_TYPE_COUNTER):
dev->counter_period_en = 1;
/* config period */
hw_suptmrx->PR = period_sysclkpd_cnt;
/* clear current cnt */
hw_suptmrx->CNT = 0;
if (cb) {
dev->_counter_irq_hdl = cb;
dev->irq_data = cb_data;
hw_suptmrx->CON |= LL_SUPTMRx_CON_UD_IE;
}
hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
break;
default:
return RET_ERR;
break;
}
return RET_OK;
}
static int32 hgtimer_v6_counter_func_stop(struct timer_device *timer)
{
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
int32 index = 0;
if (!dev->counter_en) {
return RET_ERR;
}
/* confirm which suptmr */
index = hgtimer_v6_switch_suptmr_index(dev);
if ((-1) == index) {
return RET_ERR;
}
hw_comm->SUPTMR_CON1 &= ~(1) << (0 + index);
return RET_OK;
}
static int32 hgtimer_v6_counter_func_ioctl(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2)
{
int32 ret_val = RET_OK;
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
switch (cmd) {
case (HGPWM_V0_FUNC_CMD_MASK):
ret_val = hgtimer_v6_pwm_config(dev, param1, 0);
break;
case (TIMER_SET_CLK_PSC):
ret_val = hgtimer_v6_counter_set_psc(dev, param1);
break;
default:
ret_val = RET_ERR;
break;
}
return ret_val;
}
/**********************************************************************************/
/* COUNTER FUNCTION END */
/**********************************************************************************/
static void hgtimer_v6_irq_handler(void *data)
{
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)data;
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
if ((hw_suptmrx->CON & LL_SUPTMRx_CON_UD_IF) &&
(hw_suptmrx->CON & LL_SUPTMRx_CON_UD_IE)) {
/* clear the pending */
hw_suptmrx->CON |= LL_SUPTMRx_CON_UD_IF_CLR;
/* pwm mode irq */
if (dev->opened && dev->pwm_en && dev->_pwm_irq_hdl) {
dev->_pwm_irq_hdl(PWM_IRQ_FLAG_PERIOD, dev->irq_data);
}
/* counter mode irq */
if (dev->opened && dev->counter_en) {
if (dev->counter_once_en) {
dev->counter_once_en = 0;
/* close timer & interrupt */
hw_suptmrx->CON &= ~ LL_SUPTMRx_CON_UD_IE;
}
if (dev->_counter_irq_hdl) {
dev->_counter_irq_hdl(dev->irq_data, TIMER_INTR_PERIOD);
}
}
}
if ((hw_suptmrx->CON & LL_SUPTMRx_CON_CMPA_IF) &&
(hw_suptmrx->CON & LL_SUPTMRx_CON_CMPA_IE)) {
/* clear the pending */
hw_suptmrx->CON |= LL_SUPTMRx_CON_CMPA_IF_CLR;
/* pwm mode irq */
if (dev->opened && dev->pwm_en && dev->_pwm_irq_hdl) {
dev->_pwm_irq_hdl(PWM_IRQ_FLAG_PERIOD, dev->irq_data);
}
}
}
static const struct timer_hal_ops timer_v6_ops = {
.open = hgtimer_v6_counter_func_open,
.close = hgtimer_v6_counter_func_close,
.start = hgtimer_v6_counter_func_start,
.stop = hgtimer_v6_counter_func_stop,
.ioctl = hgtimer_v6_counter_func_ioctl,
};
int32 hgtimer_v6_attach(uint32 dev_id, struct hgtimer_v6 *timer)
{
timer->opened = 0;
timer->_counter_irq_hdl = NULL;
timer->_pwm_irq_hdl = NULL;
timer->irq_data = 0;
timer->dev.dev.ops = (const struct devobj_ops *)&timer_v6_ops;
request_irq(timer->irq_num, hgtimer_v6_irq_handler, timer);
dev_register(dev_id, (struct dev_obj *)timer);
return RET_OK;
}
sdk/driver/timer/hgtimer_v6_hw.h
+633
View File
@@ -0,0 +1,633 @@
#ifndef _HGTIMER_V6_HW_H
#define _HGTIMER_V6_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/* **** SUPTMR_CON0 **** */
/* Clear SUPTMR5 counter
*/
#define LL_SUPTMR_CON0_SUPTMR5_CNT_CLR ((uint32)(1UL << 29))
/* Clear SUPTMR4 counter
*/
#define LL_SUPTMR_CON0_SUPTMR4_CNT_CLR ((uint32)(1UL << 28))
/* Clear SUPTMR3 counter
*/
#define LL_SUPTMR_CON0_SUPTMR3_CNT_CLR ((uint32)(1UL << 27))
/* Clear SUPTMR2 counter
*/
#define LL_SUPTMR_CON0_SUPTMR2_CNT_CLR ((uint32)(1UL << 26))
/* Clear SUPTMR1 counter
*/
#define LL_SUPTMR_CON0_SUPTMR1_CNT_CLR ((uint32)(1UL << 25))
/* Clear SUPTMR0 counter
*/
#define LL_SUPTMR_CON0_SUPTMR0_CNT_CLR ((uint32)(1UL << 24))
/* SUPTMR5 count type select
*/
#define LL_SUPTMR_CON0_SUPTMR5_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 21))
/* SUPTMR4 count type select
*/
#define LL_SUPTMR_CON0_SUPTMR4_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 20))
/* SUPTMR3 count type select
*/
#define LL_SUPTMR_CON0_SUPTMR3_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 19))
/* SUPTMR2 count type select
*/
#define LL_SUPTMR_CON0_SUPTMR2_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 18))
/* SUPTMR1 count type select
*/
#define LL_SUPTMR_CON0_SUPTMR1_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 17))
/* SUPTMR0 count type select
*/
#define LL_SUPTMR_CON0_SUPTMR0_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
/* Auto load point select
*/
#define LL_SUPTMR_CON0_LOAD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
/* CMPC flag point select
*/
#define LL_SUPTMR_CON0_CPMC_SEL(n) ((uint32)(((uint32)(n)&0x1) << 14))
/* SUPTMR5 count mode select
*/
#define LL_SUPTMR_CON0_SUPTMR5_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
/* SUPTMR4 count mode select
*/
#define LL_SUPTMR_CON0_SUPTMR4_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
/* SUPTMR3 count mode select
*/
#define LL_SUPTMR_CON0_SUPTMR3_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 11))
/* SUPTMR2 count mode select
*/
#define LL_SUPTMR_CON0_SUPTMR2_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
/* SUPTMR1 count mode select
*/
#define LL_SUPTMR_CON0_SUPTMR1_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 9))
/* SUPTMR0 count mode select
*/
#define LL_SUPTMR_CON0_SUPTMR0_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 8))
/* Enable SUPTMR1 SUPTMR3 and SUPTMR5 group function
*/
#define LL_SUPTMR_CON0_SUPTMR_GP1_EN ((uint32)(1UL << 7))
/* Enable SUPTMR0 SUPTMR2 and SUPTMR4 group function
*/
#define LL_SUPTMR_CON0_SUPTMR_GP0_EN ((uint32)(1UL << 6))
/* SUPTMR4 SUPTMR5 sync mode select
*/
#define LL_STRM_CON0_SUPTMR45_SYNC_MD_SEL(n) ((uint32)(((uint32)(n)&0x3) << 4))
/* SUPTMR2 SUPTMR3 sync mode select
*/
#define LL_STRM_CON0_SUPTMR23_SYNC_MD_SEL(n) ((uint32)(((uint32)(n)&0x3) << 2))
/* SUPTMR0 SUPTMR1 sync mode select
*/
#define LL_STRM_CON0_SUPTMR01_SYNC_MD_SEL(n) ((uint32)(((uint32)(n)&0x3) << 0))
/* **** SUPTMR_CON1 **** */
/* Set SUPTMR CMPC value
*/
#define LL_SUPTMR_CON1_SUPTMR_CMPC(n) ((uint32)(((uint32)(n)&0xFFFF) << 16))
/* Enable SUPTMR5 auto load
*/
#define LL_SUPTMR_CON1_SUPTMR5_LOAD_EN(x) ((uint32)((x&0x1) << 13))
/* Enable SUPTMR4 auto load
*/
#define LL_SUPTMR_CON1_SUPTMR4_LOAD_EN(x) ((uint32)((x&0x1) << 12))
/* Enable SUPTMR3 auto load
*/
#define LL_SUPTMR_CON1_SUPTMR3_LOAD_EN(x) ((uint32)((x&0x1) << 11))
/* Enable SUPTMR2 auto load
*/
#define LL_SUPTMR_CON1_SUPTMR2_LOAD_EN(x) ((uint32)((x&0x1) << 10))
/* Enable SUPTMR1 auto load
*/
#define LL_SUPTMR_CON1_SUPTMR1_LOAD_EN(x) ((uint32)((x&0x1) << 9))
/* Enable SUPTMR0 auto load
*/
#define LL_SUPTMR_CON1_SUPTMR0_LOAD_EN(x) ((uint32)((x&0x1) << 8))
/* Enable all SUPTMR auto load
*/
#define LL_STRM_CON1_ALL_SUPTMR_LOAD_EN ((uint32)(0x3F << 8))
/* Enable SUPTMR5 counter
*/
#define LL_SUPTMR_CON1_SUPTMR5_CNT_EN(x) ((uint32)((x&0x1) << 5))
/* Enable SUPTMR4 counter
*/
#define LL_SUPTMR_CON1_SUPTMR4_CNT_EN(x) ((uint32)((x&0x1) << 4))
/* Enable SUPTMR3 counter
*/
#define LL_SUPTMR_CON1_SUPTMR3_CNT_EN(x) ((uint32)((x&0x1) << 3))
/* Enable SUPTMR2 counter
*/
#define LL_SUPTMR_CON1_SUPTMR2_CNT_EN(x) ((uint32)((x&0x1) << 2))
/* Enable SUPTMR1 counter
*/
#define LL_SUPTMR_CON1_SUPTMR1_CNT_EN(x) ((uint32)((x&0x1) << 1))
/* Enable SUPTMR0 counter
*/
#define LL_SUPTMR_CON1_SUPTMR0_CNT_EN(x) ((uint32)((x&0x1) << 0))
/* **** SUPTMRx_CON **** */
/* SUPTMRx BRAKE flag clear
*/
#define LL_SUPTMRx_CON_BRK_IF_CLR ((uint32)(1UL << 31))
/* SUPTMRx counter equal to CMPB flag clear
*/
#define LL_SUPTMRx_CON_CMPB_IF_CLR ((uint32)(1UL << 30))
/* SUPTMRx counter equal to CMPA flag clear
*/
#define LL_SUPTMRx_CON_CMPA_IF_CLR ((uint32)(1UL << 29))
/* SUPTMRx counter equal to zero flag clear
*/
#define LL_SUPTMRx_CON_UD_IF_CLR ((uint32)(1UL << 28))
/* SUPTMRx counter equal to period flag clear
*/
#define LL_SUPTMRx_CON_OV_IF_CLR ((uint32)(1UL << 27))
/* SUPTMRx BRAKE flag
*/
#define LL_SUPTMRx_CON_BRK_IF ((uint32)(1UL << 26))
/* SUPTMRx counter equal to CMPB flag
*/
#define LL_SUPTMRx_CON_CMPB_IF ((uint32)(1UL << 25))
/* SUPTMRx counter equal to CMPA flag
*/
#define LL_SUPTMRx_CON_CMPA_IF ((uint32)(1UL << 24))
/* SUPTMRx counter equal to zero flag
*/
#define LL_SUPTMRx_CON_UD_IF ((uint32)(1UL << 23))
/* SUPTMRx counter equal to period flag
*/
#define LL_SUPTMRx_CON_OV_IF ((uint32)(1UL << 22))
/* Enable SUPTMRx BRAKE interrupt
*/
#define LL_SUPTMRx_CON_BRAKE_IE ((uint32)(1UL << 21))
/* Enable SUPTMRx counter equal to CMPB interrupt
*/
#define LL_SUPTMRx_CON_CMPB_IE ((uint32)(1UL << 20))
/* Enable SUPTMRx counter equal to CMPA interrupt
*/
#define LL_SUPTMRx_CON_CMPA_IE ((uint32)(1UL << 19))
/* Enable SUPTMRx counter equal to zero interrupt
*/
#define LL_SUPTMRx_CON_UD_IE ((uint32)(1UL << 18))
/* Enable SUPTMRx counter equal to period interrupt
*/
#define LL_SUPTMRx_CON_OV_IE ((uint32)(1UL << 17))
/* Set SUPTMRx clock prescale
*/
#define LL_SUPTMRx_CON_PSC(n) ((uint32)(((uint32)(n)&0x3FF) << 7))
/* **** SUPTMR_DT **** */
/* Set SUPTMR4 SUPTMR5 dead time
*/
#define LL_SUPTMR_DT_SUPTMR45_DT(n) ((uint32)(((uint32)(n)&0x3FF) << 20))
/* Set SUPTMR2 SUPTMR3 dead time
*/
#define LL_SUPTMR_DT_SUPTMR23_DT(n) ((uint32)(((uint32)(n)&0x3FF) << 10))
/* Set SUPTMR4 SUPTMR5 dead time
*/
#define LL_SUPTMR_DT_SUPTMR01_DT(n) ((uint32)(((uint32)(n)&0x3FF) << 0))
/* **** SUPTMR_DTCON **** */
/* Set SUPTMR5 output in dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR5_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 23))
/* Set SUPTMR4 output in dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR4_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 22))
/* Set SUPTMR3 output in dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR3_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 21))
/* Set SUPTMR2 output in dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR2_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 20))
/* Set SUPTMR1 output in dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR1_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 19))
/* Set SUPTMR0 output in dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR0_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 18))
/* SUPTMR5 dead time edge select
*/
#define LL_SUPTMR_DTCON_SUPTMR5_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 17))
/* SUPTMR4 dead time edge select
*/
#define LL_SUPTMR_DTCON_SUPTMR4_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
/* SUPTMR3 dead time edge select
*/
#define LL_SUPTMR_DTCON_SUPTMR3_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
/* SUPTMR2 dead time edge select
*/
#define LL_SUPTMR_DTCON_SUPTMR2_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 14))
/* SUPTMR1 dead time edge select
*/
#define LL_SUPTMR_DTCON_SUPTMR1_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
/* SUPTMR0 dead time edge select
*/
#define LL_SUPTMR_DTCON_SUPTMR0_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
/* SUPTMR4 SUPTMR5 dead time type select
*/
#define LL_SUPTMR_DTCON_SUPTMR23_DT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x7) << 9))
/* SUPTMR2 SUPTMR3 dead time type select
*/
#define LL_SUPTMR_DTCON_SUPTMR01_DT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x7) << 6))
/* SUPTMR0 SUPTMR1 dead time type select
*/
#define LL_SUPTMR_DTCON_SUPTMR45_DT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x7) << 3))
/* Enable SUPTMR4 SUPTMR5 dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR45_DT_EN ((uint32)(1UL << 2))
/* Enable SUPTMR2 SUPTMR3 dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR23_DT_EN ((uint32)(1UL << 1))
/* Enable SUPTMR0 SUPTMR1 dead time
*/
#define LL_SUPTMR_DTCON_SUPTMR01_DT_EN ((uint32)(1UL << 0))
/* **** SUPTMR_PWMCON **** */
/* Enable SUPTMR5 CMPB pwm output
*/
#define LL_SUPTMR_PWMCON_SUPTMR5_PWMB_EN ((uint32)(1UL << 23))
/* Enable SUPTMR4 CMPB pwm output
*/
#define LL_SUPTMR_PWMCON_SUPTMR4_PWMB_EN ((uint32)(1UL << 22))
/* Enable SUPTMR3 CMPB pwm output
*/
#define LL_SUPTMR_PWMCON_SUPTMR3_PWMB_EN ((uint32)(1UL << 21))
/* Enable SUPTMR2 CMPB pwm output
*/
#define LL_SUPTMR_PWMCON_SUPTMR2_PWMB_EN ((uint32)(1UL << 20))
/* Enable SUPTMR1 CMPB pwm output
*/
#define LL_SUPTMR_PWMCON_SUPTMR1_PWMB_EN ((uint32)(1UL << 19))
/* Enable SUPTMR0 CMPB pwm output
*/
#define LL_SUPTMR_PWMCON_SUPTMR0_PWMB_EN ((uint32)(1UL << 18))
/* SUPTMR5 PWMB output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR5_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 17))
/* SUPTMR4 PWMB output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR4_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
/* SUPTMR3 PWMB output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR3_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
/* SUPTMR2 PWMB output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR2_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 14))
/* SUPTMR1 PWMB output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR1_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
/* SUPTMR0 PWMB output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR0_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
/* SUPTMR5 PWMA output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR5_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 11))
/* SUPTMR4 PWMA output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR4_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
/* SUPTMR3 PWMA output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR3_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 9))
/* SUPTMR2 PWMA output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR2_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 8))
/* SUPTMR1 PWMA output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR1_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 7))
/* SUPTMR0 PWMA output action select
*/
#define LL_SUPTMR_PWMCON_SUPTMR0_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 6))
/* Enable SUPTMR5 PWM output
*/
#define LL_SUPTMR_PWMCON_SUPTMR5_PWM_EN ((uint32)(1UL << 5))
/* Enable SUPTMR4 PWM output
*/
#define LL_SUPTMR_PWMCON_SUPTMR4_PWM_EN ((uint32)(1UL << 4))
/* Enable SUPTMR3 PWM output
*/
#define LL_SUPTMR_PWMCON_SUPTMR3_PWM_EN ((uint32)(1UL << 3))
/* Enable SUPTMR2 PWM output
*/
#define LL_SUPTMR_PWMCON_SUPTMR2_PWM_EN ((uint32)(1UL << 2))
/* Enable SUPTMR1 PWM output
*/
#define LL_SUPTMR_PWMCON_SUPTMR1_PWM_EN ((uint32)(1UL << 1))
/* Enable SUPTMR0 PWM output
*/
#define LL_SUPTMR_PWMCON_SUPTMR0_PWM_EN ((uint32)(1UL << 0))
/* **** SUPTMR_PWMMSK **** */
/* SUPTMR5 PWM mask output data select
*/
#define LL_SUPTMR_PWMMSK_SUPTMR5_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
/* SUPTMR4 PWM mask output data select
*/
#define LL_SUPTMR_PWMMSK_SUPTMR4_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
/* SUPTMR3 PWM mask output data select
*/
#define LL_SUPTMR_PWMMSK_SUPTMR3_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 11))
/* SUPTMR2 PWM mask output data select
*/
#define LL_SUPTMR_PWMMSK_SUPTMR2_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
/* SUPTMR1 PWM mask output data select
*/
#define LL_SUPTMR_PWMMSK_SUPTMR1_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 9))
/* SUPTMR0 PWM mask output data select
*/
#define LL_SUPTMR_PWMMSK_SUPTMR0_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 8))
/* Enable SUPTMR5 mask output
*/
#define LL_SUPTMR_PWMMSK_SUPTMR5_PWM_MSK_EN ((uint32)(1UL << 5))
/* Enable SUPTMR4 mask output
*/
#define LL_SUPTMR_PWMMSK_SUPTMR4_PWM_MSK_EN ((uint32)(1UL << 4))
/* Enable SUPTMR3 mask output
*/
#define LL_SUPTMR_PWMMSK_SUPTMR3_PWM_MSK_EN ((uint32)(1UL << 3))
/* Enable SUPTMR2 mask output
*/
#define LL_SUPTMR_PWMMSK_SUPTMR2_PWM_MSK_EN ((uint32)(1UL << 2))
/* Enable SUPTMR1 mask output
*/
#define LL_SUPTMR_PWMMSK_SUPTMR1_PWM_MSK_EN ((uint32)(1UL << 1))
/* Enable SUPTMR0 mask output
*/
#define LL_SUPTMR_PWMMSK_SUPTMR0_PWM_MSK_EN ((uint32)(1UL << 0))
/* **** SUPTMR_BRKCON **** */
/* Set SUPTMR input filter length
*/
#define LL_SUPTMR_BRKCON_FILNUM(n) ((uint32)(((uint32)(n)&0x1f) << 23))
/* Set SUPTMR5 output in brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR5_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 22))
/* Set SUPTMR4 output in brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR4_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 21))
/* Set SUPTMR3 output in brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR3_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 20))
/* Set SUPTMR2 output in brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR2_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 19))
/* Set SUPTMR1 output in brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR1_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 18))
/* Set SUPTMR0 output in brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR0_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 17))
/* SUPTMR brake fb pin polarity select
*/
#define LL_SUPTMR_BRKCON_BRK_FB_POL_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
/* SUPTMR brake comp polarity select
*/
#define LL_SUPTMR_BRKCON_BRK_COMP_POL_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
/* Enable clear counter function when brake
*/
#define LL_SUPTMR_BRKCON_BRK_CLR_CNT_EN ((uint32)(1UL << 13))
/* SUPTMR soft brake
*/
#define LL_SUPTMR_BRKCON_BRK_SOFT ((uint32)(1UL << 12))
/* Enable SUPTMR brake source filter function
*/
#define LL_SUPTMR_BRKCON_BRK_FILT_EN ((uint32)(1UL << 11))
/* SUPTMR COMP brake select
*/
#define LL_SUPTMR_BRKCON_COMP_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
/* Disable SUPTMR counter when brake
*/
#define LL_SUPTMR_BRKCON_CNT_DIS ((uint32)(1UL << 9))
/* Enable SUPTMR FB pin brake
*/
#define LL_SUPTMR_BRKCON_FB_EN ((uint32)(1UL << 7))
/* Enable SUPTMR COMP brake
*/
#define LL_SUPTMR_BRKCON_COMP_EN ((uint32)(1UL << 6))
/* Enable SUPTMR5 brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR5_BRK_EN ((uint32)(1UL << 5))
/* Enable SUPTMR4 brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR4_BRK_EN ((uint32)(1UL << 4))
/* Enable SUPTMR3 brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR3_BRK_EN ((uint32)(1UL << 3))
/* Enable SUPTMR2 brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR2_BRK_EN ((uint32)(1UL << 2))
/* Enable SUPTMR1 brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR1_BRK_EN ((uint32)(1UL << 1))
/* Enable SUPTMR0 brake
*/
#define LL_SUPTMR_BRKCON_SUPTMR0_BRK_EN ((uint32)(1UL << 0))
/* **** SUPTMRx_PR **** */
/* Set SUPTMRx period value
*/
#define LL_SUPTMRx_PR(n) ((uint32)(((uint32)(n)&0xFFFF) << 0))
/* **** SUPTMRx_CMP **** */
/* Set SUPTMRx CMPB value
*/
#define LL_SUPTMRx_CMP_CMPB(n) ((uint32)(((uint32)(n)&0xFFFF) << 16))
/* Set SUPTMRx CMPA value
*/
#define LL_SUPTMRx_CMP_CMPA(n) ((uint32)(((uint32)(n)&0xFFFF) << 0))
/* **** SUPTMRx_CNT **** */
/* Set SUPTMRx counter value
*/
#define LL_SUPTMRx_CNT(n) ((uint32)(((uint32)(n)&0xFFFF) << 0))
struct hgtimer_v6_hw_comm {
__IO uint32_t SUPTMR_CON0;
__IO uint32_t SUPTMR_CON1;
__IO uint32_t SUPTMR_DT;
__IO uint32_t SUPTMR_DTCON;
__IO uint32_t SUPTMR_PWMCON;
__IO uint32_t SUPTMR_PWMMSK;
__IO uint32_t SUPTMR_BRKCON;
};
struct hgtimer_v6_hw_suptmrx {
__IO uint32_t CON;
__IO uint32_t PR;
__IO uint32_t CMP;
__IO uint32_t CNT;
};
#ifdef __cplusplus
}
#endif
#endif
sdk/driver/timer/hgtimer_v7.c
+1203
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sdk/driver/timer/hgtimer_v7_hw.h
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#ifndef _HGTIMER_V7_HW_H
#define _HGTIMER_V7_HW_H
#ifdef __cplusplus
extern "C" {
#endif
/***** SINPLE TIMERx CTL Register *****/
/*! Capture selection:
* 00 : GPIO
* 01 : GPIO OR
* 10 : compare0 output
* 11 : compare1 output
*/
#define LL_SIMPLE_TIMER_CAP_SEL(n) (((n)&0x3) << 16)
/*!Period break flag
*/
#define LL_SIMPLE_TIMER_PERIOD_ING (1UL << 15)
/*!Mark of capture
*/
#define LL_SIMPLE_TIMER_CAP_ING (1UL << 14)
/*!Periodic interrupt was enabled
*/
#define LL_SIMPLE_TIMER_PERIOD_IE (1UL << 13)
/*!Capture interrupt enable
*/
#define LL_SIMPLE_TIMER_CAP_IE (1UL << 12)
/*! Timer prescaler settings:
* 000 : 0 frequency division
* 001 : 2 frequency division
* 010 : 4 frequency division
* 011 : 8 frequency division
* 100 : 16 frequency division
* 101 : 32 frequency division
* 110 : 64 frequency division
* 111 : 128 frequency division
*/
#define LL_SIMPLE_TIMER_PSC(n) (((n)&0x7) << 8)
/*! Capture source edge selection
* 0x0: Capture occurs during rising edge
* 0x1: Capture occurs at falling edge
* 0x2: Capture occurs along both the rising and falling edges
* 0x3: Capture occurs along both the rising and falling edges
*/
#define LL_SIMPLE_TIMER_EDG_SCL(n) (((n)&0x3) << 6)
/*! simple timer mode select bits:
* 01 : timer counter mode
* 10 : timer pwm mode
* 11 : timer capture mode
* This bit of non-zero time counting is enabled
*/
#define LL_SIMPLE_TIMER_MODE_SEL(n) (((n)&0x3) << 4)
/*! Timer counter source select bits:
8 000 : Select GPIO (CAP PIN) as the clock source Select the rising edge as the count source;
* 001 : Select the GPIO (CAP PIN) as the clock source and the falling edge as the count source
* 010 : Select EXT_CLK_SRC1 as the clock source and the rising and falling edges as the count sources
* 011 : Select EXT_CLK_SRC0 as the clock source and the rising and falling edges as the count sources
* 100 : Select EXT_CLK_SRC2 as the clock source and the rising and falling edges as the count sources
* 111 : Select the overflow of the previous timer is selected as the count source. (withString multiple timers into one 64bit counter
* Others : system clock
*/
#define LL_SIMPLE_TIMER_INC_SRC_SEL(n) (((n)&0x7) << 0)
/***** SINPLE TIMERx CNT Register *****/
/*!Counter register
*/
#define LL_SIMPLE_TIMER_CNT(n) (((n)&0xFFFFFFFF) << 0)
/***** SINPLE TIMERx PERIOD Register *****/
/*!Period register
*/
#define LL_SIMPLE_TIMER_PERIOD(n) (((n)&0xFFFFFFFF) << 0)
/***** SINPLE TIMERx PERIOD Register *****/
/*!Comparison value register
*/
#define LL_SIMPLE_TIMER_PWM(n) (((n)&0xFFFFFFFF) << 0)
struct hgtimer_v7_hw {
__IO uint32_t TMR_CTL;
__IO uint32_t TMR_CNT;
__IO uint32_t TMR_PR;
__IO uint32_t TMR_PWM;
};
#ifdef __cplusplus
}
#endif
#endif /* _HGTIMER_V7_HW_H */