634 lines
18 KiB
C
634 lines
18 KiB
C
#ifndef _HGTIMER_V6_HW_H
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#define _HGTIMER_V6_HW_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* **** SUPTMR_CON0 **** */
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/* Clear SUPTMR5 counter
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*/
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#define LL_SUPTMR_CON0_SUPTMR5_CNT_CLR ((uint32)(1UL << 29))
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/* Clear SUPTMR4 counter
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*/
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#define LL_SUPTMR_CON0_SUPTMR4_CNT_CLR ((uint32)(1UL << 28))
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/* Clear SUPTMR3 counter
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*/
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#define LL_SUPTMR_CON0_SUPTMR3_CNT_CLR ((uint32)(1UL << 27))
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/* Clear SUPTMR2 counter
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*/
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#define LL_SUPTMR_CON0_SUPTMR2_CNT_CLR ((uint32)(1UL << 26))
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/* Clear SUPTMR1 counter
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*/
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#define LL_SUPTMR_CON0_SUPTMR1_CNT_CLR ((uint32)(1UL << 25))
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/* Clear SUPTMR0 counter
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*/
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#define LL_SUPTMR_CON0_SUPTMR0_CNT_CLR ((uint32)(1UL << 24))
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/* SUPTMR5 count type select
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*/
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#define LL_SUPTMR_CON0_SUPTMR5_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 21))
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/* SUPTMR4 count type select
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*/
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#define LL_SUPTMR_CON0_SUPTMR4_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 20))
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/* SUPTMR3 count type select
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*/
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#define LL_SUPTMR_CON0_SUPTMR3_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 19))
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/* SUPTMR2 count type select
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*/
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#define LL_SUPTMR_CON0_SUPTMR2_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 18))
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/* SUPTMR1 count type select
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*/
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#define LL_SUPTMR_CON0_SUPTMR1_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 17))
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/* SUPTMR0 count type select
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*/
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#define LL_SUPTMR_CON0_SUPTMR0_CNT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
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/* Auto load point select
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*/
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#define LL_SUPTMR_CON0_LOAD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
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/* CMPC flag point select
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*/
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#define LL_SUPTMR_CON0_CPMC_SEL(n) ((uint32)(((uint32)(n)&0x1) << 14))
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/* SUPTMR5 count mode select
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*/
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#define LL_SUPTMR_CON0_SUPTMR5_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
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/* SUPTMR4 count mode select
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*/
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#define LL_SUPTMR_CON0_SUPTMR4_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
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/* SUPTMR3 count mode select
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*/
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#define LL_SUPTMR_CON0_SUPTMR3_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 11))
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/* SUPTMR2 count mode select
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*/
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#define LL_SUPTMR_CON0_SUPTMR2_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
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/* SUPTMR1 count mode select
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*/
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#define LL_SUPTMR_CON0_SUPTMR1_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 9))
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/* SUPTMR0 count mode select
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*/
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#define LL_SUPTMR_CON0_SUPTMR0_CNT_MOD_SEL(n) ((uint32)(((uint32)(n)&0x1) << 8))
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/* Enable SUPTMR1 SUPTMR3 and SUPTMR5 group function
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*/
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#define LL_SUPTMR_CON0_SUPTMR_GP1_EN ((uint32)(1UL << 7))
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/* Enable SUPTMR0 SUPTMR2 and SUPTMR4 group function
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*/
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#define LL_SUPTMR_CON0_SUPTMR_GP0_EN ((uint32)(1UL << 6))
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/* SUPTMR4 SUPTMR5 sync mode select
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*/
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#define LL_STRM_CON0_SUPTMR45_SYNC_MD_SEL(n) ((uint32)(((uint32)(n)&0x3) << 4))
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/* SUPTMR2 SUPTMR3 sync mode select
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*/
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#define LL_STRM_CON0_SUPTMR23_SYNC_MD_SEL(n) ((uint32)(((uint32)(n)&0x3) << 2))
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/* SUPTMR0 SUPTMR1 sync mode select
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*/
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#define LL_STRM_CON0_SUPTMR01_SYNC_MD_SEL(n) ((uint32)(((uint32)(n)&0x3) << 0))
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/* **** SUPTMR_CON1 **** */
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/* Set SUPTMR CMPC value
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*/
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#define LL_SUPTMR_CON1_SUPTMR_CMPC(n) ((uint32)(((uint32)(n)&0xFFFF) << 16))
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/* Enable SUPTMR5 auto load
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*/
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#define LL_SUPTMR_CON1_SUPTMR5_LOAD_EN(x) ((uint32)((x&0x1) << 13))
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/* Enable SUPTMR4 auto load
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*/
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#define LL_SUPTMR_CON1_SUPTMR4_LOAD_EN(x) ((uint32)((x&0x1) << 12))
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/* Enable SUPTMR3 auto load
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*/
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#define LL_SUPTMR_CON1_SUPTMR3_LOAD_EN(x) ((uint32)((x&0x1) << 11))
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/* Enable SUPTMR2 auto load
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*/
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#define LL_SUPTMR_CON1_SUPTMR2_LOAD_EN(x) ((uint32)((x&0x1) << 10))
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/* Enable SUPTMR1 auto load
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*/
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#define LL_SUPTMR_CON1_SUPTMR1_LOAD_EN(x) ((uint32)((x&0x1) << 9))
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/* Enable SUPTMR0 auto load
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*/
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#define LL_SUPTMR_CON1_SUPTMR0_LOAD_EN(x) ((uint32)((x&0x1) << 8))
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/* Enable all SUPTMR auto load
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*/
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#define LL_STRM_CON1_ALL_SUPTMR_LOAD_EN ((uint32)(0x3F << 8))
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/* Enable SUPTMR5 counter
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*/
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#define LL_SUPTMR_CON1_SUPTMR5_CNT_EN(x) ((uint32)((x&0x1) << 5))
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/* Enable SUPTMR4 counter
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*/
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#define LL_SUPTMR_CON1_SUPTMR4_CNT_EN(x) ((uint32)((x&0x1) << 4))
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/* Enable SUPTMR3 counter
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*/
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#define LL_SUPTMR_CON1_SUPTMR3_CNT_EN(x) ((uint32)((x&0x1) << 3))
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/* Enable SUPTMR2 counter
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*/
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#define LL_SUPTMR_CON1_SUPTMR2_CNT_EN(x) ((uint32)((x&0x1) << 2))
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/* Enable SUPTMR1 counter
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*/
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#define LL_SUPTMR_CON1_SUPTMR1_CNT_EN(x) ((uint32)((x&0x1) << 1))
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/* Enable SUPTMR0 counter
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*/
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#define LL_SUPTMR_CON1_SUPTMR0_CNT_EN(x) ((uint32)((x&0x1) << 0))
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/* **** SUPTMRx_CON **** */
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/* SUPTMRx BRAKE flag clear
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*/
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#define LL_SUPTMRx_CON_BRK_IF_CLR ((uint32)(1UL << 31))
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/* SUPTMRx counter equal to CMPB flag clear
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*/
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#define LL_SUPTMRx_CON_CMPB_IF_CLR ((uint32)(1UL << 30))
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/* SUPTMRx counter equal to CMPA flag clear
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*/
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#define LL_SUPTMRx_CON_CMPA_IF_CLR ((uint32)(1UL << 29))
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/* SUPTMRx counter equal to zero flag clear
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*/
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#define LL_SUPTMRx_CON_UD_IF_CLR ((uint32)(1UL << 28))
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/* SUPTMRx counter equal to period flag clear
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*/
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#define LL_SUPTMRx_CON_OV_IF_CLR ((uint32)(1UL << 27))
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/* SUPTMRx BRAKE flag
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*/
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#define LL_SUPTMRx_CON_BRK_IF ((uint32)(1UL << 26))
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/* SUPTMRx counter equal to CMPB flag
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*/
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#define LL_SUPTMRx_CON_CMPB_IF ((uint32)(1UL << 25))
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/* SUPTMRx counter equal to CMPA flag
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*/
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#define LL_SUPTMRx_CON_CMPA_IF ((uint32)(1UL << 24))
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/* SUPTMRx counter equal to zero flag
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*/
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#define LL_SUPTMRx_CON_UD_IF ((uint32)(1UL << 23))
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/* SUPTMRx counter equal to period flag
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*/
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#define LL_SUPTMRx_CON_OV_IF ((uint32)(1UL << 22))
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/* Enable SUPTMRx BRAKE interrupt
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*/
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#define LL_SUPTMRx_CON_BRAKE_IE ((uint32)(1UL << 21))
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/* Enable SUPTMRx counter equal to CMPB interrupt
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*/
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#define LL_SUPTMRx_CON_CMPB_IE ((uint32)(1UL << 20))
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/* Enable SUPTMRx counter equal to CMPA interrupt
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*/
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#define LL_SUPTMRx_CON_CMPA_IE ((uint32)(1UL << 19))
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/* Enable SUPTMRx counter equal to zero interrupt
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*/
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#define LL_SUPTMRx_CON_UD_IE ((uint32)(1UL << 18))
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/* Enable SUPTMRx counter equal to period interrupt
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*/
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#define LL_SUPTMRx_CON_OV_IE ((uint32)(1UL << 17))
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/* Set SUPTMRx clock prescale
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*/
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#define LL_SUPTMRx_CON_PSC(n) ((uint32)(((uint32)(n)&0x3FF) << 7))
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/* **** SUPTMR_DT **** */
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/* Set SUPTMR4 SUPTMR5 dead time
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*/
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#define LL_SUPTMR_DT_SUPTMR45_DT(n) ((uint32)(((uint32)(n)&0x3FF) << 20))
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/* Set SUPTMR2 SUPTMR3 dead time
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*/
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#define LL_SUPTMR_DT_SUPTMR23_DT(n) ((uint32)(((uint32)(n)&0x3FF) << 10))
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/* Set SUPTMR4 SUPTMR5 dead time
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*/
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#define LL_SUPTMR_DT_SUPTMR01_DT(n) ((uint32)(((uint32)(n)&0x3FF) << 0))
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/* **** SUPTMR_DTCON **** */
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/* Set SUPTMR5 output in dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR5_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 23))
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/* Set SUPTMR4 output in dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR4_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 22))
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/* Set SUPTMR3 output in dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR3_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 21))
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/* Set SUPTMR2 output in dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR2_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 20))
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/* Set SUPTMR1 output in dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR1_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 19))
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/* Set SUPTMR0 output in dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR0_DT_DAT(n) ((uint32)(((uint32)(n)&0x1) << 18))
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/* SUPTMR5 dead time edge select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR5_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 17))
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/* SUPTMR4 dead time edge select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR4_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
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/* SUPTMR3 dead time edge select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR3_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
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/* SUPTMR2 dead time edge select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR2_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 14))
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/* SUPTMR1 dead time edge select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR1_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
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/* SUPTMR0 dead time edge select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR0_EDGE_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
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/* SUPTMR4 SUPTMR5 dead time type select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR23_DT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x7) << 9))
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/* SUPTMR2 SUPTMR3 dead time type select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR01_DT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x7) << 6))
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/* SUPTMR0 SUPTMR1 dead time type select
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*/
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#define LL_SUPTMR_DTCON_SUPTMR45_DT_TYPE_SEL(n) ((uint32)(((uint32)(n)&0x7) << 3))
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/* Enable SUPTMR4 SUPTMR5 dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR45_DT_EN ((uint32)(1UL << 2))
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/* Enable SUPTMR2 SUPTMR3 dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR23_DT_EN ((uint32)(1UL << 1))
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/* Enable SUPTMR0 SUPTMR1 dead time
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*/
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#define LL_SUPTMR_DTCON_SUPTMR01_DT_EN ((uint32)(1UL << 0))
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/* **** SUPTMR_PWMCON **** */
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/* Enable SUPTMR5 CMPB pwm output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR5_PWMB_EN ((uint32)(1UL << 23))
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/* Enable SUPTMR4 CMPB pwm output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR4_PWMB_EN ((uint32)(1UL << 22))
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/* Enable SUPTMR3 CMPB pwm output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR3_PWMB_EN ((uint32)(1UL << 21))
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/* Enable SUPTMR2 CMPB pwm output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR2_PWMB_EN ((uint32)(1UL << 20))
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/* Enable SUPTMR1 CMPB pwm output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR1_PWMB_EN ((uint32)(1UL << 19))
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/* Enable SUPTMR0 CMPB pwm output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR0_PWMB_EN ((uint32)(1UL << 18))
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/* SUPTMR5 PWMB output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR5_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 17))
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/* SUPTMR4 PWMB output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR4_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
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/* SUPTMR3 PWMB output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR3_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
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/* SUPTMR2 PWMB output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR2_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 14))
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/* SUPTMR1 PWMB output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR1_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
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/* SUPTMR0 PWMB output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR0_PWMB_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
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/* SUPTMR5 PWMA output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR5_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 11))
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/* SUPTMR4 PWMA output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR4_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
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/* SUPTMR3 PWMA output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR3_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 9))
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/* SUPTMR2 PWMA output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR2_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 8))
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/* SUPTMR1 PWMA output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR1_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 7))
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/* SUPTMR0 PWMA output action select
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR0_PWMA_SEL(n) ((uint32)(((uint32)(n)&0x1) << 6))
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/* Enable SUPTMR5 PWM output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR5_PWM_EN ((uint32)(1UL << 5))
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/* Enable SUPTMR4 PWM output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR4_PWM_EN ((uint32)(1UL << 4))
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/* Enable SUPTMR3 PWM output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR3_PWM_EN ((uint32)(1UL << 3))
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/* Enable SUPTMR2 PWM output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR2_PWM_EN ((uint32)(1UL << 2))
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/* Enable SUPTMR1 PWM output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR1_PWM_EN ((uint32)(1UL << 1))
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/* Enable SUPTMR0 PWM output
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*/
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#define LL_SUPTMR_PWMCON_SUPTMR0_PWM_EN ((uint32)(1UL << 0))
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/* **** SUPTMR_PWMMSK **** */
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/* SUPTMR5 PWM mask output data select
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR5_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 13))
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/* SUPTMR4 PWM mask output data select
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR4_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 12))
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/* SUPTMR3 PWM mask output data select
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR3_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 11))
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/* SUPTMR2 PWM mask output data select
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR2_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
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/* SUPTMR1 PWM mask output data select
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR1_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 9))
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/* SUPTMR0 PWM mask output data select
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR0_PWM_MSK_DAT_SEL(n) ((uint32)(((uint32)(n)&0x1) << 8))
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/* Enable SUPTMR5 mask output
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR5_PWM_MSK_EN ((uint32)(1UL << 5))
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/* Enable SUPTMR4 mask output
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR4_PWM_MSK_EN ((uint32)(1UL << 4))
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/* Enable SUPTMR3 mask output
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR3_PWM_MSK_EN ((uint32)(1UL << 3))
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/* Enable SUPTMR2 mask output
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR2_PWM_MSK_EN ((uint32)(1UL << 2))
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/* Enable SUPTMR1 mask output
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR1_PWM_MSK_EN ((uint32)(1UL << 1))
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/* Enable SUPTMR0 mask output
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*/
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#define LL_SUPTMR_PWMMSK_SUPTMR0_PWM_MSK_EN ((uint32)(1UL << 0))
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/* **** SUPTMR_BRKCON **** */
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/* Set SUPTMR input filter length
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*/
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#define LL_SUPTMR_BRKCON_FILNUM(n) ((uint32)(((uint32)(n)&0x1f) << 23))
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/* Set SUPTMR5 output in brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR5_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 22))
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/* Set SUPTMR4 output in brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR4_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 21))
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/* Set SUPTMR3 output in brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR3_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 20))
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/* Set SUPTMR2 output in brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR2_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 19))
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/* Set SUPTMR1 output in brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR1_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 18))
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/* Set SUPTMR0 output in brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR0_BRK_DAT(n) ((uint32)(((uint32)(n)&0x1) << 17))
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/* SUPTMR brake fb pin polarity select
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*/
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#define LL_SUPTMR_BRKCON_BRK_FB_POL_SEL(n) ((uint32)(((uint32)(n)&0x1) << 16))
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/* SUPTMR brake comp polarity select
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*/
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#define LL_SUPTMR_BRKCON_BRK_COMP_POL_SEL(n) ((uint32)(((uint32)(n)&0x1) << 15))
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/* Enable clear counter function when brake
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*/
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#define LL_SUPTMR_BRKCON_BRK_CLR_CNT_EN ((uint32)(1UL << 13))
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/* SUPTMR soft brake
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*/
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#define LL_SUPTMR_BRKCON_BRK_SOFT ((uint32)(1UL << 12))
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/* Enable SUPTMR brake source filter function
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*/
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#define LL_SUPTMR_BRKCON_BRK_FILT_EN ((uint32)(1UL << 11))
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/* SUPTMR COMP brake select
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*/
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#define LL_SUPTMR_BRKCON_COMP_SEL(n) ((uint32)(((uint32)(n)&0x1) << 10))
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/* Disable SUPTMR counter when brake
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*/
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#define LL_SUPTMR_BRKCON_CNT_DIS ((uint32)(1UL << 9))
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/* Enable SUPTMR FB pin brake
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*/
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#define LL_SUPTMR_BRKCON_FB_EN ((uint32)(1UL << 7))
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/* Enable SUPTMR COMP brake
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*/
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#define LL_SUPTMR_BRKCON_COMP_EN ((uint32)(1UL << 6))
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/* Enable SUPTMR5 brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR5_BRK_EN ((uint32)(1UL << 5))
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/* Enable SUPTMR4 brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR4_BRK_EN ((uint32)(1UL << 4))
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/* Enable SUPTMR3 brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR3_BRK_EN ((uint32)(1UL << 3))
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/* Enable SUPTMR2 brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR2_BRK_EN ((uint32)(1UL << 2))
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/* Enable SUPTMR1 brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR1_BRK_EN ((uint32)(1UL << 1))
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/* Enable SUPTMR0 brake
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*/
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#define LL_SUPTMR_BRKCON_SUPTMR0_BRK_EN ((uint32)(1UL << 0))
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/* **** SUPTMRx_PR **** */
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/* Set SUPTMRx period value
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|
*/
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#define LL_SUPTMRx_PR(n) ((uint32)(((uint32)(n)&0xFFFF) << 0))
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/* **** SUPTMRx_CMP **** */
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/* Set SUPTMRx CMPB value
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*/
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#define LL_SUPTMRx_CMP_CMPB(n) ((uint32)(((uint32)(n)&0xFFFF) << 16))
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/* Set SUPTMRx CMPA value
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|
*/
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#define LL_SUPTMRx_CMP_CMPA(n) ((uint32)(((uint32)(n)&0xFFFF) << 0))
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/* **** SUPTMRx_CNT **** */
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/* Set SUPTMRx counter value
|
|
*/
|
|
#define LL_SUPTMRx_CNT(n) ((uint32)(((uint32)(n)&0xFFFF) << 0))
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struct hgtimer_v6_hw_comm {
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|
__IO uint32_t SUPTMR_CON0;
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__IO uint32_t SUPTMR_CON1;
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|
__IO uint32_t SUPTMR_DT;
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__IO uint32_t SUPTMR_DTCON;
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|
__IO uint32_t SUPTMR_PWMCON;
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|
__IO uint32_t SUPTMR_PWMMSK;
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|
__IO uint32_t SUPTMR_BRKCON;
|
|
};
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|
|
|
struct hgtimer_v6_hw_suptmrx {
|
|
__IO uint32_t CON;
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|
__IO uint32_t PR;
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|
__IO uint32_t CMP;
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|
__IO uint32_t CNT;
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|
};
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#ifdef __cplusplus
|
|
}
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#endif
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#endif
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