Ajout FishPeper

2026-04-21 12:19:15 +02:00
parent 6744da3f88
commit 0c361a2440
2160 changed files with 589301 additions and 1 deletions
--- a/tinyPEPPER/.gitignore
+++ b/tinyPEPPER/.gitignore
@@ -0,0 +1,23 @@
+# For PCBs designed using KiCad: http://www.kicad-pcb.org/
+
+# Temporary files
+*.000
+*.bak
+*.bck
+*.kicad_pcb-bak
+*~
+_autosave-*
+*.tmp
+
+# Netlist files (exported from Eeschema)
+*.net
+
+# Autorouter files (exported from Pcbnew)
+.dsn
+
+# Exported BOM files
+*.xml
+*.csv
+
+*.pyc
+doc/*.png
--- a/tinyPEPPER/.gitmodules
+++ b/tinyPEPPER/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "kicad_misc"]
+	path = kicad_misc
+	url = https://github.com/fishpepper/kicad_misc
--- a/tinyPEPPER/LICENSE
+++ b/tinyPEPPER/LICENSE
@@ -0,0 +1,189 @@
+CERN Open Hardware Licence v1.2 
+
+Preamble
+
+Through this CERN Open Hardware Licence ("CERN OHL") version 1.2, CERN
+wishes to provide a tool to foster collaboration and sharing among
+hardware designers.  The CERN OHL is copyright CERN. Anyone is welcome
+to use the CERN OHL, in unmodified form only, for the distribution of
+their own Open Hardware designs. Any other right is reserved. Release
+of hardware designs under the CERN OHL does not constitute an
+endorsement of the licensor or its designs nor does it imply any
+involvement by CERN in the development of such designs.
+
+1. Definitions
+
+In this Licence, the following terms have the following meanings:
+ 
+“Licence” means this CERN OHL.
+
+“Documentation” means schematic diagrams, designs, circuit or circuit
+board layouts, mechanical drawings, flow charts and descriptive text,
+and other explanatory material that is explicitly stated as being made
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+be in any medium, including but not limited to computer files and
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+
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+this Licence.
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+Documentation and subsequently communicates to the public and/ or
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+
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+
+Use of the masculine gender includes the feminine and neuter genders
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+
+2. Applicability
+
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+communication to the public and distribution of the Documentation, and
+the manufacture and distribution of Products. By exercising any right
+granted under this Licence, the Licensee irrevocably accepts these
+terms and conditions.
+
+2.2. This Licence is granted by the Licensor directly to the Licensee,
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+2.3. This Licence does not extend to software, firmware, or code
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+such software, firmware, or code is explicitly expressed to be subject
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+
+3. Copying, modification, communication to the public and distribution
+of the Documentation
+
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+notices, all notices referring to Documentation Location, and all
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+
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+e) license the modified Documentation under the terms and conditions
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+registered designs that are held by, under the control of, or
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+
+5. Warranty and liability
+
+5.1. DISCLAIMER – The Documentation and any modified Documentation are
+provided "as is" and any express or implied warranties, including, but
+not limited to, implied warranties of merchantability, of satisfactory
+quality, non-infringement of third party rights, and fitness for a
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+5.2. LIMITATION OF LIABILITY – The Licensor shall have no liability
+for direct, indirect, special, incidental, consequential, exemplary,
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+limitation, procurement of substitute goods or services, loss of use,
+data or profits, or business interruption, however caused and on any
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+liability or otherwise, arising in any way in relation to the
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+6. General
+
+6.1. Except for the rights explicitly granted hereunder, this Licence
+does not imply or represent any transfer or assignment of intellectual
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+(including acronyms and abbreviations), images, or logos under which
+the Licensor is known, save in so far as required to comply with
+section 3. Any such permitted use or reference shall be factual and
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+6.3. CERN may publish updated versions of this Licence which retain
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+Licence. Section 5 shall continue to apply.
--- a/tinyPEPPER/README.md
+++ b/tinyPEPPER/README.md
@@ -0,0 +1,32 @@
+# tinyPEPPER -- a tiny and lightweight 4in1 BLHeli_S ESC
+
+My approach to build a small and lightweight ESC.
+
+See [http://fishpepper.de/projects/tinyPEPPER](http://fishpepper.de/projects/tinyPEPPER) for more details.
+
+![tinyPEPPER image](http://fishpepper.de/wp-content/uploads/2017/02/tinyPEPPER_v03-300x279.jpg)
+
+This thing is TINY! The outer dimensions are 20x20mm with a 16mm hole-to-hole spacing.
+It runs BLHELI_S 
+
+Key features:
+- 16x16mm hole-to-hole spacing
+- 1.2g (!)
+- BLHeli_S with DSHOT300
+- 1S only (really!)
+
+This work is published under the CERN open hardware license v1.2. 
+Feel free to use the design - but make sure to give proper credit 
+and release all modifications under the same license! 
+See LICENSE.txt for details!
+
+THIS COMES WITH NO WARRANTY! BUILD, FLY, AND USE AT YOUR OWN RISK!
+
+
+# Build your own
+
+Make sure to init the git submodule for the libraries in the
+kicad_misc directory by calling git submodule init && git submodule update.
+You will have to use a recent kicad version, i used the commit #efdfaeb
+when i designed this circuit board. Older versions will probably not work.
+
--- a/tinyPEPPER/doc/generate_svg.py
+++ b/tinyPEPPER/doc/generate_svg.py
@@ -0,0 +1,130 @@
+#!/usr/bin/env python
+#   Copyright 2015 Scott Bezek
+#
+#   Licensed under the Apache License, Version 2.0 (the "License");
+#   you may not use this file except in compliance with the License.
+#   You may obtain a copy of the License at
+#
+#       http://www.apache.org/licenses/LICENSE-2.0
+#
+#   Unless required by applicable law or agreed to in writing, software
+#   distributed under the License is distributed on an "AS IS" BASIS,
+#   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#   See the License for the specific language governing permissions and
+#   limitations under the License.
+
+import logging
+import os
+import pcbnew
+import shutil
+import subprocess
+
+import pcb_util
+
+from svg_processor import SvgProcessor
+
+logging.basicConfig(level=logging.DEBUG)
+logger = logging.getLogger(__name__)
+
+PCB_FILENAME = '../tinyPEPPER.kicad_pcb'
+
+# Have to use absolute path for build_directory otherwise pcbnew will output relative to the temp file
+BUILD_DIRECTORY = os.path.abspath('./')
+
+def color_with_alpha(base_color, alpha):
+    return (base_color & ~(0xFF << 24)) | ((alpha & 0xFF) << 24)
+
+def render(job):
+    temp_dir = os.path.join(BUILD_DIRECTORY, 'temp_layers')
+    shutil.rmtree(temp_dir, ignore_errors=True)
+    try:
+        os.makedirs(temp_dir)
+        plot_job(job, BUILD_DIRECTORY, temp_dir)
+    finally:
+        shutil.rmtree(temp_dir, ignore_errors=True)
+
+def plot_job(job, output_directory, temp_dir):
+    logger.info("processing job " + job["filename"])
+    with pcb_util.get_plotter(PCB_FILENAME, temp_dir) as plotter:
+        plotter.plot_options.SetMirror(job["mirror"])
+        plotter.plot_options.SetExcludeEdgeLayer(False)
+        processed_svg_files = []
+        for i, layer in enumerate(job["layers"]):
+            output_filename = plotter.plot(layer['layer'], pcbnew.PLOT_FORMAT_SVG)
+            logger.info('Post-processing %s...', output_filename)
+            processor = SvgProcessor(output_filename)
+            def colorize(original):
+                if original.lower() == '#000000':
+                    return layer['color']
+                return original
+            processor.apply_color_transform(colorize)
+            processor.wrap_with_group({
+                'opacity': str(layer['alpha']),
+            })
+
+            output_filename2 = os.path.join(temp_dir, 'processed-' + os.path.basename(output_filename))
+            processor.write(output_filename2)
+            processed_svg_files.append((output_filename2, processor))
+
+        logger.info('merging layers...')
+        final_svg = os.path.join(output_directory, job["filename"] + '.svg')
+
+        shutil.copyfile(processed_svg_files[0][0], final_svg)
+        output_processor = SvgProcessor(final_svg)
+        for _, processor in processed_svg_files:
+            output_processor.import_groups(processor)
+        output_processor.write(final_svg)
+
+        logger.info('rasterizing...')
+        final_png = os.path.join(output_directory, job["filename"] + '.png')
+
+        subprocess.check_call([
+            'inkscape',
+            '--export-area-drawing',
+            '--export-width=1010',
+            '--export-png', final_png,
+            '--export-background', '#FFFFFF',
+            final_svg,
+        ])
+
+if __name__ == '__main__':
+    
+    jobs = [
+        #front placement
+        { 
+        "filename" : "placement_front",
+        "mirror"   : False,
+        "layers"   : [
+                { 'layer': pcbnew.F_Cu, 'color': '#CC0000', 'alpha': 1.0, },
+                { 'layer': pcbnew.F_SilkS, 'color': '#045a00', 'alpha': 1.0, },
+                { 'layer': pcbnew.Eco1_User, 'color': '#002BFF', 'alpha': 1.0, },
+                { 'layer': pcbnew.F_Fab, 'color': '#000000', 'alpha': 1.0, }
+            ]
+        },
+        #back placement
+        { 
+        "filename" : "placement_back",
+        "mirror"   : True,
+        "layers"   : [
+                { 'layer': pcbnew.B_Cu, 'color': '#00DD00', 'alpha': 1.0, },
+                { 'layer': pcbnew.B_SilkS, 'color': '#A000FF', 'alpha': 1.0, },
+                { 'layer': pcbnew.Eco2_User, 'color': '#002BFF', 'alpha': 1.0, },
+                { 'layer': pcbnew.B_Fab, 'color': '#000000', 'alpha': 1.0, }
+            ]
+        },
+        #front rendering
+        #{ 
+        #"filename" : "rendered_front",
+        #"mirror"   : False,
+        #"layers"   : [
+        #        #005518
+        #        { 'layer': pcbnew.F_Cu, 'color': '#401264', 'alpha': 1.0, },
+        #        { 'layer': pcbnew.F_SilkS, 'color': '#FFFFFF', 'alpha': 1.0, },
+        #        { 'layer': pcbnew.F_Mask, 'color': '#FFE13A', 'alpha': 1.0, },
+        #        { 'layer': pcbnew.Edge_Cuts, 'color': '#000000', 'alpha': 1.0, },
+        #    ]
+        #}
+    ]
+
+    for x in jobs:
+        render(x)
--- a/tinyPEPPER/doc/pcb_util.py
+++ b/tinyPEPPER/doc/pcb_util.py
@@ -0,0 +1,156 @@
+#!/usr/bin/env python
+#   Copyright 2015 Scott Bezek
+#
+#   Licensed under the Apache License, Version 2.0 (the "License");
+#   you may not use this file except in compliance with the License.
+#   You may obtain a copy of the License at
+#
+#       http://www.apache.org/licenses/LICENSE-2.0
+#
+#   Unless required by applicable law or agreed to in writing, software
+#   distributed under the License is distributed on an "AS IS" BASIS,
+#   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#   See the License for the specific language governing permissions and
+#   limitations under the License.
+
+import argparse
+import datetime
+import logging
+import os
+import pcbnew
+import subprocess
+import tempfile
+
+from contextlib import contextmanager
+
+logging.basicConfig(level=logging.DEBUG)
+logger = logging.getLogger(__name__)
+
+_LAYER_NAME = {
+    pcbnew.F_Cu: 'F.Cu',
+    pcbnew.B_Cu: 'B.Cu',
+    pcbnew.F_Adhes: 'F.Adhes',
+    pcbnew.B_Adhes: 'B.Adhes',
+    pcbnew.F_SilkS: 'F.SilkS',
+    pcbnew.B_SilkS: 'B.SilkS',
+    pcbnew.F_Paste: 'F.Paste',
+    pcbnew.B_Paste: 'B.Paste',
+    pcbnew.F_Mask: 'F.Mask',
+    pcbnew.B_Mask: 'B.Mask',
+    pcbnew.Edge_Cuts: 'Edge.Cuts',
+    pcbnew.Eco1_User: 'Eco1.User',
+    pcbnew.Eco2_User: 'Eco2.User',
+    pcbnew.F_Fab: 'F.Fab',
+    pcbnew.B_Fab: 'B.Fab',
+    #TODO: add the rest
+}
+
+@contextmanager
+def versioned_board(filename):
+    versioned_contents = _get_versioned_contents(filename)
+    with tempfile.NamedTemporaryFile(suffix='.kicad_pcb') as temp_pcb:
+        logger.debug('Writing to %s', temp_pcb.name)
+        temp_pcb.write(versioned_contents)
+        temp_pcb.flush()
+
+        logger.debug('Load board')
+        board = pcbnew.LoadBoard(temp_pcb.name)
+        yield board
+
+def get_layer_name(kicad_layer_id):
+    if kicad_layer_id in _LAYER_NAME:
+        return _LAYER_NAME[kicad_layer_id]
+    else:
+        return 'Unknown(%r)' % (kicad_layer_id,)
+
+@contextmanager
+def get_plotter(pcb_filename, build_directory):
+    with versioned_board(pcb_filename) as board:
+        yield GerberPlotter(board, build_directory)
+
+class GerberPlotter(object):
+    def __init__(self, board, build_directory):
+        self.board = board
+        self.build_directory = build_directory
+        self.plot_controller = pcbnew.PLOT_CONTROLLER(board)
+        self.plot_options = self.plot_controller.GetPlotOptions()
+        self.plot_options.SetOutputDirectory(build_directory)
+
+        self.plot_options.SetPlotFrameRef(False)
+        self.plot_options.SetLineWidth(pcbnew.FromMM(0.35))
+        self.plot_options.SetScale(1)
+        self.plot_options.SetUseAuxOrigin(True)
+        self.plot_options.SetMirror(False)
+        self.plot_options.SetExcludeEdgeLayer(True)
+
+    def plot(self, layer, plot_format):
+        logger.info('Plotting layer %s (kicad layer=%r)', get_layer_name(layer), layer)
+        layer_name = get_layer_name(layer)
+        self.plot_controller.SetLayer(layer)
+        self.plot_controller.OpenPlotfile(layer_name, plot_format , 'Plot')
+        output_filename = self.plot_controller.GetPlotFileName()
+        
+        self.plot_controller.PlotLayer()
+        self.plot_controller.ClosePlot()
+        return output_filename
+
+    def plot_drill(self):
+        board_name = os.path.splitext(os.path.basename(self.board.GetFileName()))[0]
+        logger.info('Plotting drill file')
+        drill_writer = pcbnew.EXCELLON_WRITER(self.board)
+        drill_writer.SetMapFileFormat(pcbnew.PLOT_FORMAT_PDF)
+
+        mirror = False
+        minimalHeader = False
+        offset = pcbnew.wxPoint(0, 0)
+        merge_npth = True
+        drill_writer.SetOptions(mirror, minimalHeader, offset, merge_npth)
+
+        metric_format = True
+        drill_writer.SetFormat(metric_format)
+
+        generate_drill = True
+        generate_map = True
+        drill_writer.CreateDrillandMapFilesSet(self.build_directory, generate_drill, generate_map)
+
+        drill_file_name = os.path.join(
+            self.build_directory,
+            '%s.drl' % (board_name,)
+        )
+
+        map_file_name = os.path.join(
+            self.build_directory,
+            '%s-drl_map.pdf' % (board_name,)
+        )
+        return drill_file_name, map_file_name
+
+def _get_versioned_contents(filename):
+    with open(filename, 'rb') as pcb:
+        original_contents = pcb.read()
+        version_info = get_version_info()
+        return original_contents \
+            .replace('COMMIT: deadbeef', 'COMMIT: ' + version_info['revision']) \
+            .replace('DATE: YYYY-MM-DD', 'DATE: ' + version_info['date'])
+
+def get_version_info():
+    git_rev = subprocess.check_output([
+        'git',
+        'rev-parse',
+        '--short',
+        'HEAD',
+    ]).strip()
+
+    return {
+        'revision': git_rev,
+        'date': datetime.date.today().strftime('%Y-%m-%d'),
+    }
+
+if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description='Test pcb util')
+    parser.add_argument('input_file', help='Input .kicad_pcb file')
+    args = parser.parse_args()
+    with versioned_board(args.input_file) as board:
+        logger.info('Loaded %s', board.GetFileName())
+        for module in board.GetModules():
+            logger.info('Module %s: %s', module.GetReference(), module.GetValue())
+ 
--- a/tinyPEPPER/doc/placement_back.svg
+++ b/tinyPEPPER/doc/placement_back.svg
--- a/tinyPEPPER/doc/placement_front.svg
+++ b/tinyPEPPER/doc/placement_front.svg
--- a/tinyPEPPER/doc/svg_processor.py
+++ b/tinyPEPPER/doc/svg_processor.py
@@ -0,0 +1,77 @@
+#   Copyright 2015 Scott Bezek
+#
+#   Licensed under the Apache License, Version 2.0 (the "License");
+#   you may not use this file except in compliance with the License.
+#   You may obtain a copy of the License at
+#
+#       http://www.apache.org/licenses/LICENSE-2.0
+#
+#   Unless required by applicable law or agreed to in writing, software
+#   distributed under the License is distributed on an "AS IS" BASIS,
+#   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#   See the License for the specific language governing permissions and
+#   limitations under the License.
+
+import logging
+import re
+import xml
+from xml.dom import minidom
+
+"""
+Processes SVG files generated by pcbnew to colorize and merge
+"""
+
+logger = logging.getLogger(__name__)
+
+class SvgProcessor(object):
+
+    def __init__(self, input_file):
+        self.dom = minidom.parse(input_file)
+        self.svg_node = self.dom.documentElement
+
+    def apply_color_transform(self, transform_function):
+        # Set fill and stroke on all groups
+        for group in self.svg_node.getElementsByTagName('g'):
+            SvgProcessor._apply_transform(group, {
+                'fill': transform_function,
+                'stroke': transform_function,
+            })
+
+    def import_groups(self, from_svg_processor):
+        for child in from_svg_processor.svg_node.childNodes:
+            if child.nodeType != child.ELEMENT_NODE or child.tagName != 'g':
+                continue
+            group = child
+            output_node = self.dom.importNode(group, True)
+            self.svg_node.appendChild(output_node)
+
+    def write(self, filename):
+        with open(filename, 'wb') as output_file:
+            self.svg_node.writexml(output_file)
+
+    def wrap_with_group(self, attrs):
+        parent = self.svg_node
+        wrapper = self.dom.createElement("g")
+        for k,v in attrs.items():
+            wrapper.setAttribute(k,v)
+
+        for child in parent.getElementsByTagName('g'):
+            parent.removeChild(child)
+            wrapper.appendChild(child)
+
+        parent.appendChild(wrapper)
+
+    @staticmethod
+    def _apply_transform(node, values):
+        original_style = node.attributes['style'].value
+        for (k,v) in values.items():
+            escaped_key = re.escape(k)
+            m = re.search(r'\b' + escaped_key + r':(?P<value>[^;]*);', original_style)
+            if m:
+                transformed_value = v(m.group('value'))
+                original_style = re.sub(
+                    r'\b' + escaped_key + r':[^;]*;',
+                    k + ':' + transformed_value + ';',
+                    original_style)
+        node.attributes['style'] = original_style
+
--- a/tinyPEPPER/fp-lib-table
+++ b/tinyPEPPER/fp-lib-table
@@ -0,0 +1,3 @@
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+)
--- a/tinyPEPPER/single_esc.sch
+++ b/tinyPEPPER/single_esc.sch
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+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:custom
+LIBS:tinyPEPPER-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 4 5
+Title ""
+Date "7 oct 2016"
+Rev ""
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+Wire Wire Line
+	2150 3250 2950 3250
+Wire Wire Line
+	4200 1700 1800 1700
+Wire Wire Line
+	4200 2350 4200 1700
+Connection ~ 8350 5000
+Wire Wire Line
+	8350 5000 9700 5000
+Wire Wire Line
+	8350 5150 8150 5150
+Wire Wire Line
+	8350 4800 8350 5150
+Wire Wire Line
+	3850 5250 3850 3850
+Wire Wire Line
+	3850 5250 7300 5250
+Wire Wire Line
+	3950 4700 7300 4700
+Wire Wire Line
+	8400 3750 8400 4100
+Wire Wire Line
+	8400 4100 8150 4100
+Connection ~ 8400 3900
+Wire Wire Line
+	8400 3900 9700 3900
+Wire Wire Line
+	5900 3650 5900 3350
+Wire Wire Line
+	7300 3650 5900 3650
+Wire Wire Line
+	4050 3850 4050 4200
+Wire Wire Line
+	4050 4200 7300 4200
+Wire Wire Line
+	8150 3250 8400 3250
+Connection ~ 8400 2850
+Wire Wire Line
+	8400 2850 9700 2850
+Wire Wire Line
+	8400 3050 8150 3050
+Wire Wire Line
+	8400 2700 8400 3050
+Wire Wire Line
+	5900 2600 5900 3050
+Wire Wire Line
+	7300 2600 5900 2600
+Wire Wire Line
+	3950 3850 3950 4700
+Wire Wire Line
+	5900 3350 4900 3350
+Wire Wire Line
+	4900 3150 7300 3150
+Wire Wire Line
+	5900 3050 4900 3050
+Wire Wire Line
+	9200 1950 9200 2200
+Wire Wire Line
+	9200 1950 9600 1950
+Wire Wire Line
+	9400 1550 9400 2200
+Wire Wire Line
+	9600 1950 9600 2200
+Connection ~ 9400 1950
+Wire Wire Line
+	9400 1550 4000 1550
+Wire Wire Line
+	4000 1550 4000 2350
+Wire Wire Line
+	2600 2950 2950 2950
+Wire Wire Line
+	2600 2950 2600 6100
+Wire Wire Line
+	2600 6100 9400 6100
+Wire Wire Line
+	9400 6100 9400 5800
+Wire Wire Line
+	2500 2850 2950 2850
+Wire Wire Line
+	2500 2850 2500 6200
+Wire Wire Line
+	2500 6200 9600 6200
+Wire Wire Line
+	9600 6200 9600 5800
+Wire Wire Line
+	3900 2350 3900 2150
+Wire Wire Line
+	3900 2150 2700 2150
+Wire Wire Line
+	2700 2150 2700 6000
+Wire Wire Line
+	2700 6000 9200 6000
+Wire Wire Line
+	9200 6000 9200 5800
+Wire Wire Line
+	2250 3150 2950 3150
+Wire Wire Line
+	2250 2800 2250 3150
+Wire Wire Line
+	1750 2800 2250 2800
+Wire Wire Line
+	2350 3050 2950 3050
+Wire Wire Line
+	2350 2250 2350 3050
+Wire Wire Line
+	1700 2250 5000 2250
+Connection ~ 2350 2250
+Wire Wire Line
+	5000 3250 4900 3250
+Wire Wire Line
+	5000 2250 5000 3250
+Connection ~ 3700 2250
+Wire Wire Line
+	2000 2250 2000 2350
+Connection ~ 2000 2250
+Wire Wire Line
+	2000 2650 2000 2800
+Connection ~ 2000 2800
+Wire Wire Line
+	2200 2650 2200 2800
+Connection ~ 2200 2800
+Wire Wire Line
+	2200 2250 2200 2350
+Connection ~ 2200 2250
+Connection ~ 1850 2250
+Connection ~ 1850 2800
+Wire Wire Line
+	1850 2350 1850 2250
+Wire Wire Line
+	1850 2750 1850 3000
+Wire Wire Line
+	3700 2350 3700 2250
+Wire Wire Line
+	2150 3550 2150 3250
+Wire Wire Line
+	1850 3300 1850 3550
+Wire Wire Line
+	8150 2500 8450 2500
+Wire Wire Line
+	8400 2700 8150 2700
+Wire Wire Line
+	8150 3550 8400 3550
+Wire Wire Line
+	8400 3750 8150 3750
+Wire Wire Line
+	8150 4600 8350 4600
+Wire Wire Line
+	8350 4800 8150 4800
+Wire Wire Line
+	1850 3550 2150 3550
+$Comp
+L TP BL_TX1
+U 1 1 58750948
+P 1825 1900
+AR Path="/57F7AC44/58750948" Ref="BL_TX1"  Part="1" 
+AR Path="/57F7B0C0/58750948" Ref="BL_TX2"  Part="1" 
+AR Path="/57FB3AAC/58750948" Ref="BL_TX3"  Part="1" 
+AR Path="/57FB3AF9/58750948" Ref="BL_TX4"  Part="1" 
+F 0 "BL_TX3" H 1975 1900 60  0000 C CNN
+F 1 "TP" H 1975 2050 60  0001 C CNN
+F 2 "custom:TP_smd_0.5x0.4" H 1825 1900 60  0001 C CNN
+F 3 "~" H 1825 1900 60  0000 C CNN
+	1    1825 1900
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	2125 1900 4100 1900
+Wire Wire Line
+	4100 1900 4100 2350
+$EndSCHEMATC
--- a/tinyPEPPER/tinyPEPPER.cmp
+++ b/tinyPEPPER/tinyPEPPER.cmp
@@ -0,0 +1,339 @@
+Cmp-Mod V01 Created by CvPcb (2013-jul-07)-stable date = Fri 07 Oct 2016 07:27:34 PM CEST
+
+BeginCmp
+TimeStamp = /57F7AC44/57F791A3;
+Reference = C201;
+ValeurCmp = C;
+IdModule  = SM1210;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F796EB;
+Reference = C202;
+ValeurCmp = 100n;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F791A3;
+Reference = C301;
+ValeurCmp = C;
+IdModule  = SM1210;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F796EB;
+Reference = C302;
+ValeurCmp = 100n;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F76A91;
+Reference = FET201;
+ValeurCmp = IRLML6244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F781FC;
+Reference = FET202;
+ValeurCmp = IRLML2244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F782D1;
+Reference = FET203;
+ValeurCmp = IRLML6244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F76A73;
+Reference = FET204;
+ValeurCmp = IRLML2244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F78363;
+Reference = FET205;
+ValeurCmp = IRLML6244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F780F5;
+Reference = FET206;
+ValeurCmp = IRLML2244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F76A91;
+Reference = FET301;
+ValeurCmp = IRLML6244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F781FC;
+Reference = FET302;
+ValeurCmp = IRLML2244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F782D1;
+Reference = FET303;
+ValeurCmp = IRLML6244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F76A73;
+Reference = FET304;
+ValeurCmp = IRLML2244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F78363;
+Reference = FET305;
+ValeurCmp = IRLML6244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F780F5;
+Reference = FET306;
+ValeurCmp = IRLML2244;
+IdModule  = sot23;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F78EAB;
+Reference = OUT_A201;
+ValeurCmp = TP;
+IdModule  = TP_VIA_PHASE;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F78EAB;
+Reference = OUT_A301;
+ValeurCmp = TP;
+IdModule  = TP_VIA_PHASE;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F78EC3;
+Reference = OUT_B201;
+ValeurCmp = TP;
+IdModule  = TP_VIA_PHASE;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F78EC3;
+Reference = OUT_B301;
+ValeurCmp = TP;
+IdModule  = TP_VIA_PHASE;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F78EC9;
+Reference = OUT_C201;
+ValeurCmp = TP;
+IdModule  = TP_VIA_PHASE;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F78EC9;
+Reference = OUT_C301;
+ValeurCmp = TP;
+IdModule  = TP_VIA_PHASE;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F79DFA;
+Reference = R201;
+ValeurCmp = 4k7;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F788EE;
+Reference = R202;
+ValeurCmp = 1k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F787A6;
+Reference = R203;
+ValeurCmp = 10k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F788F4;
+Reference = R204;
+ValeurCmp = 1k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F787B5;
+Reference = R205;
+ValeurCmp = 10k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F788FA;
+Reference = R206;
+ValeurCmp = 1k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F787C4;
+Reference = R207;
+ValeurCmp = 10k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F79DFA;
+Reference = R301;
+ValeurCmp = 4k7;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F788EE;
+Reference = R302;
+ValeurCmp = 1k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F787A6;
+Reference = R303;
+ValeurCmp = 10k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F788F4;
+Reference = R304;
+ValeurCmp = 1k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F787B5;
+Reference = R305;
+ValeurCmp = 10k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F788FA;
+Reference = R306;
+ValeurCmp = 1k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F787C4;
+Reference = R307;
+ValeurCmp = 10k;
+IdModule  = SM0402;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AE6B;
+Reference = TP1;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AE9E;
+Reference = TP2;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AEE5;
+Reference = TP3;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AEF4;
+Reference = TP4;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AF0C;
+Reference = TP5;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AF1B;
+Reference = TP6;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F78473;
+Reference = TP201;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F78482;
+Reference = TP202;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F78473;
+Reference = TP301;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F78482;
+Reference = TP302;
+ValeurCmp = TP;
+IdModule  = TP_1x1;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7AC44/57F76060;
+Reference = U201;
+ValeurCmp = EFM8BB10;
+IdModule  = QFN20;
+EndCmp
+
+BeginCmp
+TimeStamp = /57F7B0C0/57F76060;
+Reference = U301;
+ValeurCmp = EFM8BB10;
+IdModule  = QFN20;
+EndCmp
+
+EndListe
--- a/tinyPEPPER/tinyPEPPER.kicad_pcb
+++ b/tinyPEPPER/tinyPEPPER.kicad_pcb
--- a/tinyPEPPER/tinyPEPPER.pro
+++ b/tinyPEPPER/tinyPEPPER.pro
@@ -0,0 +1,82 @@
+update=Tue 10 Jan 2017 04:07:39 PM CET
+version=1
+last_client=kicad
+[cvpcb]
+version=1
+NetIExt=net
+[cvpcb/libraries]
+EquName1=devcms
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill="    0.600000"
+PadDrillOvalY="    0.600000"
+PadSizeH="    1.500000"
+PadSizeV="    1.500000"
+PcbTextSizeV="    1.500000"
+PcbTextSizeH="    1.500000"
+PcbTextThickness="    0.300000"
+ModuleTextSizeV="    1.000000"
+ModuleTextSizeH="    1.000000"
+ModuleTextSizeThickness="    0.150000"
+SolderMaskClearance="    0.000000"
+SolderMaskMinWidth="    0.000000"
+DrawSegmentWidth="    0.200000"
+BoardOutlineThickness="    0.100000"
+ModuleOutlineThickness="    0.150000"
+[pcbnew/libraries]
+LibDir=
+LibName1=sockets
+LibName2=connect
+LibName3=discret
+LibName4=pin_array
+LibName5=divers
+LibName6=smd_capacitors
+LibName7=smd_resistors
+LibName8=smd_crystal&oscillator
+LibName9=smd_dil
+LibName10=smd_transistors
+LibName11=libcms
+LibName12=display
+LibName13=led
+LibName14=dip_sockets
+LibName15=pga_sockets
+LibName16=valves
+LibName17=custom
+[general]
+version=1
+[eeschema]
+version=1
+LibDir=../tinyPEPPER;kicad_misc
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=microcontrollers
+LibName13=dsp
+LibName14=microchip
+LibName15=analog_switches
+LibName16=motorola
+LibName17=texas
+LibName18=intel
+LibName19=audio
+LibName20=interface
+LibName21=digital-audio
+LibName22=philips
+LibName23=display
+LibName24=cypress
+LibName25=siliconi
+LibName26=opto
+LibName27=atmel
+LibName28=contrib
+LibName29=valves
+LibName30=kicad_misc/custom
--- a/tinyPEPPER/tinyPEPPER.sch
+++ b/tinyPEPPER/tinyPEPPER.sch
@@ -0,0 +1,272 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:custom
+LIBS:tinyPEPPER-cache
+EELAYER 26 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 5
+Title ""
+Date "7 oct 2016"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L TP TP101
+U 1 1 57F7AE6B
+P 1600 2450
+F 0 "TP101" H 1750 2450 60  0000 C CNN
+F 1 "TP" H 1750 2600 60  0001 C CNN
+F 2 "custom:TP_powerpad" H 1600 2450 60  0001 C CNN
+F 3 "~" H 1600 2450 60  0000 C CNN
+	1    1600 2450
+	-1   0    0    1   
+$EndComp
+$Comp
+L TP TP102
+U 1 1 57F7AE9E
+P 1600 2700
+F 0 "TP102" H 1750 2700 60  0000 C CNN
+F 1 "TP" H 1750 2850 60  0001 C CNN
+F 2 "custom:TP_powerpad" H 1600 2700 60  0001 C CNN
+F 3 "~" H 1600 2700 60  0000 C CNN
+	1    1600 2700
+	-1   0    0    1   
+$EndComp
+$Comp
+L TP TP103
+U 1 1 57F7AEE5
+P 1600 3350
+F 0 "TP103" H 1750 3350 60  0000 C CNN
+F 1 "TP" H 1750 3500 60  0001 C CNN
+F 2 "custom:tp_SMD_0.6x1.2" H 1600 3350 60  0001 C CNN
+F 3 "~" H 1600 3350 60  0000 C CNN
+	1    1600 3350
+	-1   0    0    1   
+$EndComp
+$Comp
+L TP TP104
+U 1 1 57F7AEF4
+P 1600 3600
+F 0 "TP104" H 1750 3600 60  0000 C CNN
+F 1 "TP" H 1750 3750 60  0001 C CNN
+F 2 "custom:tp_SMD_0.6x1.2" H 1600 3600 60  0001 C CNN
+F 3 "~" H 1600 3600 60  0000 C CNN
+	1    1600 3600
+	-1   0    0    1   
+$EndComp
+$Comp
+L TP TP105
+U 1 1 57F7AF0C
+P 1600 3850
+F 0 "TP105" H 1750 3850 60  0000 C CNN
+F 1 "TP" H 1750 4000 60  0001 C CNN
+F 2 "custom:tp_SMD_0.6x1.2" H 1600 3850 60  0001 C CNN
+F 3 "~" H 1600 3850 60  0000 C CNN
+	1    1600 3850
+	-1   0    0    1   
+$EndComp
+$Comp
+L TP TP106
+U 1 1 57F7AF1B
+P 1600 4150
+F 0 "TP106" H 1750 4150 60  0000 C CNN
+F 1 "TP" H 1750 4300 60  0001 C CNN
+F 2 "custom:tp_SMD_0.6x1.2" H 1600 4150 60  0001 C CNN
+F 3 "~" H 1600 4150 60  0000 C CNN
+	1    1600 4150
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	1900 2450 4700 2450
+Wire Wire Line
+	1900 2700 4700 2700
+Wire Wire Line
+	1900 3350 2900 3350
+Wire Wire Line
+	1900 3600 3050 3600
+Wire Wire Line
+	1900 3850 2950 3850
+Wire Wire Line
+	1900 4150 2850 4150
+Text Label 2000 2450 0    60   ~ 0
+VCC
+Text Label 2000 2700 0    60   ~ 0
+GND
+Text Label 2000 3350 0    60   ~ 0
+RC_IN_0
+Text Label 2000 3600 0    60   ~ 0
+RC_IN_1
+$Sheet
+S 4700 2350 1900 850 
+U 57F7AC44
+F0 "single esc 1" 50
+F1 "single_esc.sch" 50
+F2 "RC_IN" I L 4700 3100 60 
+F3 "VCC" I L 4700 2450 60 
+F4 "GND" I L 4700 2700 60 
+$EndSheet
+Wire Wire Line
+	4700 3100 2900 3100
+Wire Wire Line
+	2900 3100 2900 3350
+Wire Wire Line
+	3050 3600 3050 4250
+Wire Wire Line
+	3050 4250 4700 4250
+Wire Wire Line
+	4450 3900 4700 3900
+Wire Wire Line
+	4450 2700 4450 6150
+Connection ~ 4450 2700
+Wire Wire Line
+	4600 2450 4600 5950
+Wire Wire Line
+	4600 3700 4700 3700
+Connection ~ 4600 2450
+$Sheet
+S 4700 3600 2450 800 
+U 57F7B0C0
+F0 "single esc 2" 50
+F1 "single_esc.sch" 50
+F2 "RC_IN" I L 4700 4250 60 
+F3 "VCC" I L 4700 3700 60 
+F4 "GND" I L 4700 3900 60 
+$EndSheet
+$Sheet
+S 4700 4700 2000 800 
+U 57FB3AAC
+F0 "single esc 3" 60
+F1 "single_esc.sch" 60
+F2 "RC_IN" I L 4700 5350 60 
+F3 "VCC" I L 4700 4800 60 
+F4 "GND" I L 4700 5000 60 
+$EndSheet
+$Sheet
+S 4750 5850 1900 800 
+U 57FB3AF9
+F0 "single esc 4" 60
+F1 "single_esc.sch" 60
+F2 "RC_IN" I L 4750 6500 60 
+F3 "VCC" I L 4750 5950 60 
+F4 "GND" I L 4750 6150 60 
+$EndSheet
+Wire Wire Line
+	4750 6500 2850 6500
+Wire Wire Line
+	2850 6500 2850 4150
+Wire Wire Line
+	2950 3850 2950 5350
+Wire Wire Line
+	2950 5350 4700 5350
+Wire Wire Line
+	4450 6150 4750 6150
+Connection ~ 4450 3900
+Wire Wire Line
+	4700 5000 4450 5000
+Connection ~ 4450 5000
+Wire Wire Line
+	4600 5950 4750 5950
+Connection ~ 4600 3700
+Wire Wire Line
+	4600 4800 4700 4800
+Connection ~ 4600 4800
+$Comp
+L CUSTOM_C C1000
+U 1 1 57FCB86E
+P 2800 2250
+F 0 "C1000" V 2571 2250 40  0000 C CNN
+F 1 "47u" V 2647 2250 40  0000 C CNN
+F 2 "Capacitors_SMD:C_0805" H 2838 2100 30  0001 C CNN
+F 3 "" H 2800 2250 60  0000 C CNN
+	1    2800 2250
+	0    1    1    0   
+$EndComp
+Wire Wire Line
+	2600 2250 2600 2450
+Connection ~ 2600 2450
+Wire Wire Line
+	3000 2250 3000 2700
+Connection ~ 3000 2700
+$Comp
+L hole H1
+U 1 1 58465F4C
+P 9500 2250
+F 0 "H1" H 9556 2537 60  0000 C CNN
+F 1 "hole" H 9556 2431 60  0000 C CNN
+F 2 "custom:mouting_hole" H 9500 2250 60  0001 C CNN
+F 3 "" H 9500 2250 60  0000 C CNN
+	1    9500 2250
+	1    0    0    -1  
+$EndComp
+$Comp
+L hole H2
+U 1 1 58466048
+P 9500 2700
+F 0 "H2" H 9556 2987 60  0000 C CNN
+F 1 "hole" H 9556 2881 60  0000 C CNN
+F 2 "custom:mouting_hole" H 9500 2700 60  0001 C CNN
+F 3 "" H 9500 2700 60  0000 C CNN
+	1    9500 2700
+	1    0    0    -1  
+$EndComp
+$Comp
+L hole H3
+U 1 1 58466181
+P 10200 2250
+F 0 "H3" H 10072 2197 60  0000 R CNN
+F 1 "hole" H 10072 2303 60  0000 R CNN
+F 2 "custom:mouting_hole" H 10200 2250 60  0001 C CNN
+F 3 "" H 10200 2250 60  0000 C CNN
+	1    10200 2250
+	-1   0    0    1   
+$EndComp
+$Comp
+L hole H4
+U 1 1 58466291
+P 10200 2700
+F 0 "H4" H 10072 2647 60  0000 R CNN
+F 1 "hole" H 10072 2753 60  0000 R CNN
+F 2 "custom:mouting_hole" H 10200 2700 60  0001 C CNN
+F 3 "" H 10200 2700 60  0000 C CNN
+	1    10200 2700
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	2600 2250 2650 2250
+Wire Wire Line
+	2950 2250 3000 2250
+$EndSCHEMATC