Ajout FishPeper
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OpenSky_BL/dma.h
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122
OpenSky_BL/dma.h
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/*
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Copyright 2016 fishpepper <AT> gmail.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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author: fishpepper <AT> gmail.com
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*/
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#ifndef DMA_H_
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#define DMA_H_
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// HAL_DMA CONFIG
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// see https://e2e.ti.com/support/wireless_connectivity/f/156/t/16922
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typedef struct {
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uint8_t SRCADDRH;
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uint8_t SRCADDRL;
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uint8_t DESTADDRH;
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uint8_t DESTADDRL;
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uint8_t LENH : 5;
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uint8_t VLEN : 3;
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uint8_t LENL : 8;
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uint8_t TRIG : 5;
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uint8_t TMODE : 2;
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uint8_t WORDSIZE : 1;
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uint8_t PRIORITY : 2;
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uint8_t M8 : 1;
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uint8_t IRQMASK : 1;
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uint8_t DESTINC : 2;
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uint8_t SRCINC : 2;
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} dma_desc_t;
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#define HI(a) (uint8_t) ((uint16_t)(a) >> 8 )
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#define LO(a) (uint8_t) ((uint16_t)(a) & 0xFF )
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#define SET_WORD(H, L, val) { (H) = HI(val); (L) = LO(val); }
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#define DMA_PRI_LOW 0x00 // Low, CPU has priority
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#define DMA_PRI_GUARANTEED 0x01 // Guaranteed, DMA at least every second try
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#define DMA_PRI_HIGH 0x02 // High, DMA has priority
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#define DMA_PRI_ABSOLUTE 0x03 // Highest, DMA has priority. Reserved for DMA port access.
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#define DMA_PRI_LOW 0x00 // Low, CPU has priority
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#define DMA_TRIG_NONE 0 // No trigger, setting DMAREQ.DMAREQx bit starts transfer
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#define DMA_TRIG_PREV 1 // DMA channel is triggered by completion of previous channel
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#define DMA_TRIG_T1_CH0 2 // Timer 1, compare, channel 0
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#define DMA_TRIG_T1_CH1 3 // Timer 1, compare, channel 1
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#define DMA_TRIG_T1_CH2 4 // Timer 1, compare, channel 2
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#define DMA_TRIG_T2_COMP 5 // Timer 2, compare
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#define DMA_TRIG_T2_OVFL 6 // Timer 2, overflow
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#define DMA_TRIG_T3_CH0 7 // Timer 3, compare, channel 0
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#define DMA_TRIG_T3_CH1 8 // Timer 3, compare, channel 1
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#define DMA_TRIG_T4_CH0 9 // Timer 4, compare, channel 0
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#define DMA_TRIG_T4_CH1 10 // Timer 4, compare, channel 1
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#define DMA_TRIG_ST 11 // Sleep Timer compare
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#define DMA_TRIG_IOC_0 12 // Port 0 I/O pin input transition
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#define DMA_TRIG_IOC_1 13 // Port 1 I/O pin input transition
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#define DMA_TRIG_URX0 14 // USART0 RX complete
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#define DMA_TRIG_UTX0 15 // USART0 TX complete
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#define DMA_TRIG_URX1 16 // USART1 RX complete
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#define DMA_TRIG_UTX1 17 // USART1 TX complete
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#define DMA_TRIG_FLASH 18 // Flash data write complete
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#define DMA_TRIG_RADIO 19 // RF packet byte received/transmit
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#define DMA_TRIG_ADC_CHALL 20 // ADC end of a conversion in a sequence, sample ready
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#define DMA_TRIG_ADC_CH0 21 // ADC end of conversion channel 0 in sequence, sample ready
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#define DMA_TRIG_ADC_CH1 22 // ADC end of conversion channel 1 in sequence, sample ready
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#define DMA_TRIG_ADC_CH2 23 // ADC end of conversion channel 2 in sequence, sample ready
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#define DMA_TRIG_ADC_CH3 24 // ADC end of conversion channel 3 in sequence, sample ready
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#define DMA_TRIG_ADC_CH4 25 // ADC end of conversion channel 4 in sequence, sample ready
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#define DMA_TRIG_ADC_CH5 26 // ADC end of conversion channel 5 in sequence, sample ready
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#define DMA_TRIG_ADC_CH6 27 // ADC end of conversion channel 6 in sequence, sample ready
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#define DMA_TRIG_ADC_CH7 28 // ADC end of conversion channel 7 in sequence, sample ready
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#define DMA_TRIG_ENC_DW 29 // AES encryption processor requests download input data
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#define DMA_TRIG_ENC_UP 30 // AES encryption processor requests upload output data
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#define DMA_VLEN_USE_LEN 0x00 // Use LEN for transfer count
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#define DMA_VLEN_FIRST_BYTE_P_1 0x01 // tx the nr of bytes specified by the 1st byte +1
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#define DMA_VLEN_FIRST_BYTE 0x02 // tx the nr of bytes indicated by the 1st byte (itself incl.)
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#define DMA_VLEN_FIRST_BYTE_P_2 0x03 // tx the nr of bytes specified by the 1st byte +2
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#define DMA_VLEN_FIRST_BYTE_P_3 0x04 // tx the nr of bytes specified by the 1st byte +3
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#define DMA_LEN_MAX 0xFF // The maximum length is always decided by the 1st byte
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#define DMA_WORDSIZE_BYTE 0x00 // tx a byte at a time
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#define DMA_WORDSIZE_WORD 0x01 // tx a 16-bit word at a time
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#define DMA_TMODE_SINGLE 0x00 // tx a single byte/word after each DMA trigger
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#define DMA_TMODE_BLOCK 0x01 // tx block of data (length len) after each DMA trigger
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#define DMA_TMODE_SINGLE_REPEATED 0x02 // tx single byte/word (after len transfers, rearm DMA)
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#define DMA_TMODE_BLOCK_REPEATED 0x03 // tx block of data (after len transfers, rearm DMA)
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#define DMA_ARM_ABORT 0x80
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#define DMA_ARM_CH0 (1<<0)
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#define DMA_SRCINC_0 0x00 // Increment source pointer by 0 bytes/words after each transfer
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#define DMA_SRCINC_1 0x01 // Increment source pointer by 1 bytes/words after each transfer
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#define DMA_SRCINC_2 0x02 // Increment source pointer by 2 bytes/words after each transfer
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#define DMA_SRCINC_M1 0x03 // Decrement source pointer by 1 bytes/words after each transfer
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#define DMA_DESTINC_0 0x00 // Increment dest pointer by 0 bytes/words after each transfer
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#define DMA_DESTINC_1 0x01 // Increment dest pointer by 1 bytes/words after each transfer
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#define DMA_DESTINC_2 0x02 // Increment dest pointer by 2 bytes/words after each transfer
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#define DMA_DESTINC_M1 0x03 // Decrement dest pointer by 1 bytes/words after each transfer
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#define DMA_IRQMASK_DISABLE 0x00 // Disable interrupt generation
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#define DMA_IRQMASK_ENABLE 0x01 // Enable interrupt generation upon DMA channel done
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#define DMA_M8_USE_8_BITS 0x00 // Use all 8 bits for transfer count
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#define DMA_M8_USE_7_BITS 0x01 // Use 7 LSB for transfer count
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#define DMAIRQ_DMAIF0 (1<<0)
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#define DMAIRQ_DMAIF1 (1<<1)
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#define DMAIRQ_DMAIF2 (1<<2)
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#define DMAIRQ_DMAIF3 (1<<3)
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#define DMAIRQ_DMAIF4 (1<<4)
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#endif // DMA_H_
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