Ajout FishPeper
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OpenSky/arch/stm32f1/hal_cc25xx.h
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OpenSky/arch/stm32f1/hal_cc25xx.h
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/*
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Copyright 2017 fishpepper <AT> gmail.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http:// www.gnu.org/licenses/>.
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author: fishpepper <AT> gmail.com
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*/
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#ifndef HAL_CC25XX_H__
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#define HAL_CC25XX_H__
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#include <stdint.h>
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void hal_cc25xx_init(void);
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void hal_cc25xx_set_register(uint8_t reg, uint8_t val);
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uint8_t hal_cc25xx_get_register(uint8_t address);
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void hal_cc25xx_strobe(uint8_t val);
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void hal_cc25xx_enable_receive(void);
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void hal_cc25xx_enable_transmit(void);
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void hal_cc25xx_enter_rxmode(void);
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void hal_cc25xx_enter_txmode(void);
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#define hal_cc25xx_rx_sleep() { delay_us(1352); }
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#define hal_cc25xx_tx_sleep() { delay_us(1250); }
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// not used on d4rii
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#define hal_cc25xx_disable_rf_interrupt() {}
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#define hal_cc25xx_setup_rf_dma(mode) {}
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#define hal_cc25xx_partnum_valid(p, v) ((p == 0x80) && (v = 0x03))
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uint8_t hal_cc25xx_get_status(void);
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static void hal_cc25xx_init_gpio(void);
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uint32_t hal_cc25xx_set_antenna(uint8_t id);
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void hal_cc25xx_set_gdo_mode(void);
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uint8_t hal_cc25xx_get_gdo_status(void);
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void hal_cc25xx_process_packet(volatile uint8_t *packet_received,
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volatile uint8_t *buffer, uint8_t maxlen);
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void hal_cc25xx_transmit_packet(volatile uint8_t *buffer, uint8_t len);
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void hal_cc25xx_read_fifo(uint8_t *buf, uint8_t len);
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void hal_cc25xx_register_read_multi(uint8_t address, uint8_t *buffer, uint8_t len);
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uint8_t hal_cc25xx_transmission_completed(void);
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// adress checks
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_00 ((0<<1) | (0<<0))
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_01 ((0<<1) | (1<<0))
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_10 ((1<<1) | (0<<0))
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_11 ((1<<1) | (1<<0))
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// append status bytes?
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#define CC2500_PKTCTRL1_APPEND_STATUS (1<<2)
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// crc autoflush
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#define CC2500_PKTCTRL1_CRC_AUTOFLUSH (1<<3)
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// Flags
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#define BURST_FLAG 0b01000000
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#define WRITE_FLAG 0b00000000
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#define READ_FLAG 0b10000000
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// Definitions for burst/single access to registers
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#define CC2500_WRITE_SINGLE 0x00
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#define CC2500_WRITE_BURST 0x40
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#define CC2500_READ_SINGLE 0x80
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#define CC2500_READ_BURST 0xC0
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#define CC2500_STATUS_STATE_IDLE (0<<4)
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#define CC2500_STATUS_STATE_RX (1<<4)
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#define CC2500_STATUS_STATE_TX (2<<4)
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#define CC2500_STATUS_STATE_FSTXON (3<<4)
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#define CC2500_STATUS_STATE_CALIBRATE (4<<4)
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#define CC2500_STATUS_STATE_SETTLING (5<<4)
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#define CC2500_STATUS_STATE_RXFIFO_OVF (6<<4)
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#define CC2500_STATUS_STATE_TXFIFO_OVF (7<<4)
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#define hal_cc25xx_get_register_burst(x) hal_cc25xx_get_register(x | READ_FLAG | BURST_FLAG)
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// strobes
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#define RFST_SRES 0x30
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#define RFST_SFSTXON 0x31
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#define RFST_SXOFF 0x32
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#define RFST_SCAL 0x33
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#define RFST_SRX 0x34
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#define RFST_STX 0x35
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#define RFST_SIDLE 0x36
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#define RFST_SWOR 0x38
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#define RFST_SPWD 0x39
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#define RFST_SFRX 0x3A
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#define RFST_SFTX 0x3B
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#define RFST_SWORRST 0x3C
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#define RFST_SNOP 0x3D
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// Status registers
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#define PARTNUM 0x30|BURST_FLAG
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#define VERSION 0x31|BURST_FLAG
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#define FREQEST 0x32|BURST_FLAG
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#define LQI 0x33|BURST_FLAG
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#define RSSI 0x34|BURST_FLAG
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#define MARCSTATE 0x35|BURST_FLAG
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#define WORTIME1 0x36|BURST_FLAG
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#define WORTIME0 0x37|BURST_FLAG
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#define PKTSTATUS 0x38|BURST_FLAG
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#define VCO_VC_DAC 0x39|BURST_FLAG
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#define TXBYTES 0x3A|BURST_FLAG
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#define RXBYTES 0x3B|BURST_FLAG
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#define RCCTRL1_STATUS 0x3C|BURST_FLAG
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#define RCCTRL0_STATUS 0x3D|BURST_FLAG
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// Status byte states
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#define STB_IDLE 0x00
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#define STB_RX 0x10
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#define STB_TX 0x20
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#define STB_FSTXON 0x30
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#define STB_CALIBRATE 0x40
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#define STB_SETTLING 0x50
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#define STB_RX_OVF 0x60
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#define STB_TX_UNDF 0x70
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// Config registers addresses
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#define IOCFG2 0x00
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#define IOCFG1 0x01
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#define IOCFG0 0x02
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#define FIFOTHR 0x03
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#define SYNC1 0x04
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#define SYNC0 0x05
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#define PKTLEN 0x06
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#define PKTCTRL1 0x07
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#define PKTCTRL0 0x08
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#define ADDR 0x09
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#define CHANNR 0x0A
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#define FSCTRL1 0x0B
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#define FSCTRL0 0x0C
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#define FREQ2 0x0D
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#define FREQ1 0x0E
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#define FREQ0 0x0F
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#define MDMCFG4 0x10
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#define MDMCFG3 0x11
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#define MDMCFG2 0x12
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#define MDMCFG1 0x13
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#define MDMCFG0 0x14
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#define DEVIATN 0x15
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#define MCSM2 0x16
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#define MCSM1 0x17
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#define MCSM0 0x18
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#define FOCCFG 0x19
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#define BSCFG 0x1A
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#define AGCCTRL2 0x1B
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#define AGCCTRL1 0x1C
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#define AGCCTRL0 0x1D
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#define WOREVT1 0x1E
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#define WOREVT0 0x1F
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#define WORCTRL 0x20
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#define FREND1 0x21
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#define FREND0 0x22
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#define FSCAL3 0x23
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#define FSCAL2 0x24
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#define FSCAL1 0x25
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#define FSCAL0 0x26
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#define RCCTRL1 0x27
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#define RCCTRL0 0x28
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#define FSTEST 0x29
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#define PTEST 0x2A
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#define AGCTEST 0x2B
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#define TEST2 0x2C
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#define TEST1 0x2D
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#define TEST0 0x2E
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#define PA_TABLE0 0x3E
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// FIFO
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#define CC25XX_FIFO 0x3F
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#endif // HAL_CC25XX_H_
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