Ajout FishPeper
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205
OpenSky/arch/cc251x/hal_storage.c
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205
OpenSky/arch/cc251x/hal_storage.c
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/*
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Copyright 2017 fishpepper <AT> gmail.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http:// www.gnu.org/licenses/>.
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author: fishpepper <AT> gmail.com
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*/
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#include "hal_storage.h"
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#include <cc2510fx.h>
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#include "debug.h"
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#include "main.h"
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#include "delay.h"
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#include "wdt.h"
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__xdata HAL_DMA_DESC flash_dma_config;
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// no ini value -> sdcc does not init this!
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__code __at(STORAGE_LOCATION) uint8_t storage_on_flash[STORAGE_PAGE_SIZE];
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void hal_storage_init(void) {
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debug("hal_storage: init\n"); debug_flush();
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}
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void hal_storage_write(uint8_t *buffer, uint16_t len) {
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hal_storage_flash_write((uint16_t)storage_on_flash, buffer, len);
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}
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void hal_storage_read(uint8_t *storage_ptr, uint16_t len) {
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uint16_t i;
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debug("hal_storage: loading from flash: "); debug_flush();
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// copy from persistant flash to ram:
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for (i = 0; i < len; i++) {
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storage_ptr[i] = storage_on_flash[i];
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debug_put_hex8(storage_on_flash[i]); debug_putc(' '); debug_flush();
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wdt_reset();
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}
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}
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static void hal_storage_flash_write(uint16_t address, uint8_t *data, uint16_t len) {
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uint16_t i = 0;
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uint8_t *flash_ptr = 0;
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debug("hal_storage: will write page at 0x"); debug_flush();
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debug_put_hex8(address >> 8);
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debug_put_hex8(address & 0xff);
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debug_put_newline();
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// this is VERY important:
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// make sure to write an even number of bytes!
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// simply write one extra byte
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if (len & 0x0001) {
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debug("flash: corrected len to even\n");
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len++;
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}
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// disable interrupts
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cli();
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// cancel _ALL_ ongoing DMA transfers:
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DMAARM = DMA_ARM_ABORT | 0x1F;
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// high prio
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flash_dma_config.PRIORITY = DMA_PRI_HIGH;
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// irrelevant since we use LEN for transfer count
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flash_dma_config.M8 = DMA_M8_USE_8_BITS;
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// disable ints from this ch
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flash_dma_config.IRQMASK = DMA_IRQMASK_DISABLE;
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// use dma flash data write complete trigger
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flash_dma_config.TRIG = DMA_TRIG_FLASH;
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// single mode, see datasheet
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flash_dma_config.TMODE = DMA_TMODE_SINGLE;
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// one byte
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flash_dma_config.WORDSIZE = DMA_WORDSIZE_BYTE;
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// set src: address of data to be written
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SET_WORD(flash_dma_config.SRCADDRH, flash_dma_config.SRCADDRL, data);
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// destination is flash controller data reg
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SET_WORD(flash_dma_config.DESTADDRH, flash_dma_config.DESTADDRL, &X_FWDATA);
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// use LEN
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flash_dma_config.VLEN = DMA_VLEN_USE_LEN;
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// set length
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SET_WORD(flash_dma_config.LENH, flash_dma_config.LENL, len);
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// set srcinc to 1 byte
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flash_dma_config.SRCINC = DMA_SRCINC_1;
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// fixed, always write to FWDATA
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flash_dma_config.DESTINC = DMA_DESTINC_0;
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// Save pointer to the DMA configuration struct into DMA-channel 0
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// configuration registers
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SET_WORD(DMA0CFGH, DMA0CFGL, flash_dma_config);
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// waiting for the flash controller to be ready
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while (FCTL & FCTL_BUSY) {}
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// configure flash controller for 26mhz clock
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FWT = 0x2A; // (21 * 26) / (16);
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// set up address:
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SET_WORD(FADDRH, FADDRL, ((uint16_t)address)>>1);
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// re enable ints
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sei();
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debug("hal_storage: erasing page\n"); debug_flush();
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// disable interrupts
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cli();
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// clear any pending flags
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DMAIRQ = 0;
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// erase that page
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// has to be 2byte aligned. use a hack to place it at a given adress:
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hal_storage_flash_erase_page();
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// Wait for the erase operation to complete
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while (FCTL & FCTL_BUSY) {}
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// FCTL = 0;
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// re enable ints
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sei();
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debug("hal_storage: erase done\n"); debug_flush();
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debug("hal_storage: will write ["); debug_flush();
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i = 0;
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while (i < len) {
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debug_put_hex8(((uint8_t *)data)[i++]);
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debug_put_hex8(((uint8_t *)data)[i++]);
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debug_putc(' ');
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debug_flush();
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}
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debug("]\n");
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debug("hal_storage: will write flash now\n"); debug_flush();
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// disable interrupts
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cli();
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// arm the DMA channel, so that a DMA trigger will initiate DMA writing
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DMAARM = DMA_ARM_CH0;
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NOP();
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// enable flash write. this generates a DMA trigger.
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// must be aligned on a 2-byte boundary and is therefor implemented in assembly!
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hal_storage_flash_enable_write();
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// wait for dma finish
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while (!(DMAIRQ & DMAIRQ_DMAIF0)) {
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wdt_reset();
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}
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// wait until flash controller not busy
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while (FCTL & (FCTL_BUSY | FCTL_SWBUSY)) {}
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sei();
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// by now, the transfer is completed, so the transfer count is reached.
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// the DMA channel 0 interrupt flag is then set, so we clear it here.
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DMAIRQ &= ~DMAIRQ_DMAIF0;
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debug("hal_storage: read back [");
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// copy from persistant flash to ram:
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flash_ptr = address;
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for (i = 0; i < len; i++) {
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debug_put_hex8(*flash_ptr++); debug_putc(' '); debug_flush();
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wdt_reset();
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}
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debug("]\n");
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debug("hal_storage: write done");
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}
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void hal_storage_flash_enable_write(void) {
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__asm
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.even // IMPORTANT: PLACE THIS ON A 2BYTE BOUNDARY!
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ORL _FCTL, #0x02; // FCTL |= FCTL_WRITE
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NOP;
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__endasm;
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}
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void hal_storage_flash_erase_page(void) {
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__asm
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.even // IMPORTANT: PLACE THIS ON A 2BYTE BOUNDARY!
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ORL _FCTL, #0x01; // FCTL |= FCTL_ERASE
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NOP; // required sequence!
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__endasm;
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}
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