Ajout FishPeper
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276
OpenSky/arch/cc251x/hal_cc25xx.h
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276
OpenSky/arch/cc251x/hal_cc25xx.h
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/*
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Copyright 2017 fishpepper <AT> gmail.com
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http:// www.gnu.org/licenses/>.
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author: fishpepper <AT> gmail.com
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*/
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#ifndef HAL_CC25XX_H_
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#define HAL_CC25XX_H_
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#include <stdint.h>
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#include "hal_defines.h"
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#include "config.h"
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#include <cc2510fx.h>
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#define CC25XX_FIFO FIFO
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#define hal_cc25xx_set_register(reg, val) { reg = val; }
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#define hal_cc25xx_strobe(val) { RFST = val; }
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#define hal_cc25xx_get_register(r) (r)
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#define hal_cc25xx_get_register_burst(r) (r)
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#ifdef RF_LNA_PORT
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#define RF_LNA_ENABLE() { PORT2BIT(RF_LNA_PORT, RF_LNA_PIN) = RF_LNA_ON_LEVEL; }
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#define RF_LNA_DISABLE() { PORT2BIT(RF_LNA_PORT, RF_LNA_PIN) = ~RF_LNA_ON_LEVEL; }
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#define RF_PA_ENABLE() { PORT2BIT(RF_PA_PORT, RF_PA_PIN) = RF_PA_ON_LEVEL; }
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#define RF_PA_DISABLE() { PORT2BIT(RF_PA_PORT, RF_PA_PIN) = ~RF_PA_ON_LEVEL; }
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#endif // RF_LNA_PORT
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#ifdef RF_ANTENNA_SWITCH_PORT
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#define RF_ANTENNA_SELECT_A() { PORT2BIT(RF_ANTENNA_SWITCH_PORT, RF_ANTENNA_SWITCH_PIN) = RF_ANTENNA_A_LEVEL; }
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#define RF_ANTENNA_SELECT_B() { PORT2BIT(RF_ANTENNA_SWITCH_PORT, RF_ANTENNA_SWITCH_PIN) = ~RF_ANTENNA_A_LEVEL; }
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#endif // RF_ANTENNA_SWITCH_PORT
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#ifdef RF_HIGH_GAIN_MODE_PORT
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#define RF_HIGH_GAIN_MODE_ENABLE() { \
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PORT2BIT(RF_HIGH_GAIN_MODE_PORT, RF_HIGH_GAIN_MODE_PIN) = RF_HIGH_GAIN_MODE_ON_LEVEL; }
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#define RF_HIGH_GAIN_MODE_DISBALE() { \
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PORT2BIT(RF_HIGH_GAIN_MODE_PORT, RF_HIGH_GAIN_MODE_PIN) = ~RF_HIGH_GAIN_MODE_ON_LEVEL; }
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#endif // RF_HIGH_GAIN_MODE_PORT
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#ifdef RF_BYPASS_MODE_PORT
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#define RF_BYPASS_MODE_ENABLE() { PORT2BIT(RF_BYPASS_MODE_PORT, RF_BYPASS_MODE_PIN) = RF_BYPASS_MODE_ON_LEVEL; }
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#define RF_BYPASS_MODE_DISABLE() { PORT2BIT(RF_BYPASS_MODE_PORT, RF_BYPASS_MODE_PIN) = ~RF_BYPASS_MODE_ON_LEVEL; }
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#endif // RF_BYPASS_MODE_PORT
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uint32_t hal_cc25xx_set_antenna(uint8_t id);
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#define hal_cc25xx_process_packet(packet_received, buffer, maxlen) {}
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void hal_cc25xx_init(void);
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#define hal_cc25xx_set_gdo_mode() {}
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void hal_cc25xx_disable_rf_interrupt(void);
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#define hal_cc25xx_rx_sleep() { delay_us(1000); }
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#define hal_cc25xx_tx_sleep() { delay_us(900); }
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void hal_cc25xx_enter_rxmode(void);
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void hal_cc25xx_enter_txmode(void);
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void hal_cc25xx_setup_rf_dma(uint8_t mode);
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void hal_cc25xx_enable_receive(void);
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void hal_cc25xx_transmit_packet(volatile uint8_t *buffer, uint8_t len);
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uint8_t hal_cc25xx_transmission_completed(void);
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void hal_cc25xx_rf_interrupt(void) __interrupt RF_VECTOR;
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#define hal_cc25xx_partnum_valid(p, v) ((p == 0x81) && (v = 0x04))
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#define PERCFG_U0CFG (1<<0)
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#define PERCFG_U1CFG (1<<1)
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#define PERCFG_T4CFG (1<<4)
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#define PERCFG_T3CFG (1<<5)
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#define PERCFG_T1CFG (1<<6)
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#define IEN0_RFTXRXIE (1<<0)
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#define IEN0_ADCIE (1<<1)
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#define IEN0_URX0IE (1<<2)
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#define IEN0_URX1IE (1<<3)
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#define IEN0_ENCIE (1<<4)
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#define IEN0_STIE (1<<5)
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#define IEN0_EA (1<<7)
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// bit 7 - unused
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// bit 6 - unused
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#define PICTL_P2IEN (1<<5)
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#define PICTL_P0IENH (1<<4)
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#define PICTL_P0IENL (1<<3)
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#define PICTL_P2ICON (1<<2)
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#define PICTL_P1ICON (1<<1)
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#define PICTL_P0ICON (1<<0)
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#define IEN1_P0IE (1<<5)
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#define IEN1_T4IE (1<<4)
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#define IEN1_T3IE (1<<3)
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#define IEN1_T2IE (1<<2)
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#define IEN1_T1IE (1<<1)
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#define IEN1_DMAIE (1<<0)
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#define IEN2_RFIE (1<<0)
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#define IEN2_P2IE (1<<1)
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#define IEN2_UTX0IE (1<<2)
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#define IEN2_UTX1IE (1<<3)
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#define IEN2_P1IE (1<<4)
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#define IEN2_WDTIE (1<<5)
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#define U0GCR_ORDER (1<<5)
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#define U0GCR_CPHA (1<<6)
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#define U0GCR_CPOL (1<<7)
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#define U0CSR_TX_BYTE (1<<1)
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#define U1GCR_ORDER (1<<5)
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#define U1GCR_CPHA (1<<6)
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#define U1GCR_CPOL (1<<7)
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#define UxCSR_RX_ENABLE (1<<6)
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#define UxCSR_RX_BYTE (1<<2)
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#define UxCSR_TX_BYTE (1<<1)
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#define RFST_SNOP 0x05
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#define RFST_SIDLE 0x04
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#define RFST_STX 0x03
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#define RFST_SRX 0x02
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#define RFST_SCAL 0x01
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#define RFST_SFSTXON 0x00
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// statemachine on cc2510 is different.
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// instead of SF*X we should use SIDLE
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#define RFST_SFTX RFST_SIDLE
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#define RFST_SFRX RFST_SIDLE
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// append status
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#define CC2500_PKTCTRL1_APPEND_STATUS (1<<2)
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// crc autoflush
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#define CC2500_PKTCTRL1_CRC_AUTOFLUSH (1<<3)
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// adress checks
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_00 ((0<<1) | (0<<0))
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_01 ((0<<1) | (1<<0))
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_10 ((1<<1) | (0<<0))
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#define CC2500_PKTCTRL1_FLAG_ADR_CHECK_11 ((1<<1) | (1<<0))
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#define CLKCON_TICKSPD_001 (0b00001000)
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#define CLKCON_TICKSPD_010 (0b00010000)
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#define CLKCON_TICKSPD_011 (0b00011000)
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#define CLKCON_TICKSPD_100 (0b00100000)
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#define CLKCON_TICKSPD_101 (0b00101000)
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#define CLKCON_TICKSPD_110 (0b00110000)
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#define CLKCON_TICKSPD_111 (0b00111000)
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#define CLKCON_OSC32K (1<<7)
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#define ADCCON2_SREF_INT (0b00<<6)
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#define ADCCON2_SREF_EXT (0b01<<6)
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#define ADCCON2_SREF_AVDD (0b10<<6)
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#define ADCCON2_SREF_EXTDIFF (0b11<<6)
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#define ADCCON2_SDIV_7BIT (0b00<<4)
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#define ADCCON2_SDIV_9BIT (0b01<<4)
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#define ADCCON2_SDIV_10BIT (0b10<<4)
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#define ADCCON2_SDIV_12BIT (0b11<<4)
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#define ADCCON2_SCH_AIN0 (0b0000<<0)
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#define ADCCON2_SCH_AIN1 (0b0001<<0)
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#define ADCCON2_SCH_AIN2 (0b0010<<0)
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#define ADCCON2_SCH_AIN3 (0b0011<<0)
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#define ADCCON2_SCH_AIN4 (0b0100<<0)
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#define ADCCON2_SCH_AIN5 (0b0101<<0)
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#define ADCCON2_SCH_AIN6 (0b0110<<0)
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#define ADCCON2_SCH_AIN7 (0b0111<<0)
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#define ADCCON2_SCH_AIN0AIN1 (0b1000<<0)
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#define ADCCON2_SCH_AIN2AIN3 (0b1001<<0)
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#define ADCCON2_SCH_AIN4AIN5 (0b1010<<0)
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#define ADCCON2_SCH_AIN6AIN7 (0b1011<<0)
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#define ADCCON2_SCH_GND (0b1100<<0)
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#define ADCCON2_SCH_POSVREF (0b1101<<0)
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#define ADCCON2_SCH_TEMP (0b1110<<0)
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#define ADCCON2_SCH_VDD3 (0b1111<<0)
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#define ADCCON1_ST (1<<6)
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#define ADCCON1_STSEL_FULL_SPEED (0b01<<4)
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#define WDCTL_EN (1<<3)
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#define WDCTL_MODE (1<<2)
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#define WDCTL_INT (0b11)
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#define WDCTL_INT_1S (0b00)
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#define FCTL_BUSY (1<<7)
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#define FCTL_SWBUSY (1<<6)
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#define FCTL_WRITE (1<<1)
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#define FCTL_ERASE (1<<0)
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#define T1CTL_MODE_SUSPEND (0b00<<0)
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#define T1CTL_MODE_FREE_RUNNING (0b01<<0)
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#define T1CTL_MODE_MODULO (0b10<<0)
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#define T1CTL_MODE_UPDOWN (0b11<<0)
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#define T1CTL_DIV_1 (0b00<<2)
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#define T1CTL_DIV_8 (0b01<<2)
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#define T1CTL_DIV_32 (0b10<<2)
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#define T1CTL_DIV_128 (0b11<<2)
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#define T1CTL_OVFIF (1<<4)
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#define T1CTL_CH0_IF (1<<5)
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#define T1CTL_CH1_IF (1<<6)
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#define T1CTL_CH2_IF (1<<7)
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#define T3CTL_MODE_SUSPEND (0b00<<0)
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#define T3CTL_MODE_FREE_RUNNING (0b01<<0)
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#define T3CTL_MODE_MODULO (0b10<<0)
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#define T3CTL_MODE_UPDOWN (0b11<<0)
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#define T3CTL_CLR (1<<2)
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#define T3CTL_OVFIM (1<<3)
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#define T3CTL_START (1<<4)
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#define T3CTL_DIV_1 (0b000<<5)
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#define T3CTL_DIV_2 (0b001<<5)
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#define T3CTL_DIV_4 (0b010<<5)
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#define T3CTL_DIV_8 (0b011<<5)
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#define T3CTL_DIV_16 (0b100<<5)
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#define T3CTL_DIV_32 (0b101<<5)
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#define T3CTL_DIV_64 (0b110<<5)
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#define T3CTL_DIV_128 (0b111<<5)
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#define T4CTL_MODE_SUSPEND (0b00<<0)
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#define T4CTL_MODE_FREE_RUNNING (0b01<<0)
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#define T4CTL_MODE_MODULO (0b10<<0)
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#define T4CTL_MODE_UPDOWN (0b11<<0)
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#define T4CTL_CLR (1<<2)
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#define T4CTL_OVFIM (1<<3)
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#define T4CTL_START (1<<4)
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#define T4CTL_DIV_1 (0b000<<5)
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#define T4CTL_DIV_2 (0b001<<5)
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#define T4CTL_DIV_4 (0b010<<5)
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#define T4CTL_DIV_8 (0b011<<5)
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#define T4CTL_DIV_16 (0b100<<5)
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#define T4CTL_DIV_32 (0b101<<5)
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#define T4CTL_DIV_64 (0b110<<5)
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#define T4CTL_DIV_128 (0b111<<5)
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#define T1CCTLx_CAP_NO (0b00<<0)
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#define T1CCTLx_CAP_RISING (0b01<<0)
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#define T1CCTLx_CAP_FALLING (0b10<<0)
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#define T1CCTLx_CAP_BOTH (0b11<<0)
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#define T1CCTLx_MODE_CAPTURE (0<<2)
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#define T1CCTLx_MODE_COMPARE (1<<2)
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#define T1CCTLx_CMP_SET (0b000<<3)
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#define T1CCTLx_CMP_CLEAR (0b001<<3)
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#define T1CCTLx_CMP_TOGGLE (0b010<<3)
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#define T1CCTLx_CMP_SETCLR0 (0b011<<3)
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#define T1CCTLx_CMP_CLRSET0 (0b100<<3)
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#define T1CCTLx_CMP_RES0 (0b101<<3)
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#define T1CCTLx_CMP_RES1 (0b110<<3)
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#define T1CCTLx_CMP_RES2 (0b111<<3)
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#define T1CCTLx_IM (1<<6)
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#define T1CCTLx_CPSEL_RF (1<<7)
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// add missing defines
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#include <compiler.h>
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SFRX(TEST2, 0xDF23);
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SFRX(TEST1, 0xDF24);
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SFRX(TEST0, 0xDF25);
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#endif // HAL_CC25XX_H_
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