793 lines
25 KiB
C
793 lines
25 KiB
C
/**
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* @file hgtimer_v6.c
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* @author bxd
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* @brief super timer
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* @version
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* TXW80X
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* @date 2023-08-02
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*
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* @copyright Copyright (c) 2023
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*
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*/
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#include "typesdef.h"
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#include "list.h"
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#include "errno.h"
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#include "dev.h"
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#include "osal/irq.h"
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#include "osal/string.h"
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#include "hal/timer_device.h"
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#include "hal/pwm.h"
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#include "dev/pwm/hgpwm_v0.h"
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#include "dev/timer/hgtimer_v6.h"
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#include "hgtimer_v6_hw.h"
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/**********************************************************************************/
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/* COMM FUNCTION */
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/**********************************************************************************/
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#define HGTIMER_V6_HW_SUPTMRCON0_BIT (\
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LL_STRM_CON0_SUPTMR01_SYNC_MD_SEL(0x3) | \
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LL_STRM_CON0_SUPTMR23_SYNC_MD_SEL(0x3) | \
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LL_STRM_CON0_SUPTMR45_SYNC_MD_SEL(0x3) | \
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LL_SUPTMR_CON0_SUPTMR_GP0_EN | \
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LL_SUPTMR_CON0_SUPTMR_GP1_EN | \
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LL_SUPTMR_CON0_CPMC_SEL(0x1) | \
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LL_SUPTMR_CON0_LOAD_SEL(0x1) | \
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LL_SUPTMR_CON0_SUPTMR0_CNT_TYPE_SEL(0x1) | \
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LL_SUPTMR_CON0_SUPTMR1_CNT_TYPE_SEL(0x1) | \
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LL_SUPTMR_CON0_SUPTMR2_CNT_TYPE_SEL(0x1) | \
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LL_SUPTMR_CON0_SUPTMR3_CNT_TYPE_SEL(0x1) | \
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LL_SUPTMR_CON0_SUPTMR4_CNT_TYPE_SEL(0x1) | \
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LL_SUPTMR_CON0_SUPTMR5_CNT_TYPE_SEL(0x1) \
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)
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static int32 hgtimer_v6_switch_suptmr_index(struct hgtimer_v6 *dev)
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{
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switch ((uint32)(dev->hw_suptmrx)) {
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case ((uint32)HG_SUPTMR0_BASE):
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return 0;
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break;
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case ((uint32)HG_SUPTMR1_BASE):
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return 1;
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break;
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case ((uint32)HG_SUPTMR2_BASE):
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return 2;
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break;
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case ((uint32)HG_SUPTMR3_BASE):
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return 3;
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break;
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case ((uint32)HG_SUPTMR4_BASE):
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return 4;
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break;
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case ((uint32)HG_SUPTMR5_BASE):
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return 5;
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break;
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default:
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return -1;
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break;
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}
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}
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/**********************************************************************************/
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/* PWM FUNCTION START */
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/**********************************************************************************/
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static int32 hgtimer_v6_pwm_switch_func_cmd(enum hgpwm_v0_func_cmd param)
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{
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switch (param) {
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case (HGPWM_V0_FUNC_CMD_INIT):
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return HGTIMER_V6_PWM_FUNC_CMD_INIT;
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break;
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case (HGPWM_V0_FUNC_CMD_DEINIT):
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return HGTIMER_V6_PWM_FUNC_CMD_DEINIT;
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break;
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case (HGPWM_V0_FUNC_CMD_START):
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return HGTIMER_V6_PWM_FUNC_CMD_START;
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break;
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case (HGPWM_V0_FUNC_CMD_STOP):
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return HGTIMER_V6_PWM_FUNC_CMD_STOP;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
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return HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY;
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break;
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case (HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE):
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return HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE;
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break;
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case (HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD):
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return HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD;
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break;
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case (HGPWM_V0_FUNC_CMD_RELEASE_IRQ):
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return HGTIMER_V6_PWM_FUNC_CMD_RELEASE_IRQ;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER):
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return HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PRESCALER;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
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return HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY;
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break;
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default:
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return -1;
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break;
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}
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}
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static inline int32 hgtimer_v6_pwm_func_init(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
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int32 index = 0;
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if (dev->opened) {
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return -EBUSY;
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}
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if (pin_func(dev->dev.dev.dev_id, 1) != RET_OK) {
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return RET_ERR;
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}
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if ((p_config->duty < 0) || ((p_config->duty) > (p_config->period))) {
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return RET_ERR;
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}
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/* confirm which suptmr */
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index = hgtimer_v6_switch_suptmr_index(dev);
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if ((-1) == index) {
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return RET_ERR;
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}
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/* config regs */
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switch ((uint32)(dev->hw_suptmrx)) {
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case ((uint32)HG_SUPTMR0_BASE):
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hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR0_CNT_MOD_SEL(1);
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hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
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break;
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case ((uint32)HG_SUPTMR1_BASE):
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hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR1_CNT_MOD_SEL(1);
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hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
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break;
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case ((uint32)HG_SUPTMR2_BASE):
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hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR2_CNT_MOD_SEL(1);
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hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
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break;
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case ((uint32)HG_SUPTMR3_BASE):
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hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR3_CNT_MOD_SEL(1);
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hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
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break;
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case ((uint32)HG_SUPTMR4_BASE):
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hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR4_CNT_MOD_SEL(1);
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hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
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break;
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case ((uint32)HG_SUPTMR5_BASE):
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hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR5_CNT_MOD_SEL(1);
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hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
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break;
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default:
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return RET_ERR;
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break;
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}
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/* config PWMCON: PWMVA; PWMEN */
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hw_comm->SUPTMR_PWMCON &= ~(((1) << (6 + index)) | ((0) << (0 + index)));
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/* config period */
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hw_suptmrx->PR = p_config->period;
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/* config compare */
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hw_suptmrx->CMP = p_config->duty;
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/* clear current cnt */
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hw_suptmrx->CNT = 0;
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dev->opened = 1;
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dev->pwm_en = 1;
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_deinit(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
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int32 index = 0;
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if ((!dev->opened) || (!dev->pwm_en)) {
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return RET_OK;
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}
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/* confirm which suptmr */
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index = hgtimer_v6_switch_suptmr_index(dev);
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if ((-1) == index) {
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return RET_ERR;
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}
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irq_disable(dev->irq_num);
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pin_func(dev->dev.dev.dev_id, 0);
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/* comm reg CON1: CNTEN; */
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hw_comm->SUPTMR_CON1 &= ~((1) << (0 + index));
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/* comm reg PWMCON: PWMEN; */
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hw_comm->SUPTMR_PWMCON &= ~((1) << (0 + index));
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hw_suptmrx->CON = 0;
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/* clear current cnt */
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hw_suptmrx->CNT = 0;
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dev->opened = 0;
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dev->pwm_en = 0;
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_start(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
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int32 index = 0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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/* confirm which suptmr */
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index = hgtimer_v6_switch_suptmr_index(dev);
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if ((-1) == index) {
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return RET_ERR;
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}
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/* comm reg PWMCON: PWMEN*/
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hw_comm->SUPTMR_PWMCON |= (1) << (0 + index);
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/* comm reg CON1: CNTEN */
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hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_stop(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
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int32 index = 0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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/* confirm which suptmr */
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index = hgtimer_v6_switch_suptmr_index(dev);
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if ((-1) == index) {
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return RET_ERR;
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}
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/* comm reg PWMCON: PWMEN*/
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hw_comm->SUPTMR_PWMCON &= ~((1) << (0 + index));
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/* comm reg CON1: CNTEN */
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hw_comm->SUPTMR_CON1 &= ~((1) << (0 + index));
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_ioctl_set_period_duty(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
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int32 index = 0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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if ((p_config->duty < 0) || ((p_config->duty) > (p_config->period))) {
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return RET_ERR;
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}
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/* confirm which suptmr */
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index = hgtimer_v6_switch_suptmr_index(dev);
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if ((-1) == index) {
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return RET_ERR;
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}
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/* config period */
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hw_suptmrx->PR = p_config->period;
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/* config compare */
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hw_suptmrx->CMP = p_config->duty;
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/* clear current cnt */
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hw_suptmrx->CNT = 0;
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/* comm reg CON1: LOADEN */
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hw_comm->SUPTMR_CON1 |= (1) << (8 + index);
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_cmd_ioctl_set_prescaler(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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hw_suptmrx->CON = (hw_suptmrx->CON &~ (LL_SUPTMRx_CON_PSC(0x3FF))) | (LL_SUPTMRx_CON_PSC(p_config->param1));
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_cmd_ioctl_set_period_duty_immediately(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
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int32 index = 0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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/* confirm which suptmr */
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index = hgtimer_v6_switch_suptmr_index(dev);
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if ((-1) == index) {
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return RET_ERR;
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}
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/* comm reg PWMCON: PWMEN*/
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hw_comm->SUPTMR_PWMCON &= ~((1) << (0 + index));
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/* comm reg CON1: CNTEN */
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hw_comm->SUPTMR_CON1 &= ~((1) << (0 + index));
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hw_suptmrx->CNT = 0;
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hw_suptmrx->PR = p_config->period;
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hw_suptmrx->CMP = p_config->duty;
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/* comm reg PWMCON: PWMEN*/
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hw_comm->SUPTMR_PWMCON |= (1) << (0 + index);
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/* comm reg CON1: CNTEN */
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hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_request_irq_compare(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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dev->_pwm_irq_hdl = p_config->irq_hdl;
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dev->irq_data = p_config->irq_data;
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hw_suptmrx->CON |= LL_SUPTMRx_CON_CMPA_IE;
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irq_enable(dev->irq_num);
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_request_irq_period(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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dev->_pwm_irq_hdl = p_config->irq_hdl;
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dev->irq_data = p_config->irq_data;
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hw_suptmrx->CON |= LL_SUPTMRx_CON_UD_IE;
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irq_enable(dev->irq_num);
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return RET_OK;
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}
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static inline int32 hgtimer_v6_pwm_func_release_irq(struct hgtimer_v6 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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irq_disable(dev->irq_num);
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dev->_pwm_irq_hdl = NULL;
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dev->irq_data = 0;
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hw_suptmrx->CON &= ~(LL_SUPTMRx_CON_UD_IE | LL_SUPTMRx_CON_UD_IE);
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return RET_OK;
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}
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static int32 hgtimer_v6_pwm_config(struct hgtimer_v6 *dev, uint32 config, uint32 param)
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{
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struct hgpwm_v0_config *p_config;
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int32 hgtimer_v6_pwm_func_cmd = 0;
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int32 ret_val = RET_OK;
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/* Make sure the config struct pointer */
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if (!config) {
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return -EINVAL;
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}
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p_config = (struct hgpwm_v0_config *)config;
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hgtimer_v6_pwm_func_cmd = hgtimer_v6_pwm_switch_func_cmd(p_config->func_cmd);
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if ((-1) == hgtimer_v6_pwm_func_cmd) {
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return -EINVAL;
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}
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switch (hgtimer_v6_pwm_func_cmd) {
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case (HGTIMER_V6_PWM_FUNC_CMD_INIT):
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ret_val = hgtimer_v6_pwm_func_init(dev, p_config);
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break;
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case (HGTIMER_V6_PWM_FUNC_CMD_DEINIT):
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ret_val = hgtimer_v6_pwm_func_deinit(dev, p_config);
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break;
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case (HGTIMER_V6_PWM_FUNC_CMD_START):
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ret_val = hgtimer_v6_pwm_func_start(dev, p_config);
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break;
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case (HGTIMER_V6_PWM_FUNC_CMD_STOP):
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ret_val = hgtimer_v6_pwm_func_stop(dev, p_config);
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break;
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case (HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
|
|
ret_val = hgtimer_v6_pwm_func_ioctl_set_period_duty(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE):
|
|
ret_val = hgtimer_v6_pwm_func_request_irq_compare(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD):
|
|
ret_val = hgtimer_v6_pwm_func_request_irq_period(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V6_PWM_FUNC_CMD_RELEASE_IRQ):
|
|
ret_val = hgtimer_v6_pwm_func_release_irq(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PRESCALER):
|
|
ret_val = hgtimer_v6_pwm_func_cmd_ioctl_set_prescaler(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
|
|
ret_val = hgtimer_v6_pwm_func_cmd_ioctl_set_period_duty_immediately(dev, p_config);
|
|
break;
|
|
default:
|
|
ret_val = -ENOTSUPP;
|
|
break;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**********************************************************************************/
|
|
/* PWM FUNCTION END */
|
|
/**********************************************************************************/
|
|
|
|
|
|
/**********************************************************************************/
|
|
/* COUNTER FUNCTION START */
|
|
/**********************************************************************************/
|
|
static int32 hgtimer_v6_counter_switch_hal_type(struct hgtimer_v6 *dev, enum timer_type param)
|
|
{
|
|
|
|
switch (param) {
|
|
case (TIMER_TYPE_ONCE):
|
|
dev->type = HGTIMER_V6_TYPE_ONCE;
|
|
return 0;
|
|
break;
|
|
case (TIMER_TYPE_PERIODIC):
|
|
dev->type = HGTIMER_V6_TYPE_PERIODIC;
|
|
return 1;
|
|
break;
|
|
default:
|
|
return -1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int32 hgtimer_v6_counter_set_psc(struct hgtimer_v6 *timer, uint32 psc)
|
|
{
|
|
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
|
|
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
|
|
|
|
if (!dev->counter_en) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
hw_suptmrx->CON = (hw_suptmrx->CON & ~ LL_SUPTMRx_CON_PSC(0x3FF)) | LL_SUPTMRx_CON_PSC(psc);
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v6_counter_func_open(struct timer_device *timer, enum timer_type type, uint32 flags)
|
|
{
|
|
|
|
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
|
|
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
|
|
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
|
|
|
|
if (dev->opened) {
|
|
return -EBUSY;
|
|
}
|
|
|
|
if ((-1) == hgtimer_v6_counter_switch_hal_type(dev, type)) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
irq_enable(dev->irq_num);
|
|
|
|
switch (dev->type) {
|
|
/* TIMER_TYPE_ONCE */
|
|
case (HGTIMER_V6_TYPE_ONCE):
|
|
|
|
/* TIMER_TYPE_PERIODIC */
|
|
case (HGTIMER_V6_TYPE_PERIODIC):
|
|
|
|
/* TIMER_TYPE_COUNTER */
|
|
case (HGTIMER_V6_TYPE_COUNTER):
|
|
|
|
/* config regs */
|
|
switch ((uint32)(dev->hw_suptmrx)) {
|
|
case ((uint32)HG_SUPTMR0_BASE):
|
|
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR0_CNT_MOD_SEL(1);
|
|
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
|
|
break;
|
|
case ((uint32)HG_SUPTMR1_BASE):
|
|
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR1_CNT_MOD_SEL(1);
|
|
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
|
|
break;
|
|
case ((uint32)HG_SUPTMR2_BASE):
|
|
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR2_CNT_MOD_SEL(1);
|
|
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
|
|
break;
|
|
case ((uint32)HG_SUPTMR3_BASE):
|
|
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR3_CNT_MOD_SEL(1);
|
|
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
|
|
break;
|
|
case ((uint32)HG_SUPTMR4_BASE):
|
|
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR4_CNT_MOD_SEL(1);
|
|
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
|
|
break;
|
|
case ((uint32)HG_SUPTMR5_BASE):
|
|
hw_comm->SUPTMR_CON0 = (hw_comm->SUPTMR_CON0 & ~(HGTIMER_V6_HW_SUPTMRCON0_BIT)) | LL_SUPTMR_CON0_SUPTMR5_CNT_MOD_SEL(1);
|
|
hw_suptmrx->CON = LL_SUPTMRx_CON_PSC(0); /* default psc: 1 */
|
|
break;
|
|
default:
|
|
return RET_ERR;
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
return RET_ERR;
|
|
break;
|
|
}
|
|
|
|
/* clear current cnt */
|
|
hw_suptmrx->CNT = 0;
|
|
|
|
dev->opened = 1;
|
|
dev->counter_en = 1;
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v6_counter_func_close(struct timer_device *timer)
|
|
{
|
|
|
|
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
|
|
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
|
|
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
|
|
int32 index = 0;
|
|
|
|
if ((!dev->opened) || (!dev->counter_en)) {
|
|
return RET_OK;
|
|
}
|
|
|
|
/* confirm which suptmr */
|
|
index = hgtimer_v6_switch_suptmr_index(dev);
|
|
if ((-1) == index) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
irq_disable(dev->irq_num);
|
|
|
|
/* config regs */
|
|
hw_comm->SUPTMR_CON1 &= ~(1) << (0 + index);
|
|
hw_suptmrx->CON = 0;
|
|
dev->opened = 0;
|
|
dev->counter_en = 0;
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v6_counter_func_start(struct timer_device *timer, uint32 period_sysclkpd_cnt, timer_cb_hdl cb, uint32 cb_data)
|
|
{
|
|
|
|
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
|
|
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
|
|
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
|
|
int32 index = 0;
|
|
|
|
if (!dev->counter_en) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
/* confirm which suptmr */
|
|
index = hgtimer_v6_switch_suptmr_index(dev);
|
|
if ((-1) == index) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
switch (dev->type) {
|
|
|
|
/* TIMER_TYPE_ONCE */
|
|
case (HGTIMER_V6_TYPE_ONCE):
|
|
|
|
dev->counter_once_en = 1;
|
|
|
|
/* config period */
|
|
hw_suptmrx->PR = period_sysclkpd_cnt;
|
|
|
|
/* clear current cnt */
|
|
hw_suptmrx->CNT = 0;
|
|
|
|
if (cb) {
|
|
dev->_counter_irq_hdl = cb;
|
|
dev->irq_data = cb_data;
|
|
hw_suptmrx->CON |= LL_SUPTMRx_CON_OV_IE;
|
|
}
|
|
|
|
hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
|
|
break;
|
|
|
|
/* TIMER_TYPE_PERIODIC */
|
|
case (HGTIMER_V6_TYPE_PERIODIC):
|
|
|
|
/* TIMER_TYPE_COUNTER */
|
|
case (HGTIMER_V6_TYPE_COUNTER):
|
|
|
|
dev->counter_period_en = 1;
|
|
|
|
/* config period */
|
|
hw_suptmrx->PR = period_sysclkpd_cnt;
|
|
|
|
/* clear current cnt */
|
|
hw_suptmrx->CNT = 0;
|
|
|
|
if (cb) {
|
|
dev->_counter_irq_hdl = cb;
|
|
dev->irq_data = cb_data;
|
|
hw_suptmrx->CON |= LL_SUPTMRx_CON_UD_IE;
|
|
}
|
|
|
|
hw_comm->SUPTMR_CON1 |= (1) << (0 + index);
|
|
break;
|
|
default:
|
|
return RET_ERR;
|
|
break;
|
|
}
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v6_counter_func_stop(struct timer_device *timer)
|
|
{
|
|
|
|
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
|
|
struct hgtimer_v6_hw_comm *hw_comm = (struct hgtimer_v6_hw_comm *)dev->hw_comm;
|
|
int32 index = 0;
|
|
|
|
if (!dev->counter_en) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
/* confirm which suptmr */
|
|
index = hgtimer_v6_switch_suptmr_index(dev);
|
|
if ((-1) == index) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
hw_comm->SUPTMR_CON1 &= ~(1) << (0 + index);
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v6_counter_func_ioctl(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2)
|
|
{
|
|
|
|
int32 ret_val = RET_OK;
|
|
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)timer;
|
|
|
|
switch (cmd) {
|
|
case (HGPWM_V0_FUNC_CMD_MASK):
|
|
ret_val = hgtimer_v6_pwm_config(dev, param1, 0);
|
|
break;
|
|
case (TIMER_SET_CLK_PSC):
|
|
ret_val = hgtimer_v6_counter_set_psc(dev, param1);
|
|
break;
|
|
default:
|
|
ret_val = RET_ERR;
|
|
break;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**********************************************************************************/
|
|
/* COUNTER FUNCTION END */
|
|
/**********************************************************************************/
|
|
|
|
static void hgtimer_v6_irq_handler(void *data)
|
|
{
|
|
|
|
struct hgtimer_v6 *dev = (struct hgtimer_v6 *)data;
|
|
struct hgtimer_v6_hw_suptmrx *hw_suptmrx = (struct hgtimer_v6_hw_suptmrx *)dev->hw_suptmrx;
|
|
|
|
|
|
if ((hw_suptmrx->CON & LL_SUPTMRx_CON_UD_IF) &&
|
|
(hw_suptmrx->CON & LL_SUPTMRx_CON_UD_IE)) {
|
|
/* clear the pending */
|
|
hw_suptmrx->CON |= LL_SUPTMRx_CON_UD_IF_CLR;
|
|
|
|
/* pwm mode irq */
|
|
if (dev->opened && dev->pwm_en && dev->_pwm_irq_hdl) {
|
|
dev->_pwm_irq_hdl(PWM_IRQ_FLAG_PERIOD, dev->irq_data);
|
|
}
|
|
|
|
/* counter mode irq */
|
|
if (dev->opened && dev->counter_en) {
|
|
if (dev->counter_once_en) {
|
|
dev->counter_once_en = 0;
|
|
|
|
/* close timer & interrupt */
|
|
hw_suptmrx->CON &= ~ LL_SUPTMRx_CON_UD_IE;
|
|
}
|
|
if (dev->_counter_irq_hdl) {
|
|
dev->_counter_irq_hdl(dev->irq_data, TIMER_INTR_PERIOD);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
if ((hw_suptmrx->CON & LL_SUPTMRx_CON_CMPA_IF) &&
|
|
(hw_suptmrx->CON & LL_SUPTMRx_CON_CMPA_IE)) {
|
|
/* clear the pending */
|
|
hw_suptmrx->CON |= LL_SUPTMRx_CON_CMPA_IF_CLR;
|
|
|
|
/* pwm mode irq */
|
|
if (dev->opened && dev->pwm_en && dev->_pwm_irq_hdl) {
|
|
dev->_pwm_irq_hdl(PWM_IRQ_FLAG_PERIOD, dev->irq_data);
|
|
}
|
|
}
|
|
}
|
|
|
|
static const struct timer_hal_ops timer_v6_ops = {
|
|
.open = hgtimer_v6_counter_func_open,
|
|
.close = hgtimer_v6_counter_func_close,
|
|
.start = hgtimer_v6_counter_func_start,
|
|
.stop = hgtimer_v6_counter_func_stop,
|
|
.ioctl = hgtimer_v6_counter_func_ioctl,
|
|
};
|
|
|
|
int32 hgtimer_v6_attach(uint32 dev_id, struct hgtimer_v6 *timer)
|
|
{
|
|
|
|
timer->opened = 0;
|
|
timer->_counter_irq_hdl = NULL;
|
|
timer->_pwm_irq_hdl = NULL;
|
|
timer->irq_data = 0;
|
|
timer->dev.dev.ops = (const struct devobj_ops *)&timer_v6_ops;
|
|
request_irq(timer->irq_num, hgtimer_v6_irq_handler, timer);
|
|
dev_register(dev_id, (struct dev_obj *)timer);
|
|
return RET_OK;
|
|
}
|
|
|
|
|