798 lines
26 KiB
C
798 lines
26 KiB
C
/**
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* @file hgtimer_v5.c
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* @author bxd
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* @brief low power led timer
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* @version
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* TXW80X
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* @date 2023-08-02
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*
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* @copyright Copyright (c) 2023
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*
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*/
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#include "typesdef.h"
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#include "list.h"
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#include "errno.h"
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#include "dev.h"
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#include "osal/irq.h"
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#include "osal/string.h"
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#include "hal/timer_device.h"
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#include "hal/pwm.h"
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#include "dev/pwm/hgpwm_v0.h"
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#include "dev/timer/hgtimer_v5.h"
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#include "hgtimer_v5_hw.h"
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/**********************************************************************************/
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/* LOW LAYER FUNCTION */
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/**********************************************************************************/
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#define LL_LED_TIMER_CHECK_COUNT_OV_INTERRUPT_ENABLE(p_timer) (LED_TIMER0_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 8)) : \
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((LED_TIMER1_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 9)) : \
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((LED_TIMER2_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 10)) : \
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((LED_TIMER3_BASE == (uint32)p_timer) ? (SYSCTRL->SYS_CON15 & (1 << 11)) : 0)))
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static inline void hgtimer_v5_irq_config(struct hgtimer_v5 *dev, uint32 enable) {
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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uint32 pos = 0;
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uint32 addr = (uint32)(&hw->LED_TMR_CON0);
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//Confirm which led_timer will be enable interrupt
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if (LED_TIMER0_BASE == addr) {
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pos = 8;
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} else if (LED_TIMER1_BASE == addr) {
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pos = 9;
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} else if (LED_TIMER2_BASE == addr) {
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pos = 10;
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} else if (LED_TIMER3_BASE == addr){
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pos = 11;
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}
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sysctrl_unlock();
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if (enable) {
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SYSCTRL->SYS_CON15 |= (1 << pos);
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} else {
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SYSCTRL->SYS_CON15 &= ~(1 << pos);
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}
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sysctrl_lock();
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}
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/**********************************************************************************/
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/* PWM FUNCTION START */
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/**********************************************************************************/
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static int32 hgtimer_v5_pwm_switch_func_cmd(enum hgpwm_v0_func_cmd param) {
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switch (param) {
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case (HGPWM_V0_FUNC_CMD_INIT):
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return HGTIMER_V5_PWM_FUNC_CMD_INIT;
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break;
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case (HGPWM_V0_FUNC_CMD_DEINIT):
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return HGTIMER_V5_PWM_FUNC_CMD_DEINIT;
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break;
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case (HGPWM_V0_FUNC_CMD_START):
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return HGTIMER_V5_PWM_FUNC_CMD_START;
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break;
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case (HGPWM_V0_FUNC_CMD_STOP):
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return HGTIMER_V5_PWM_FUNC_CMD_STOP;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
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return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM):
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return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE):
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return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE;
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break;
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case (HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD):
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return HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD;
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break;
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case (HGPWM_V0_FUNC_CMD_RELEASE_IRQ):
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return HGTIMER_V5_PWM_FUNC_CMD_RELEASE_IRQ;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER):
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return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PRESCALER;
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break;
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case (HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
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return HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY;
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break;
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default:
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return -1;
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break;
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}
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}
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static int32 hgtimer_v5_pwm_switch_period_duty(uint32 period, uint32 duty, uint32 *p_period, uint32 *p_duty) {
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uint32 pmu_con0_tmp = 0;
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uint32 period_us_to_reg = 0;
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uint32 duty_us_to_reg = 0;
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pmu_con0_tmp = PMU->PMUCON0;
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/* make sure the period */
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switch ((pmu_con0_tmp & (0x3 << 25)) >> 25) {
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/* rc128k_pre */
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case (0):
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period_us_to_reg = ((128000*period) / 1000000);
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duty_us_to_reg = ((128000*duty ) / 1000000);
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if (period_us_to_reg && duty_us_to_reg) {
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*p_period = period_us_to_reg;
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*p_duty = duty_us_to_reg;
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return 0;
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} else {
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return -1;
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}
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break;
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/* x32m_div_clk */
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case (1):
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period_us_to_reg = ((32000000*period) / 1000000);
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duty_us_to_reg = ((32000000*duty ) / 1000000);
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if (period_us_to_reg && duty_us_to_reg) {
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*p_period = period_us_to_reg;
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*p_duty = duty_us_to_reg;
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return 1;
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} else {
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return -1;
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}
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break;
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/* rc10m_clk */
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case (2):
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period_us_to_reg = ((10000000*period) / 1000000);
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duty_us_to_reg = ((10000000*duty ) / 1000000);
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if (period_us_to_reg && duty_us_to_reg) {
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*p_period = period_us_to_reg;
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*p_duty = duty_us_to_reg;
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return 2;
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} else {
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return -1;
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}
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break;
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/* lxosc32k_clk */
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case (3):
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period_us_to_reg = ((32000*period) / 1000000);
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duty_us_to_reg = ((32000*duty ) / 1000000);
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if (period_us_to_reg && duty_us_to_reg) {
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*p_period = period_us_to_reg;
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*p_duty = duty_us_to_reg;
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return 3;
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} else {
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return -1;
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}
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break;
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default:
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return -EINVAL;
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break;
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}
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}
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static inline int32 hgtimer_v5_pwm_func_init(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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uint32 period_to_reg = 0;
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uint32 duty_to_reg = 0;
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uint32 led_timer_con0_tmp = 0;
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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if (dev->opened) {
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return -EBUSY;
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}
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if (pin_func(dev->dev.dev.dev_id , 1) != RET_OK) {
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return RET_ERR;
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}
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/* make sure the period & duty */
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hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &duty_to_reg);
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hgtimer_v5_irq_config(dev, 0);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
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/* config reg */
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(1 );
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0 );
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(duty_to_reg);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
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dev->opened = 1;
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dev->pwm_en = 1;
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_deinit(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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if ((!dev->opened) || (!dev->pwm_en)) {
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return RET_OK;
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}
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irq_disable(dev->irq_num);
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pin_func(dev->dev.dev.dev_id , 0);
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hgtimer_v5_irq_config(dev, 0);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
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dev->opened = 0;
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dev->pwm_en = 0;
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_start(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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led_timer_con0_tmp |= LL_LED_TIMER_CON0_TMR_EN(1);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_stop(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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led_timer_con0_tmp &= ~ LL_LED_TIMER_CON0_TMR_EN(1);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_ioctl_set_period_duty(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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uint32 period_to_reg = 0;
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uint32 duty_to_reg = 0;
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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if ((p_config->duty < 0) || ((p_config->duty) > (p_config->period))) {
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return RET_ERR;
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}
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/* make sure the period & duty */
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if ((-1) == hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &duty_to_reg)) {
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return -EINVAL;
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};
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(duty_to_reg);
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/* led timer must stop to config period & duty */
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hgtimer_v5_pwm_func_stop(dev, p_config);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
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hgtimer_v5_pwm_func_start(dev, p_config);
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_ioctl_set_single_incream(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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uint32 period_to_reg = 0;
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uint32 none = 50; /* just for through the "func_switch_period_duty", no use */
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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/* make sure the pwm step > 0 */
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if (!p_config->duty) {
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return -EINVAL;
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}
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/* make sure the period & duty */
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if ((-1) == hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &none)) {
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return -EINVAL;
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}
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/* config reg */
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(2);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(p_config->duty);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_ioctl_set_incream_decrease(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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uint32 period_to_reg = 0;
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uint32 none = 50; /* just for through the "func_switch_period_duty", no use */
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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/* make sure the pwm step > 0 */
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if (!p_config->duty) {
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return -EINVAL;
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}
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/* make sure the period & duty */
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if ((-1) == hgtimer_v5_pwm_switch_period_duty(p_config->period, p_config->duty, &period_to_reg, &none)) {
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return -EINVAL;
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}
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/* config reg */
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(3);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF )) | LL_LED_TIMER_CON0_TMR_PR(period_to_reg);
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led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_STEP(0xFFF)) | LL_LED_TIMER_CON0_TMR_STEP(p_config->duty);
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_cmd_ioctl_set_prescaler(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config)
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{
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struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
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uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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led_timer_con0_tmp = (led_timer_con0_tmp &~ (LL_LED_TIMER_CON0_TMR_PSR(0xF))) | (LL_LED_TIMER_CON0_TMR_PSR(p_config->param1));
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pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_cmd_ioctl_set_period_duty_immediately(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config)
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{
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_request_irq_period(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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dev->_pwm_irq_hdl = p_config->irq_hdl;
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dev->irq_data = p_config->irq_data;
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hgtimer_v5_irq_config(dev, 1);
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irq_enable(dev->irq_num);
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return RET_OK;
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}
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static inline int32 hgtimer_v5_pwm_func_release_irq(struct hgtimer_v5 *dev, struct hgpwm_v0_config *p_config) {
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if (!dev->pwm_en) {
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return RET_ERR;
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}
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irq_disable(dev->irq_num);
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dev->_pwm_irq_hdl = NULL;
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dev->irq_data = 0;
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hgtimer_v5_irq_config(dev, 0);
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return RET_OK;
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}
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static int32 hgtimer_v5_pwm_config(struct hgtimer_v5 *dev, uint32 config, uint32 param) {
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struct hgpwm_v0_config *p_config;
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int32 hgtimer_v5_pwm_func_cmd = 0;
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int32 ret_val = RET_OK;
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/* Make sure the config struct pointer */
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if (!config) {
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return -EINVAL;
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}
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p_config = (struct hgpwm_v0_config*)config;
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hgtimer_v5_pwm_func_cmd = hgtimer_v5_pwm_switch_func_cmd(p_config->func_cmd);
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if ((-1) == hgtimer_v5_pwm_func_cmd) {
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return -EINVAL;
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}
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switch (hgtimer_v5_pwm_func_cmd) {
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case (HGTIMER_V5_PWM_FUNC_CMD_INIT):
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ret_val = hgtimer_v5_pwm_func_init(dev, p_config);
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break;
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|
case (HGTIMER_V5_PWM_FUNC_CMD_DEINIT):
|
|
ret_val = hgtimer_v5_pwm_func_deinit(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_START):
|
|
ret_val = hgtimer_v5_pwm_func_start(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_STOP):
|
|
ret_val = hgtimer_v5_pwm_func_stop(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY):
|
|
ret_val = hgtimer_v5_pwm_func_ioctl_set_period_duty(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM):
|
|
ret_val = hgtimer_v5_pwm_func_ioctl_set_single_incream(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE):
|
|
ret_val = hgtimer_v5_pwm_func_ioctl_set_incream_decrease(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD):
|
|
ret_val = hgtimer_v5_pwm_func_request_irq_period(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_RELEASE_IRQ):
|
|
ret_val = hgtimer_v5_pwm_func_release_irq(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PRESCALER):
|
|
ret_val = hgtimer_v5_pwm_func_cmd_ioctl_set_prescaler(dev, p_config);
|
|
break;
|
|
case (HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY):
|
|
ret_val = hgtimer_v5_pwm_func_cmd_ioctl_set_period_duty_immediately(dev, p_config);
|
|
break;
|
|
default:
|
|
ret_val = -ENOTSUPP;
|
|
break;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
/**********************************************************************************/
|
|
/* PWM FUNCTION END */
|
|
/**********************************************************************************/
|
|
|
|
|
|
/**********************************************************************************/
|
|
/* COUNTER FUNCTION START */
|
|
/**********************************************************************************/
|
|
static int32 hgtimer_v5_counter_switch_hal_type(struct hgtimer_v5 *dev, enum timer_type param) {
|
|
|
|
switch (param) {
|
|
case (TIMER_TYPE_ONCE):
|
|
dev->type = HGTIMER_V5_TYPE_ONCE;
|
|
return 0;
|
|
break;
|
|
case (TIMER_TYPE_PERIODIC):
|
|
dev->type = HGTIMER_V5_TYPE_PERIODIC;
|
|
return 1;
|
|
break;
|
|
default:
|
|
return -1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int32 hgtimer_v5_counter_switch_tmo_us(uint32 tmo_us) {
|
|
|
|
uint32 pmu_con0_tmp = 0;
|
|
uint32 tmo_us_to_reg = 0;
|
|
|
|
pmu_con0_tmp = PMU->PMUCON0;
|
|
|
|
/* make sure the period */
|
|
switch ((pmu_con0_tmp & (0x3 << 25)) >> 25) {
|
|
/* rc128k_pre */
|
|
case (0):
|
|
tmo_us_to_reg = ((128000*tmo_us) / 1000000);
|
|
if (tmo_us_to_reg) {
|
|
return tmo_us_to_reg;
|
|
} else {
|
|
return -1;
|
|
}
|
|
break;
|
|
/* x32m_div_clk */
|
|
case (1):
|
|
tmo_us_to_reg = ((32000000*tmo_us) / 1000000);
|
|
if (tmo_us_to_reg) {
|
|
return tmo_us_to_reg;
|
|
} else {
|
|
return -1;
|
|
}
|
|
break;
|
|
/* rc10m_clk */
|
|
case (2):
|
|
tmo_us_to_reg = ((10000000*tmo_us) / 1000000);
|
|
if (tmo_us_to_reg) {
|
|
return tmo_us_to_reg;
|
|
} else {
|
|
return -1;
|
|
}
|
|
break;
|
|
/* lxosc32k_clk */
|
|
case (3):
|
|
tmo_us_to_reg = ((32000*tmo_us) / 1000000);
|
|
if (tmo_us_to_reg) {
|
|
return tmo_us_to_reg;
|
|
} else {
|
|
return -1;
|
|
}
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int32 hgtimer_v5_counter_set_psc(struct hgtimer_v5 *timer, uint32 psc)
|
|
{
|
|
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
|
|
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
|
|
uint32 led_timer_con0_tmp = 0;
|
|
|
|
if (!dev->counter_en) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
led_timer_con0_tmp = hw->LED_TMR_CON0;
|
|
|
|
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F)) | LL_LED_TIMER_CON0_TMR_PSR(psc);
|
|
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v5_counter_func_open(struct timer_device *timer, enum timer_type type, uint32 flags) {
|
|
|
|
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
|
|
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
|
|
uint32 led_timer_con0_tmp = 0;
|
|
|
|
if (dev->opened) {
|
|
return -EBUSY;
|
|
}
|
|
|
|
if ((-1) == hgtimer_v5_counter_switch_hal_type(dev, type)) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
irq_enable(dev->irq_num);
|
|
hgtimer_v5_irq_config(dev, 0);
|
|
|
|
pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
|
|
|
|
switch (dev->type) {
|
|
/* TIMER_TYPE_ONCE */
|
|
case (HGTIMER_V5_TYPE_ONCE):
|
|
|
|
/* TIMER_TYPE_PERIODIC */
|
|
case (HGTIMER_V5_TYPE_PERIODIC):
|
|
|
|
/* TIMER_TYPE_COUNTER */
|
|
case (HGTIMER_V5_TYPE_COUNTER):
|
|
//Config reg
|
|
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_MODE(0xFFF)) | LL_LED_TIMER_CON0_TMR_MODE(0);
|
|
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PSR(0x00F )) | LL_LED_TIMER_CON0_TMR_PSR(0 );
|
|
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
|
|
break;
|
|
default:
|
|
return RET_ERR;
|
|
break;
|
|
}
|
|
|
|
dev->opened = 1;
|
|
dev->counter_en = 1;
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v5_counter_func_close(struct timer_device *timer) {
|
|
|
|
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
|
|
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
|
|
|
|
if ((!dev->opened) || (!dev->counter_en)) {
|
|
return RET_OK;
|
|
}
|
|
|
|
irq_disable(dev->irq_num);
|
|
|
|
pmu_reg_write((uint32)&hw->LED_TMR_CON0, 0x00000000);
|
|
dev->opened = 0;
|
|
dev->counter_en = 0;
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v5_counter_func_start(struct timer_device *timer, uint32 period_clkpd_cnt, timer_cb_hdl cb, uint32 cb_data) {
|
|
|
|
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
|
|
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
|
|
int32 tmo_us_to_reg = 0;
|
|
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
|
|
|
|
if (!dev->counter_en) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
/* make sure the period */
|
|
// tmo_us_to_reg = hgtimer_v5_counter_switch_tmo_us(tmo_us);
|
|
// if ((-1) == tmo_us_to_reg) {
|
|
// return -EINVAL;
|
|
// }
|
|
tmo_us_to_reg = period_clkpd_cnt;
|
|
if (!tmo_us_to_reg || (tmo_us_to_reg > 0xFFF)) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
switch (dev->type) {
|
|
|
|
/* TIMER_TYPE_ONCE */
|
|
case (HGTIMER_V5_TYPE_ONCE):
|
|
|
|
dev->counter_once_en = 1;
|
|
|
|
/* config reg */
|
|
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF)) | LL_LED_TIMER_CON0_TMR_PR(tmo_us_to_reg);
|
|
led_timer_con0_tmp |= LL_LED_TIMER_CON0_TMR_EN(1);
|
|
|
|
if (cb) {
|
|
dev->_counter_irq_hdl = cb;
|
|
dev->irq_data = cb_data;
|
|
hgtimer_v5_irq_config(dev, 1);
|
|
}
|
|
|
|
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
|
|
break;
|
|
|
|
/* TIMER_TYPE_PERIODIC */
|
|
case (HGTIMER_V5_TYPE_PERIODIC):
|
|
|
|
/* TIMER_TYPE_COUNTER */
|
|
case (HGTIMER_V5_TYPE_COUNTER):
|
|
|
|
dev->counter_period_en = 1;
|
|
|
|
/* config reg */
|
|
led_timer_con0_tmp = (led_timer_con0_tmp &~ LL_LED_TIMER_CON0_TMR_PR(0xFFF)) | LL_LED_TIMER_CON0_TMR_PR(tmo_us_to_reg);
|
|
led_timer_con0_tmp |= LL_LED_TIMER_CON0_TMR_EN(1);
|
|
|
|
if (cb) {
|
|
dev->_counter_irq_hdl = cb;
|
|
dev->irq_data = cb_data;
|
|
hgtimer_v5_irq_config(dev, 1);
|
|
}
|
|
|
|
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
|
|
break;
|
|
default:
|
|
return RET_ERR;
|
|
break;
|
|
}
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v5_counter_func_stop(struct timer_device *timer) {
|
|
|
|
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
|
|
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
|
|
uint32 led_timer_con0_tmp = hw->LED_TMR_CON0;
|
|
|
|
if (!dev->counter_en) {
|
|
return RET_ERR;
|
|
}
|
|
|
|
led_timer_con0_tmp &= ~ LL_LED_TIMER_CON0_TMR_EN(1);
|
|
pmu_reg_write((uint32)&hw->LED_TMR_CON0, led_timer_con0_tmp);
|
|
|
|
return RET_OK;
|
|
}
|
|
|
|
static int32 hgtimer_v5_counter_func_ioctl(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2) {
|
|
|
|
int32 ret_val = RET_OK;
|
|
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)timer;
|
|
|
|
switch (cmd) {
|
|
case (HGPWM_V0_FUNC_CMD_MASK):
|
|
ret_val = hgtimer_v5_pwm_config(dev, param1, 0);
|
|
break;
|
|
case (TIMER_SET_CLK_PSC):
|
|
ret_val = hgtimer_v5_counter_set_psc(dev, param1);
|
|
break;
|
|
default:
|
|
ret_val = RET_ERR;
|
|
break;
|
|
}
|
|
|
|
return ret_val;
|
|
}
|
|
|
|
/**********************************************************************************/
|
|
/* COUNTER FUNCTION END */
|
|
/**********************************************************************************/
|
|
static inline void hgtimer_v5_clear_count_ov_pending(struct hgtimer_v5 *dev) {
|
|
|
|
uint32 pndclr_temp = PMU->PNDCLR;
|
|
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
|
|
uint32 addr = (uint32)(&hw->LED_TMR_CON0);
|
|
|
|
//Confirm which led timer pending will be clear
|
|
if (LED_TIMER0_BASE == addr) {
|
|
pndclr_temp |= (1 << 25);
|
|
} else if (LED_TIMER1_BASE == addr) {
|
|
pndclr_temp |= (1 << 26);
|
|
} else if (LED_TIMER2_BASE == addr) {
|
|
pndclr_temp |= (1 << 27);
|
|
} else if (LED_TIMER3_BASE == addr) {
|
|
pndclr_temp |= (1 << 28);
|
|
}
|
|
|
|
pmu_reg_write((uint32)&PMU->PNDCLR, pndclr_temp);
|
|
}
|
|
|
|
static void hgtimer_v5_irq_handler(void *data) {
|
|
|
|
struct hgtimer_v5 *dev = (struct hgtimer_v5 *)data;
|
|
struct hgtimer_v5_hw *hw = (struct hgtimer_v5_hw *)dev->hw;
|
|
|
|
if ((hw->LED_TMR_CON0 & LL_LED_TIMER_CON0_TMR_PENDING(1)) &&
|
|
LL_LED_TIMER_CHECK_COUNT_OV_INTERRUPT_ENABLE(&(hw->LED_TMR_CON0))) {
|
|
|
|
hgtimer_v5_clear_count_ov_pending(dev);
|
|
|
|
/* pwm mode irq */
|
|
if (dev->opened && dev->pwm_en && dev->_pwm_irq_hdl) {
|
|
dev->_pwm_irq_hdl(PWM_IRQ_FLAG_PERIOD, dev->irq_data);
|
|
}
|
|
|
|
/* counter mode irq */
|
|
if (dev->opened && dev->counter_en) {
|
|
if (dev->counter_once_en) {
|
|
dev->counter_once_en = 0;
|
|
|
|
/* close timer & interrupt */
|
|
hgtimer_v5_irq_config(dev, 0);
|
|
}
|
|
if (dev->_counter_irq_hdl) {
|
|
dev->_counter_irq_hdl(dev->irq_data, TIMER_INTR_PERIOD);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static const struct timer_hal_ops timer_v5_ops = {
|
|
.open = hgtimer_v5_counter_func_open,
|
|
.close = hgtimer_v5_counter_func_close,
|
|
.start = hgtimer_v5_counter_func_start,
|
|
.stop = hgtimer_v5_counter_func_stop,
|
|
.ioctl = hgtimer_v5_counter_func_ioctl,
|
|
};
|
|
|
|
int32 hgtimer_v5_attach(uint32 dev_id, struct hgtimer_v5 *timer) {
|
|
|
|
timer->opened = 0;
|
|
timer->_counter_irq_hdl = NULL;
|
|
timer->_pwm_irq_hdl = NULL;
|
|
timer->irq_data = 0;
|
|
timer->dev.dev.ops = (const struct devobj_ops *)&timer_v5_ops;
|
|
request_irq(timer->irq_num, hgtimer_v5_irq_handler, timer);
|
|
dev_register(dev_id, (struct dev_obj *)timer);
|
|
return RET_OK;
|
|
}
|
|
|