pure sdk for main
This commit is contained in:
divadiow
@@ -0,0 +1,980 @@
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#include "typesdef.h"
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#include "list.h"
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#include "errno.h"
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#include "dev.h"
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#include "hal/spi.h"
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#include "hal/spi_nor.h"
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#include "osal/sleep.h"
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/**
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* @brief Standard SPI instructions
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*/
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#define SPI_NOR_STANDARD_WRITE_ENABLE 0x06
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#define SPI_NOR_STANDARD_WRITE_DISABLE 0x04
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#define SPI_NOR_STANDARD_READ_STATUS_REG 0x05
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#define SPI_NOR_STANDARD_WRITE_STATUS_REG 0x01
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#define SPI_NOR_STANDARD_PAGE_PROGRAM 0x02
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#define SPI_NOR_STANDARD_SECTOR_ERASE 0x20
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#define SPI_NOR_STANDARD_BLOCK_ERASE 0xD8
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#define SPI_NOR_STANDARD_CHIP_ERASE 0xC7//0x60
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#define SPI_NOR_STANDARD_ERASE_SUSPEND 0x75
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#define SPI_NOR_STANDARD_ERASE_RESUME 0x7A
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#define SPI_NOR_STANDARD_READ_DATA 0x03
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#define SPI_NOR_STANDARD_FAST_READ 0x0B
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#define SPI_NOR_STANDARD_RELEASE_POWERDOWN_ID 0xAB
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#define SPI_NOR_STANDARD_DEVICE_ID 0x90
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#define SPI_NOR_STANDARD_JEDEC_ID 0x9F
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#define SPI_NOR_STANDARD_ENABLE_QPI 0x38
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#define SPI_NOR_STANDARD_POWER_DOWN 0xB9
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#define SPI_NOR_STANDARD_RELEASE_POWER_DOWN 0xAB
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#define SPI_NOR_STANDARD_ERASE_SECURITY_REG 0x44
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#define SPI_NOR_STANDARD_PROGRAM_SECURITY_REG 0x42
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#define SPI_NOR_STANDARD_READ_SECURITY_REG 0x48
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/**
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* @}
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*/
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/**
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* @brief Dual SPI instructions
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*/
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#define SPI_NOR_DUAL_FAST_READ_DUAL_OUTPUT 0x3B
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#define SPI_NOR_DUAL_FAST_READ_DUAL_IO 0xBB
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/**
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* @}
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*/
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/**
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* @brief Quad SPI instructions
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*/
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#define SPI_NOR_QUAD_PAGE_PROGRAM 0x32
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#define SPI_NOR_QUAD_FAST_READ_QUAD_OUTPUT 0x6B
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#define SPI_NOR_QUAD_FAST_READ_QUAD_IO 0xEB
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/**
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* @}
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*/
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/**
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* @brief QPI instructions
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*/
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#define SPI_NOR_QPI_WRITE_ENABLE 0x06
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#define SPI_NOR_QPI_WRITE_DISABLE 0x04
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#define SPI_NOR_QPI_READ_STATUS_REG 0x05
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#define SPI_NOR_QPI_WRITE_STATUS_REG 0x01
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#define SPI_NOR_QPI_PAGE_PROGRAM 0x02
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#define SPI_NOR_QPI_SECTOR_ERASE 0x20
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#define SPI_NOR_QPI_BLOCK_ERASE 0xD8
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#define SPI_NOR_QPI_CHIP_ERASE 0xC7
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#define SPI_NOR_QPI_ERASE_SUSPEND 0x75
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#define SPI_NOR_QPI_ERASE_RESUME 0x7A
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#define SPI_NOR_QPI_FAST_READ 0x0B
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#define SPI_NOR_QPI_FAST_READ_QUAD_IO 0xEB
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#define SPI_NOR_QPI_JEDEC_ID 0x9F
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#define SPI_NOR_QPI_DISABLE_QPI 0xFF
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/**
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* @}
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*/
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/**
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* @brief SPI NOR STATUS register
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*/
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#define SPI_NOR_STATUS_BUSY 0x01
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#define SPI_NOR_STATUS_WEL 0x02
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#define SPI_NOR_STATUS2_QUAD_ENABLE 0x200
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/**
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* @}
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*/
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/**
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* @brief Standard SPI instructions
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*/
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//JECEC ID
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void spi_nor_standard_read_jedec_id(struct spi_nor_flash *flash, uint8 *buf)
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{
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uint8 instruction = SPI_NOR_STANDARD_JEDEC_ID;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_read(flash->spidev, buf, 3);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//write disable
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static void spi_nor_standard_write_disable(struct spi_nor_flash *flash)
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{
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uint8 instruction = SPI_NOR_STANDARD_WRITE_DISABLE;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//write enable
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static void spi_nor_standard_write_enable(struct spi_nor_flash *flash)
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{
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uint8 instruction = SPI_NOR_STANDARD_WRITE_ENABLE;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//read status register
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static uint8 spi_nor_standard_read_status_register(struct spi_nor_flash *flash)
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{
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uint8 instruction = SPI_NOR_STANDARD_READ_STATUS_REG;
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uint8 result;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_read(flash->spidev, &result, 1);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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return result;
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}
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//write status register
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static void spi_nor_standard_write_status_register(struct spi_nor_flash *flash, uint16 data)
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{
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uint8 write_buf[3];
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spi_nor_standard_write_enable(flash);
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write_buf[0] = SPI_NOR_STANDARD_WRITE_STATUS_REG;
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write_buf[1] = data;
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write_buf[2] = data >> 8;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 3);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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spi_nor_standard_write_disable(flash);
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}
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//read data
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static void spi_nor_standard_read_data(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
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{
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uint8 write_buf[4];
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write_buf[0] = SPI_NOR_STANDARD_READ_DATA;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 4);
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spi_read(flash->spidev, buf, buf_size);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//fast read
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static void spi_nor_standard_fast_read(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
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{
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uint8 write_buf[5];
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write_buf[0] = SPI_NOR_STANDARD_FAST_READ;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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write_buf[4] = 0x00; //dummy clock
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 5);
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spi_read(flash->spidev, buf, buf_size);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//page program
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static void spi_nor_standard_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
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{
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uint8 write_buf[4];
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spi_nor_standard_write_enable(flash);
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write_buf[0] = SPI_NOR_STANDARD_PAGE_PROGRAM;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 4);
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spi_write(flash->spidev, buf, buf_size);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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//wait page program done
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while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
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spi_nor_standard_write_disable(flash);
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}
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//sector erase
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static void spi_nor_standard_sector_erase(struct spi_nor_flash *flash, uint32 addr)
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{
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uint8 write_buf[4];
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spi_nor_standard_write_enable(flash);
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write_buf[0] = SPI_NOR_STANDARD_SECTOR_ERASE;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 4);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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//wait sector erase done
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while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
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spi_nor_standard_write_disable(flash);
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}
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//block erase
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static void spi_nor_standard_block_erase(struct spi_nor_flash *flash, uint32 addr)
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{
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uint8 write_buf[4];
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spi_nor_standard_write_enable(flash);
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write_buf[0] = SPI_NOR_STANDARD_BLOCK_ERASE;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 4);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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//wait block erase done
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while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
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spi_nor_standard_write_disable(flash);
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}
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//chip erase
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static void spi_nor_standard_chip_erase(struct spi_nor_flash *flash)
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{
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uint8 instruction = SPI_NOR_STANDARD_CHIP_ERASE;
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spi_nor_standard_write_enable(flash);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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//wait block erase done
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while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
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spi_nor_standard_write_disable(flash);
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}
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//enter QPI
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static void spi_nor_standard_enter_qpi(struct spi_nor_flash *flash)
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{
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uint8 instruction = SPI_NOR_STANDARD_ENABLE_QPI;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//enter power down
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static void spi_nor_standard_power_down(struct spi_nor_flash *flash)
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{
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uint8 instruction = SPI_NOR_STANDARD_POWER_DOWN;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//release power down
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static void spi_nor_standard_release_power_down(struct spi_nor_flash *flash)
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{
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uint8 instruction = SPI_NOR_STANDARD_RELEASE_POWER_DOWN;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, &instruction, 1);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//erase security registers
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static void spi_nor_standard_erase_security_reg(struct spi_nor_flash *flash, uint32 addr)
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{
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uint8 write_buf[4];
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spi_nor_standard_write_enable(flash);
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write_buf[0] = SPI_NOR_STANDARD_ERASE_SECURITY_REG;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 4);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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//wait block erase done
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while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
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spi_nor_standard_write_disable(flash);
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}
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//program security registers
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static void spi_nor_standard_program_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
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{
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uint8 write_buf[4];
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spi_nor_standard_write_enable(flash);
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write_buf[0] = SPI_NOR_STANDARD_PROGRAM_SECURITY_REG;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 4);
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spi_write(flash->spidev, buf, buf_size);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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//wait block erase done
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while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
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spi_nor_standard_write_disable(flash);
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}
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//read security registers
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static void spi_nor_standard_read_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
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{
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uint8 write_buf[5];
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write_buf[0] = SPI_NOR_STANDARD_READ_SECURITY_REG;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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write_buf[4] = 0; //dummy
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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spi_write(flash->spidev, write_buf, 5);
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spi_read(flash->spidev, buf, buf_size);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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static void spi_nor_standard_open(struct spi_nor_flash *flash)
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{
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//release power down
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//spi_nor_standard_release_power_down(flash);
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//wait done
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//os_sleep_us(100);
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}
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/**
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* @}
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*/
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/**
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* @brief Dual SPI instructions
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*/
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//fast read dual output
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//If flash supports DUAL, this function is also generally supported
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static void spi_nor_dual_fast_read_dual_output(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
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{
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uint8 write_buf[5];
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write_buf[0] = SPI_NOR_DUAL_FAST_READ_DUAL_OUTPUT;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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write_buf[4] = 0x00; //dummy clock
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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//instruction & address & dummy clock should tx in Standard SPI mode
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spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
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spi_write(flash->spidev, write_buf, 5);
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//data rx in DUAL SPI mode
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spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_DUAL_MODE, 0);
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spi_read(flash->spidev, buf, buf_size);
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//Return to normal mode
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spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
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spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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}
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//fast read dual IO
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//warning! You need to confirm that nor flash supports this function.
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static void spi_nor_dual_fast_read_dual_io(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
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{
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uint8 write_buf[5];
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write_buf[0] = SPI_NOR_DUAL_FAST_READ_DUAL_IO;
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write_buf[1] = addr >> 16;
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write_buf[2] = addr >> 8;
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write_buf[3] = addr;
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write_buf[4] = 0x00;
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spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
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//instruction should tx in Standard SPI mode
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spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
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spi_write(flash->spidev, write_buf, 1);
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//address & dummy clock should tx in DUAL SPI mode
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spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_DUAL_MODE, 0);
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spi_write(flash->spidev, &write_buf[1], 4);
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||||
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||||
//data rx in DUAL SPI mode
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||||
spi_read(flash->spidev, buf, buf_size);
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||||
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||||
//Return to normal mode
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||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
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||||
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||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
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||||
}
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||||
|
||||
static void spi_nor_quad_open(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint16 status;
|
||||
|
||||
//release power down
|
||||
spi_nor_standard_release_power_down(flash);
|
||||
//wait done
|
||||
os_sleep_us(50);
|
||||
|
||||
status = spi_nor_standard_read_status_register(flash);
|
||||
status |= SPI_NOR_STATUS2_QUAD_ENABLE;
|
||||
spi_nor_standard_write_status_register(flash, status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Quad SPI instructions
|
||||
* @note warning! You need to confirm that nor flash supports this function.
|
||||
*/
|
||||
//fast read quad output
|
||||
static void spi_nor_quad_fast_read_quad_output(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
uint8 write_buf[5];
|
||||
|
||||
write_buf[0] = SPI_NOR_QUAD_FAST_READ_QUAD_OUTPUT;
|
||||
write_buf[1] = addr >> 16;
|
||||
write_buf[2] = addr >> 8;
|
||||
write_buf[3] = addr;
|
||||
write_buf[4] = 0x00; //dummy clock
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
|
||||
//instruction & address & dummy clock should tx in Standard SPI mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
spi_write(flash->spidev, write_buf, 5);
|
||||
|
||||
//data rx in QUAD SPI mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
spi_read(flash->spidev, buf, buf_size);
|
||||
|
||||
//Return to normal mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
}
|
||||
|
||||
//fast read quad IO
|
||||
static void spi_nor_quad_fast_read_quad_io(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
uint8 write_buf[7];
|
||||
|
||||
write_buf[0] = SPI_NOR_QUAD_FAST_READ_QUAD_IO;
|
||||
write_buf[1] = addr >> 16;
|
||||
write_buf[2] = addr >> 8;
|
||||
write_buf[3] = addr;
|
||||
write_buf[4] = 0x00;
|
||||
write_buf[5] = 0x00; //dummy clock
|
||||
write_buf[6] = 0x00; //dummy clock
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
|
||||
//instruction should tx in Standard SPI mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
spi_write(flash->spidev, write_buf, 1);
|
||||
|
||||
//address & dummy clock should tx in QUAD SPI mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
spi_write(flash->spidev, &write_buf[1], 6);
|
||||
|
||||
//data rx in DUAL SPI mode
|
||||
spi_read(flash->spidev, buf, buf_size);
|
||||
|
||||
//Return to normal mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
}
|
||||
|
||||
//quad input page program
|
||||
static void spi_nor_quad_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
uint8 write_buf[4];
|
||||
|
||||
write_buf[0] = SPI_NOR_QUAD_PAGE_PROGRAM;
|
||||
write_buf[1] = addr >> 16;
|
||||
write_buf[2] = addr >> 8;
|
||||
write_buf[3] = addr;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
spi_nor_standard_write_enable(flash);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, write_buf, 4);
|
||||
//data tx in QUAD SPI mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
spi_write(flash->spidev, buf, buf_size);
|
||||
//Return to normal mode
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
//wait tx done
|
||||
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
|
||||
spi_nor_standard_write_disable(flash);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief QPI instructions
|
||||
* @note warning! You need to confirm that nor flash supports this function.
|
||||
*/
|
||||
//JECEC ID
|
||||
static void spi_nor_qpi_read_jedec_id(struct spi_nor_flash *flash, uint8 *buf)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_QPI_JEDEC_ID;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_read(flash->spidev, buf, 3);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
}
|
||||
|
||||
//write disable
|
||||
static void spi_nor_qpi_write_disable(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_QPI_WRITE_DISABLE;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
}
|
||||
|
||||
//write enable
|
||||
static void spi_nor_qpi_write_enable(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_QPI_WRITE_ENABLE;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
}
|
||||
|
||||
//read status register
|
||||
static uint8 spi_nor_qpi_read_status_register(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_QPI_READ_STATUS_REG;
|
||||
uint8 result;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_read(flash->spidev, &result, 1);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
//write status register
|
||||
static void spi_nor_qpi_write_status_register(struct spi_nor_flash *flash, uint16 data)
|
||||
{
|
||||
uint8 write_buf[3];
|
||||
|
||||
spi_nor_qpi_write_enable(flash);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
write_buf[0] = SPI_NOR_QPI_WRITE_STATUS_REG;
|
||||
write_buf[1] = data;
|
||||
write_buf[2] = data >> 8;
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, write_buf, 3);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
spi_nor_qpi_write_disable(flash);
|
||||
}
|
||||
|
||||
//fast read quad io
|
||||
static void spi_nor_qpi_fast_read_quad_io(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
uint8 write_buf[5];
|
||||
|
||||
write_buf[0] = SPI_NOR_QPI_FAST_READ_QUAD_IO;
|
||||
write_buf[1] = addr >> 16;
|
||||
write_buf[2] = addr >> 8;
|
||||
write_buf[3] = addr;
|
||||
write_buf[4] = 0x00;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, write_buf, 5);
|
||||
spi_read(flash->spidev, buf, buf_size);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
}
|
||||
|
||||
//page program
|
||||
static void spi_nor_qpi_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
uint8 write_buf[4];
|
||||
|
||||
spi_nor_qpi_write_enable(flash);
|
||||
|
||||
write_buf[0] = SPI_NOR_QPI_PAGE_PROGRAM;
|
||||
write_buf[1] = addr >> 16;
|
||||
write_buf[2] = addr >> 8;
|
||||
write_buf[3] = addr;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, write_buf, 4);
|
||||
spi_write(flash->spidev, buf, buf_size);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
//wait page program done
|
||||
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
|
||||
|
||||
spi_nor_qpi_write_disable(flash);
|
||||
}
|
||||
|
||||
//sector erase
|
||||
static void spi_nor_qpi_sector_erase(struct spi_nor_flash *flash, uint32 addr)
|
||||
{
|
||||
uint8 write_buf[4];
|
||||
|
||||
spi_nor_qpi_write_enable(flash);
|
||||
|
||||
write_buf[0] = SPI_NOR_QPI_SECTOR_ERASE;
|
||||
write_buf[1] = addr >> 16;
|
||||
write_buf[2] = addr >> 8;
|
||||
write_buf[3] = addr;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, write_buf, 4);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
//wait sector erase done
|
||||
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
|
||||
|
||||
spi_nor_qpi_write_disable(flash);
|
||||
}
|
||||
|
||||
//block erase
|
||||
static void spi_nor_qpi_block_erase(struct spi_nor_flash *flash, uint32 addr)
|
||||
{
|
||||
uint8 write_buf[4];
|
||||
|
||||
spi_nor_qpi_write_enable(flash);
|
||||
|
||||
write_buf[0] = SPI_NOR_QPI_BLOCK_ERASE;
|
||||
write_buf[1] = addr >> 16;
|
||||
write_buf[2] = addr >> 8;
|
||||
write_buf[3] = addr;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, write_buf, 4);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
//wait block erase done
|
||||
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
|
||||
|
||||
spi_nor_qpi_write_disable(flash);
|
||||
}
|
||||
|
||||
//chip erase
|
||||
static void spi_nor_qpi_chip_erase(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_QPI_CHIP_ERASE;
|
||||
|
||||
spi_nor_qpi_write_enable(flash);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
|
||||
//wait block erase done
|
||||
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
|
||||
|
||||
spi_nor_qpi_write_disable(flash);
|
||||
}
|
||||
|
||||
//disable QPI
|
||||
static void spi_nor_standard_disable_qpi(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_QPI_DISABLE_QPI;
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
|
||||
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
|
||||
}
|
||||
|
||||
//enter power down
|
||||
static void spi_nor_qpi_power_down(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_STANDARD_POWER_DOWN;
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
}
|
||||
|
||||
//release power down
|
||||
static void spi_nor_qpi_release_power_down(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint8 instruction = SPI_NOR_STANDARD_RELEASE_POWER_DOWN;
|
||||
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
|
||||
spi_write(flash->spidev, &instruction, 1);
|
||||
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
|
||||
}
|
||||
|
||||
static void spi_nor_qpi_open(struct spi_nor_flash *flash)
|
||||
{
|
||||
uint16 status;
|
||||
|
||||
//release power down
|
||||
spi_nor_qpi_release_power_down(flash);
|
||||
//wait done
|
||||
os_sleep_us(50);
|
||||
|
||||
status = spi_nor_standard_read_status_register(flash);
|
||||
status |= SPI_NOR_STATUS2_QUAD_ENABLE;
|
||||
spi_nor_standard_write_status_register(flash, status);
|
||||
spi_nor_standard_enter_qpi(flash);
|
||||
}
|
||||
|
||||
static void spi_nor_qpi_close(struct spi_nor_flash *flash)
|
||||
{
|
||||
spi_nor_standard_disable_qpi(flash);
|
||||
}
|
||||
|
||||
static void spi_nor_xip_open(struct spi_nor_flash *flash)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static void spi_nor_xip_close(struct spi_nor_flash *flash)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static void spi_nor_xip_read_data(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_READ);
|
||||
spi_read(flash->spidev, buf, buf_size);
|
||||
}
|
||||
|
||||
static void spi_nor_xip_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_WRITE);
|
||||
spi_write(flash->spidev, buf, buf_size);
|
||||
}
|
||||
|
||||
static void spi_nor_xip_sector_erase(struct spi_nor_flash *flash, uint32 addr)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_ERASE_4KB,addr, XIP_ERASE);
|
||||
}
|
||||
|
||||
static void spi_nor_xip_block_erase(struct spi_nor_flash *flash, uint32 addr)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_ERASE_64KB,addr, 0);
|
||||
}
|
||||
|
||||
//erase security registers
|
||||
static void spi_nor_xip_erase_security_reg(struct spi_nor_flash *flash, uint32 addr)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_ERASE_SECURITY_REG,addr, 0);
|
||||
}
|
||||
|
||||
//program security registers
|
||||
static void spi_nor_xip_program_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_SECURITY_WRITE);
|
||||
spi_ioctl(flash->spidev,SPI_XIP_PROGRAM_SECURITY_REG, (uint32)buf, buf_size);
|
||||
}
|
||||
|
||||
//read security registers
|
||||
static void spi_nor_xip_read_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_SECURITY_READ);
|
||||
spi_ioctl(flash->spidev,SPI_XIP_READ_SECURITY_REG, (uint32)buf, buf_size);
|
||||
}
|
||||
|
||||
|
||||
static void spi_nor_xip_custom_read_data(struct spi_nor_flash *flash, uint32_t param)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_CUSTOM_READ_CMD,param,0);
|
||||
}
|
||||
|
||||
static void spi_nor_xip_custom_write_data(struct spi_nor_flash *flash, uint32_t param)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_CUSTOM_WRITE_CMD,param,0);
|
||||
}
|
||||
|
||||
static void spi_nor_xip_custom_erase(struct spi_nor_flash *flash, uint32_t param)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_CUSTOM_ERASE_CMD,param,0);
|
||||
}
|
||||
|
||||
static void spi_nor_xip_reg_opt(struct spi_nor_flash *flash, uint32_t param)
|
||||
{
|
||||
spi_ioctl(flash->spidev,SPI_XIP_REG_OPT, param, 0);
|
||||
}
|
||||
|
||||
static int32 spi_nor_xip_ioctl(struct spi_nor_flash *flash, uint32_t cmd,uint32_t param1,uint32_t param2)
|
||||
{
|
||||
return spi_ioctl(flash->spidev,cmd,param1,param2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
//SPI NOR function
|
||||
static const struct spi_nor_bus spinor_bus_list[] = {
|
||||
//NORMAL SPI
|
||||
{
|
||||
spi_nor_standard_open,
|
||||
NULL,
|
||||
spi_nor_standard_read_data,
|
||||
spi_nor_standard_page_program,
|
||||
spi_nor_standard_sector_erase,
|
||||
spi_nor_standard_block_erase,
|
||||
spi_nor_standard_chip_erase,
|
||||
spi_nor_standard_power_down,
|
||||
spi_nor_standard_release_power_down,
|
||||
spi_nor_standard_erase_security_reg,
|
||||
spi_nor_standard_program_security_reg,
|
||||
spi_nor_standard_read_security_reg,
|
||||
},
|
||||
//DUAL SPI
|
||||
{
|
||||
spi_nor_standard_open,
|
||||
NULL,
|
||||
spi_nor_dual_fast_read_dual_output,
|
||||
spi_nor_standard_page_program,
|
||||
spi_nor_standard_sector_erase,
|
||||
spi_nor_standard_block_erase,
|
||||
spi_nor_standard_chip_erase,
|
||||
spi_nor_standard_power_down,
|
||||
spi_nor_standard_release_power_down,
|
||||
spi_nor_standard_erase_security_reg,
|
||||
spi_nor_standard_program_security_reg,
|
||||
spi_nor_standard_read_security_reg,
|
||||
},
|
||||
//QUAD SPI
|
||||
{
|
||||
spi_nor_quad_open,
|
||||
NULL,
|
||||
spi_nor_quad_fast_read_quad_output,
|
||||
spi_nor_quad_page_program,
|
||||
spi_nor_standard_sector_erase,
|
||||
spi_nor_standard_block_erase,
|
||||
spi_nor_standard_chip_erase,
|
||||
spi_nor_standard_power_down,
|
||||
spi_nor_standard_release_power_down,
|
||||
spi_nor_standard_erase_security_reg,
|
||||
spi_nor_standard_program_security_reg,
|
||||
spi_nor_standard_read_security_reg,
|
||||
},
|
||||
//QPI
|
||||
{
|
||||
spi_nor_qpi_open,
|
||||
spi_nor_qpi_close,
|
||||
spi_nor_qpi_fast_read_quad_io,
|
||||
spi_nor_qpi_page_program,
|
||||
spi_nor_qpi_sector_erase,
|
||||
spi_nor_qpi_block_erase,
|
||||
spi_nor_qpi_chip_erase,
|
||||
spi_nor_qpi_power_down,
|
||||
spi_nor_qpi_release_power_down,
|
||||
spi_nor_standard_erase_security_reg,
|
||||
spi_nor_standard_program_security_reg,
|
||||
spi_nor_standard_read_security_reg,
|
||||
},
|
||||
//XIP
|
||||
{
|
||||
spi_nor_xip_open,
|
||||
spi_nor_xip_close,
|
||||
spi_nor_xip_read_data,
|
||||
spi_nor_xip_page_program,
|
||||
spi_nor_xip_sector_erase,
|
||||
spi_nor_xip_block_erase,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
spi_nor_xip_erase_security_reg,
|
||||
spi_nor_xip_program_security_reg,
|
||||
spi_nor_xip_read_security_reg,
|
||||
spi_nor_xip_custom_read_data,
|
||||
spi_nor_xip_custom_write_data,
|
||||
spi_nor_xip_custom_erase,
|
||||
spi_nor_xip_ioctl,
|
||||
},
|
||||
};
|
||||
|
||||
const struct spi_nor_bus * spi_nor_bus_get(enum spi_nor_mode mode)
|
||||
{
|
||||
ASSERT(mode < ARRAY_SIZE(spinor_bus_list));
|
||||
return &spinor_bus_list[mode];
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user