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pure sdk for main

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divadiow
2025-08-27 09:51:58 +01:00
parent f0d033f1c9
commit 0571416e7c
3283 changed files with 1577720 additions and 1 deletions
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sdk/lib/bus/spi/lcd/gc9503v.c
+447
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@@ -0,0 +1,447 @@
#include "lib/lcd/lcd.h"
#if LCD_GC9503V_EN
#define CMD(x) {LCD_CMD,x}
#define DAT(x) {LCD_DAT,x}
#define DLY(x) {DELAY_MS,x}
#define END {LCD_TAB_END,LCD_TAB_END}
const uint8_t gc9503v_register_init_tab[][2] = {
#if 1
CMD(0x11),
DLY(250),
CMD(0xF0),DAT(0x55),DAT(0xaa),DAT(0x52),DAT(0x08),DAT(0x00),
DLY(10),CMD(0xF6),DAT(0x5a),DAT(0x87),
DLY(10),CMD(0xF0),DAT(0x55),DAT(0xaa),DAT(0x52),DAT(0x08),DAT(0x00),
DLY(10),CMD(0xF6),DAT(0x5a),DAT(0x87),
DLY(10),CMD(0xF6),DAT(0x5a),DAT(0x87),
CMD(0xC1),DAT(0x3F),
CMD(0xC2),DAT(0x0E),
CMD(0xC6),DAT(0xF8),
CMD(0xc9),DAT(0x10),
CMD(0xcD),DAT(0x25),
CMD(0x87),DAT(0x04),DAT(0x03),DAT(0x66),
CMD(0x86),DAT(0x99),DAT(0xa3),DAT(0xa3),DAT(0x31),
CMD(0xf8),DAT(0x8a),
CMD(0xac),DAT(0x45),
CMD(0xA7),DAT(0x47),
CMD(0xA0),DAT(0xcc),
CMD(0xa3),DAT(0x22),
CMD(0xFd),DAT(0x28),DAT(0x3c),DAT(0x00),
CMD(0x71),DAT(0x48),
CMD(0x72),DAT(0x48),
CMD(0x73),DAT(0x00),DAT(0x44),
CMD(0x97),DAT(0xdd),
CMD(0x83),DAT(0x93),
CMD(0x9A),DAT(0x80),
CMD(0x9B),DAT(0x58),
CMD(0x82),DAT(0x36),DAT(0x36),
CMD(0xFA),DAT(0x08),DAT(0x08),DAT(0x08),DAT(0x04),
CMD(0xB0),DAT(0x80),DAT(0x0E),DAT(0x0E),DAT(0x14),DAT(0x04),
CMD(0xB1),DAT(0x04),
CMD(0x7A),DAT(0x13),DAT(0x1A),
CMD(0x7B),DAT(0x13),DAT(0x1A),
#if 1
CMD(0x6D),DAT(0x1E),DAT(0x1E),DAT(0x1E),DAT(0x1D),DAT(0x00),DAT(0x07),DAT(0x01),DAT(0x1E),DAT(0x04),DAT(0x1F),DAT(0x0D),DAT(0x0F),DAT(0x09),DAT(0x0B),DAT(0x1E),DAT(0x1E),DAT(0x1E),DAT(0x1E),DAT(0x0C),DAT(0x0A),DAT(0x10),DAT(0x0E),DAT(0x1F),DAT(0x04),DAT(0x1E),DAT(0x02),DAT(0x08),DAT(0x00),DAT(0x1D),DAT(0x1E),DAT(0x1E),DAT(0x1E),
CMD(0x60),DAT(0x38),DAT(0x0c),DAT(0x2d),DAT(0x6d),DAT(0x38),DAT(0x0b),DAT(0x2d),DAT(0x6d),
CMD(0x61),DAT(0x18),DAT(0x02),DAT(0x2d),DAT(0x6d),DAT(0x78),DAT(0x18),DAT(0x2d),DAT(0x6d),
CMD(0x62),DAT(0x78),DAT(0x18),DAT(0x2d),DAT(0x6d),DAT(0x18),DAT(0x02),DAT(0x2d),DAT(0x6d),
CMD(0x63),DAT(0x38),DAT(0x0a),DAT(0x2d),DAT(0x6d),DAT(0x38),DAT(0x09),DAT(0x2d),DAT(0x6d),
CMD(0x64),DAT(0x38),DAT(0x08),DAT(0x02),DAT(0x80),DAT(0x03),DAT(0x03),DAT(0x38),DAT(0x07),DAT(0x02),DAT(0x81),DAT(0x03),DAT(0x03),DAT(0x2d),DAT(0x6d),DAT(0x2d),DAT(0x6d),
CMD(0x65),DAT(0x38),DAT(0x06),DAT(0x02),DAT(0x82),DAT(0x03),DAT(0x03),DAT(0x38),DAT(0x05),DAT(0x02),DAT(0x83),DAT(0x03),DAT(0x03),DAT(0x2d),DAT(0x6d),DAT(0x2d),DAT(0x6d),
CMD(0x66),DAT(0x38),DAT(0x04),DAT(0x02),DAT(0x84),DAT(0x03),DAT(0x03),DAT(0x38),DAT(0x03),DAT(0x02),DAT(0x85),DAT(0x03),DAT(0x03),DAT(0x2d),DAT(0x6d),DAT(0x2d),DAT(0x6d),
CMD(0x67),DAT(0x38),DAT(0x02),DAT(0x02),DAT(0x86),DAT(0x03),DAT(0x03),DAT(0x38),DAT(0x01),DAT(0x02),DAT(0x87),DAT(0x03),DAT(0x03),DAT(0x2d),DAT(0x6d),DAT(0x2d),DAT(0x6d),
#endif
CMD(0x69),DAT(0x14),DAT(0x22),DAT(0x14),DAT(0x22),DAT(0x14),DAT(0x22),DAT(0x08),
CMD(0x6b),DAT(0x07),
#if 1
CMD(0xD1),DAT(0x00),DAT(0x00),DAT(0x00),DAT(0x1D),DAT(0x00),DAT(0x4D),DAT(0x00),DAT(0x70),DAT(0x00),DAT(0x90),DAT(0x00),DAT(0xC3),DAT(0x00),DAT(0xE8),DAT(0x01),DAT(0x1B),DAT(0x01),DAT(0x4C),DAT(0x01),DAT(0xA2),DAT(0x01),DAT(0xE0),DAT(0x02),DAT(0x43),DAT(0x02),DAT(0x8E),DAT(0x02),DAT(0x90),DAT(0x02),DAT(0xD3),DAT(0x03),DAT(0x18),DAT(0x03),DAT(0x43),DAT(0x03),DAT(0x81),DAT(0x03),DAT(0xA4),DAT(0x03),DAT(0xBA),DAT(0x03),DAT(0xC9),DAT(0x03),DAT(0xDC),DAT(0x03),DAT(0xE7),DAT(0x03),DAT(0xF4),DAT(0x03),DAT(0xFC),DAT(0x03),DAT(0xFF),
CMD(0xD2),DAT(0x00),DAT(0x00),DAT(0x00),DAT(0x1D),DAT(0x00),DAT(0x4D),DAT(0x00),DAT(0x70),DAT(0x00),DAT(0x90),DAT(0x00),DAT(0xC3),DAT(0x00),DAT(0xE8),DAT(0x01),DAT(0x1B),DAT(0x01),DAT(0x4C),DAT(0x01),DAT(0xA2),DAT(0x01),DAT(0xE0),DAT(0x02),DAT(0x43),DAT(0x02),DAT(0x8E),DAT(0x02),DAT(0x90),DAT(0x02),DAT(0xD3),DAT(0x03),DAT(0x18),DAT(0x03),DAT(0x43),DAT(0x03),DAT(0x81),DAT(0x03),DAT(0xA4),DAT(0x03),DAT(0xBA),DAT(0x03),DAT(0xC9),DAT(0x03),DAT(0xDC),DAT(0x03),DAT(0xE7),DAT(0x03),DAT(0xF4),DAT(0x03),DAT(0xFC),DAT(0x03),DAT(0xFF),
CMD(0xD3),DAT(0x00),DAT(0x00),DAT(0x00),DAT(0x1D),DAT(0x00),DAT(0x4D),DAT(0x00),DAT(0x70),DAT(0x00),DAT(0x90),DAT(0x00),DAT(0xC3),DAT(0x00),DAT(0xE8),DAT(0x01),DAT(0x1B),DAT(0x01),DAT(0x4C),DAT(0x01),DAT(0xA2),DAT(0x01),DAT(0xE0),DAT(0x02),DAT(0x43),DAT(0x02),DAT(0x8E),DAT(0x02),DAT(0x90),DAT(0x02),DAT(0xD3),DAT(0x03),DAT(0x18),DAT(0x03),DAT(0x43),DAT(0x03),DAT(0x81),DAT(0x03),DAT(0xA4),DAT(0x03),DAT(0xBA),DAT(0x03),DAT(0xC9),DAT(0x03),DAT(0xDC),DAT(0x03),DAT(0xE7),DAT(0x03),DAT(0xF4),DAT(0x03),DAT(0xFC),DAT(0x03),DAT(0xFF),
CMD(0xD4),DAT(0x00),DAT(0x00),DAT(0x00),DAT(0x1D),DAT(0x00),DAT(0x4D),DAT(0x00),DAT(0x70),DAT(0x00),DAT(0x90),DAT(0x00),DAT(0xC3),DAT(0x00),DAT(0xE8),DAT(0x01),DAT(0x1B),DAT(0x01),DAT(0x4C),DAT(0x01),DAT(0xA2),DAT(0x01),DAT(0xE0),DAT(0x02),DAT(0x43),DAT(0x02),DAT(0x8E),DAT(0x02),DAT(0x90),DAT(0x02),DAT(0xD3),DAT(0x03),DAT(0x18),DAT(0x03),DAT(0x43),DAT(0x03),DAT(0x81),DAT(0x03),DAT(0xA4),DAT(0x03),DAT(0xBA),DAT(0x03),DAT(0xC9),DAT(0x03),DAT(0xDC),DAT(0x03),DAT(0xE7),DAT(0x03),DAT(0xF4),DAT(0x03),DAT(0xFC),DAT(0x03),DAT(0xFF),
CMD(0xD5),DAT(0x00),DAT(0x00),DAT(0x00),DAT(0x1D),DAT(0x00),DAT(0x4D),DAT(0x00),DAT(0x70),DAT(0x00),DAT(0x90),DAT(0x00),DAT(0xC3),DAT(0x00),DAT(0xE8),DAT(0x01),DAT(0x1B),DAT(0x01),DAT(0x4C),DAT(0x01),DAT(0xA2),DAT(0x01),DAT(0xE0),DAT(0x02),DAT(0x43),DAT(0x02),DAT(0x8E),DAT(0x02),DAT(0x90),DAT(0x02),DAT(0xD3),DAT(0x03),DAT(0x18),DAT(0x03),DAT(0x43),DAT(0x03),DAT(0x81),DAT(0x03),DAT(0xA4),DAT(0x03),DAT(0xBA),DAT(0x03),DAT(0xC9),DAT(0x03),DAT(0xDC),DAT(0x03),DAT(0xE7),DAT(0x03),DAT(0xF4),DAT(0x03),DAT(0xFC),DAT(0x03),DAT(0xFF),
CMD(0xD6),DAT(0x00),DAT(0x00),DAT(0x00),DAT(0x1D),DAT(0x00),DAT(0x4D),DAT(0x00),DAT(0x70),DAT(0x00),DAT(0x90),DAT(0x00),DAT(0xC3),DAT(0x00),DAT(0xE8),DAT(0x01),DAT(0x1B),DAT(0x01),DAT(0x4C),DAT(0x01),DAT(0xA2),DAT(0x01),DAT(0xE0),DAT(0x02),DAT(0x43),DAT(0x02),DAT(0x8E),DAT(0x02),DAT(0x90),DAT(0x02),DAT(0xD3),DAT(0x03),DAT(0x18),DAT(0x03),DAT(0x43),DAT(0x03),DAT(0x81),DAT(0x03),DAT(0xA4),DAT(0x03),DAT(0xBA),DAT(0x03),DAT(0xC9),DAT(0x03),DAT(0xDC),DAT(0x03),DAT(0xE7),DAT(0x03),DAT(0xF4),DAT(0x03),DAT(0xFC),DAT(0x03),DAT(0xFF),
#endif
CMD(0x3A),DAT(0x66),
DLY(200), CMD(0x11),DAT(0x00),
DLY(200), CMD(0x29),DAT(0x00),
END
#else
CMD(0x11),
DLY(250),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x13),
CMD(0xEF),
DAT(0x08),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x10),
CMD(0xC0),
DAT(0xE9),
DAT(0x03),
CMD(0xC1),
DAT(0x11),
DAT(0x02),
CMD(0xC2),
DAT(0x07),
DAT(0x06),
CMD(0xC3),
DAT(0x00),
CMD(0xCC),
DAT(0x18),
CMD(0xB0),
DAT(0x00),
DAT(0x0D),
DAT(0x14),
DAT(0x0D),
DAT(0x10),
DAT(0x05),
DAT(0x02),
DAT(0x08),
DAT(0x08),
DAT(0x1E),
DAT(0x05),
DAT(0x13),
DAT(0x11),
DAT(0xA3),
DAT(0x29),
DAT(0x18),
CMD(0xB1),
DAT(0x00),
DAT(0x0C),
DAT(0x14),
DAT(0x0C),
DAT(0x10),
DAT(0x05),
DAT(0x03),
DAT(0x08),
DAT(0x07),
DAT(0x20),
DAT(0x05),
DAT(0x13),
DAT(0x11),
DAT(0xA4),
DAT(0x29),
DAT(0x18),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x11),
CMD(0xB0),
DAT(0x6C),
CMD(0xB1),
DAT(0x8D),
CMD(0xB2),
DAT(0x89),
CMD(0xB3),
DAT(0x80),
CMD(0xB5),
DAT(0x4E),
CMD(0xB7),
DAT(0x85),
CMD(0xB8),
DAT(0x20),
CMD(0xB9),
DAT(0x00),
DAT(0x13),
CMD(0xC0),
DAT(0x09),
CMD(0xC1),
DAT(0x78),
CMD(0xC2),
DAT(0x78),
CMD(0xD0),
DAT(0x88),
CMD(0xE0),
DAT(0x00),
DAT(0x00),
DAT(0x02),
CMD(0xE1),
DAT(0x08),
DAT(0x00),
DAT(0x0A),
DAT(0x00),
DAT(0x07),
DAT(0x00),
DAT(0x09),
DAT(0x00),
DAT(0x00),
DAT(0x33),
DAT(0x33),
CMD(0xE2),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
CMD(0xE3),
DAT(0x00),
DAT(0x00),
DAT(0x33),
DAT(0x33),
CMD(0xE4),
DAT(0x44),
DAT(0x44),
CMD(0xE5),
DAT(0x0E),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x10),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0A),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0C),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
CMD(0xE6),
DAT(0x00),
DAT(0x00),
DAT(0x33),
DAT(0x33),
CMD(0xE7),
DAT(0x44),
DAT(0x44),
CMD(0xE8),
DAT(0x0D),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0F),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x09),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0B),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
CMD(0xEB),
DAT(0x02),
DAT(0x01),
DAT(0xE4),
DAT(0xE4),
DAT(0x44),
DAT(0x00),
DAT(0x40),
CMD(0xEC),
DAT(0x02),
DAT(0x01),
CMD(0xED),
DAT(0xAB),
DAT(0x89),
DAT(0x76),
DAT(0x54),
DAT(0x01),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0x10),
DAT(0x45),
DAT(0x67),
DAT(0x98),
DAT(0xBA),
CMD(0xEF),
DAT(0x08),
DAT(0x08),
DAT(0x08),
DAT(0x45),
DAT(0x3F),
DAT(0x54),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x13),
CMD(0xE8),
DAT(0x00),
DAT(0x0E),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x00),
CMD(0x11),
DAT(0x00),
DLY (120),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x13),
CMD(0xE8),
DAT(0x00),
DAT(0x0C),
DLY (10),
CMD(0xE8),
DAT(0x00),
DAT(0x00),
CMD(0xE6),
DAT(0x16),
DAT(0x7C),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x00),
/*
CMD(0xFF),//bist mode
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x12),
CMD(0xD1),
DAT(0x81),
CMD(0xD2),
DAT(0x06),//bist mode 0x00列灰阶分两半 02红03绿04蓝05白边框06棋盘格07黑底白像素网格08RGB彩条
*/
CMD(0x3A),
DAT(0x55),
CMD(0x29),
DAT(0x00),
DLY (20),
END
#endif
};
lcddev_t lcdstruct = {
.name = "gc9503v",
.lcd_bus_type = LCD_BUS_RGB,
.bus_width = LCD_BUS_WIDTH_18,
.color_mode = LCD_MODE_666,
.osd_scan_mode = LCD_ROTATE_90,
.scan_mode = LCD_ROTATE_90,//rotate 90 LCD_ROTATE_0
.te_mode = 0xff,//te mode, 0xff:disable
.colrarray = 0,//0:_RGB_ 1:_RBG_,2:_GBR_,3:_GRB_,4:_BRG_,5:_BGR_
.pclk = 20000000,
.even_order = 0,
.odd_order = 0,
.screen_w = 360,
.screen_h = 640,
.video_x = 0,
.video_y = 0,
.video_w = 360,
.video_h = 640,
.osd_x = 0,
.osd_y = 0,
.osd_w = 360, // 0 : value will set to video_w , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.osd_h = 640,// 0 : value will set to video_h , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.init_table = gc9503v_register_init_tab,
.pclk_inv = 1,
.vlw = 1,
.vbp = 14,
.vfp = 14,
.hlw = 1,
.hbp = 20,
.hfp = 4,
.de_inv = 0,
.hs_inv = 1,
.vs_inv = 1,
.de_en = 1,
.vs_en = 1,
.hs_en = 1,
};
#endif
sdk/lib/bus/spi/lcd/hx8282.c
+67
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@@ -0,0 +1,67 @@
#include "lib/lcd/lcd.h"
#if LCD_HX8282_EN
#define CMD(x) {LCD_CMD,x}
#define DAT(x) {LCD_DAT,x}
#define DLY(x) {DELAY_MS,x}
#define END {LCD_TAB_END,LCD_TAB_END}
const uint8_t hx8282_register_init_tab[][2] = {
END
};
lcddev_t lcdstruct = {
.name = "st7701s",
.lcd_bus_type = LCD_BUS_RGB,
.bus_width = LCD_BUS_WIDTH_18,
.color_mode = LCD_MODE_666,
.osd_scan_mode = LCD_ROTATE_0,
.scan_mode = LCD_ROTATE_0,//rotate 90
.te_mode = 0xff,//te mode, 0xff:disable
.colrarray = 0,//0:_RGB_ 1:_RBG_,2:_GBR_,3:_GRB_,4:_BRG_,5:_BGR_
.pclk = 48000000,
.even_order = 0,
.odd_order = 0,
.screen_w = 1024,
.screen_h = 600,
.video_x = 0,
.video_y = 0,
.video_w = 1024,
.video_h = 600,
.osd_x = 0,
.osd_y = 0,
.osd_w = 1024, // 0 : value will set to video_w , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.osd_h = 600, // 0 : value will set to video_h , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.init_table = NULL,
.pclk_inv = 1,
.vlw = 30,
.vbp = 22,
.vfp = 60,
.hlw = 8,
.hbp = 160,
.hfp = 160,
.de_inv = 0,
.hs_inv = 0,
.vs_inv = 0,
.de_en = 1,
.vs_en = 1,
.hs_en = 1,
};
#endif
sdk/lib/bus/spi/lcd/st7701s.c
+385
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@@ -0,0 +1,385 @@
#include "lib/lcd/lcd.h"
#if LCD_ST7701S_EN
#define CMD(x) {LCD_CMD,x}
#define DAT(x) {LCD_DAT,x}
#define DLY(x) {DELAY_MS,x}
#define END {LCD_TAB_END,LCD_TAB_END}
const uint8_t st7701s_register_init_tab[][2] = {
CMD(0x11),
DLY(250),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x13),
CMD(0xEF),
DAT(0x08),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x10),
CMD(0xC0),
DAT(0xE9),
DAT(0x03),
CMD(0xC1),
DAT(0x11),
DAT(0x02),
CMD(0xC2),
DAT(0x07),
DAT(0x06),
CMD(0xC3),
DAT(0x80),
CMD(0xCC),
DAT(0x18),
CMD(0xB0),
DAT(0x00),
DAT(0x0D),
DAT(0x14),
DAT(0x0D),
DAT(0x10),
DAT(0x05),
DAT(0x02),
DAT(0x08),
DAT(0x08),
DAT(0x1E),
DAT(0x05),
DAT(0x13),
DAT(0x11),
DAT(0xA3),
DAT(0x29),
DAT(0x18),
CMD(0xB1),
DAT(0x00),
DAT(0x0C),
DAT(0x14),
DAT(0x0C),
DAT(0x10),
DAT(0x05),
DAT(0x03),
DAT(0x08),
DAT(0x07),
DAT(0x20),
DAT(0x05),
DAT(0x13),
DAT(0x11),
DAT(0xA4),
DAT(0x29),
DAT(0x18),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x11),
CMD(0xB0),
DAT(0x6C),
CMD(0xB1),
DAT(0x4D),
CMD(0xB2),
DAT(0x89),
CMD(0xB3),
DAT(0x80),
CMD(0xB5),
DAT(0x4E),
CMD(0xB7),
DAT(0x85),
CMD(0xB8),
DAT(0x20),
CMD(0xB9),
DAT(0x00),
DAT(0x13),
CMD(0xC0),
DAT(0x09),
CMD(0xC1),
DAT(0x78),
CMD(0xC2),
DAT(0x78),
CMD(0xD0),
DAT(0x88),
CMD(0xE0),
DAT(0x00),
DAT(0x00),
DAT(0x02),
CMD(0xE1),
DAT(0x08),
DAT(0x00),
DAT(0x0A),
DAT(0x00),
DAT(0x07),
DAT(0x00),
DAT(0x09),
DAT(0x00),
DAT(0x00),
DAT(0x33),
DAT(0x33),
CMD(0xE2),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0x00),
CMD(0xE3),
DAT(0x00),
DAT(0x00),
DAT(0x33),
DAT(0x33),
CMD(0xE4),
DAT(0x44),
DAT(0x44),
CMD(0xE5),
DAT(0x0E),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x10),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0A),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0C),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
CMD(0xE6),
DAT(0x00),
DAT(0x00),
DAT(0x33),
DAT(0x33),
CMD(0xE7),
DAT(0x44),
DAT(0x44),
CMD(0xE8),
DAT(0x0D),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0F),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x09),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
DAT(0x0B),
DAT(0x60),
DAT(0xA0),
DAT(0xA0),
CMD(0xEB),
DAT(0x02),
DAT(0x01),
DAT(0xE4),
DAT(0xE4),
DAT(0x44),
DAT(0x00),
DAT(0x40),
CMD(0xEC),
DAT(0x02),
DAT(0x01),
CMD(0xED),
DAT(0xAB),
DAT(0x89),
DAT(0x76),
DAT(0x54),
DAT(0x01),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0xFF),
DAT(0x10),
DAT(0x45),
DAT(0x67),
DAT(0x98),
DAT(0xBA),
CMD(0xEF),
DAT(0x08),
DAT(0x08),
DAT(0x08),
DAT(0x45),
DAT(0x3F),
DAT(0x54),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x13),
CMD(0xE8),
DAT(0x00),
DAT(0x0E),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x00),
CMD(0x11),
DAT(0x00),
DLY (120),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x13),
CMD(0xE8),
DAT(0x00),
DAT(0x0C),
DLY (10),
CMD(0xE8),
DAT(0x00),
DAT(0x00),
CMD(0xE6),
DAT(0x16),
DAT(0x7C),
CMD(0xFF),
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x00),
/*
CMD(0xFF),//bist mode
DAT(0x77),
DAT(0x01),
DAT(0x00),
DAT(0x00),
DAT(0x12),
CMD(0xD1),
DAT(0x81),
CMD(0xD2),
DAT(0x06),//bist mode 0x00列灰阶分两半 02红03绿04蓝05白边框06棋盘格07黑底白像素网格08RGB彩条
*/
CMD(0x3A),
DAT(0x55),
CMD(0x29),
DAT(0x00),
DLY (20),
END
};
lcddev_t lcdstruct = {
.name = "st7701s",
.lcd_bus_type = LCD_BUS_RGB,
.bus_width = LCD_BUS_WIDTH_16,
.color_mode = LCD_MODE_565,
.osd_scan_mode = LCD_ROTATE_90,
.scan_mode = LCD_ROTATE_90,//rotate 90
.te_mode = 0xff,//te mode, 0xff:disable
.colrarray = 0,//0:_RGB_ 1:_RBG_,2:_GBR_,3:_GRB_,4:_BRG_,5:_BGR_
.pclk = 20000000,
.even_order = 0,
.odd_order = 0,
.screen_w = 480,
.screen_h = 848,
.video_x = 0,
.video_y = 0,
.video_w = 480,
.video_h = 848,
.osd_x = 0,
.osd_y = 0,
.osd_w = 480, // 0 : value will set to video_w , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.osd_h = 848, // 0 : value will set to video_h , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.init_table = st7701s_register_init_tab,
.pclk_inv = 1,
.vlw = 10,
.vbp = 6,
.vfp = 10,
.hlw = 8,
.hbp = 8,
.hfp = 30,
.de_inv = 0,
.hs_inv = 1,
.vs_inv = 1,
.de_en = 1,
.vs_en = 1,
.hs_en = 1,
};
#endif
sdk/lib/bus/spi/lcd/st7789v.c
+173
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#include "lib/lcd/lcd.h"
#if LCD_ST7789V_EN
#define CMD(x) {LCD_CMD,x}
#define DAT(x) {LCD_DAT,x}
#define DLY(x) {DELAY_MS,x}
#define END {LCD_TAB_END,LCD_TAB_END}
uint8_t st7789_register_init_tab[][2] = {
//Sleep Out
CMD( 0x11),
DLY( 0x64),
//TEON,and Not consist of HBlanking
CMD( 0x35),
DAT( 0x00),
//Set Tear Scanline,when display 0th line,the TE output
CMD( 0x44),
DAT( 0x00),
DAT( 0x00),
//65K-color RGB interface,and 18bit/pixel
CMD( 0x3A),
DAT( 0x66), // 18bit/pixel DB[6:4]
CMD( 0x21),
CMD( 0xB0),
DAT( 0x11), //RGB mode
DAT( 0xF4), //6bit bus width 666 mode set RIM=1
CMD( 0xB1),
DAT( 0xe0), //RGB hv mode,vsync low active,hsync low active
DAT( 0x05), //vbp
DAT( 0x14), //hbp
//Porch Setting(set VBlank),back porch 8,front porch 8
CMD( 0xB2),
DAT( 0x08), //bpa
DAT( 0x08),
DAT( 0x00),
DAT( 0x22),
DAT( 0x22),
//Gate Control
CMD( 0xB7),
DAT( 0x35),
//-----------------Power Setting------------------
CMD( 0xBB),
DAT( 0x27),
CMD( 0xC0),
DAT( 0x2C),
CMD( 0xC2),
DAT( 0x01),
CMD( 0xC6),
DAT( 0x18),
CMD( 0xC6),
DAT( 0x0F),
CMD( 0xC4),
DAT( 0x20),
CMD( 0xC3),
DAT( 0x10),
CMD( 0xCA),
DAT( 0x0F),
CMD( 0xD0),
DAT( 0xA4),
DAT( 0xA1),
//-----------------Gamma Setting--------------------
CMD( 0xE0),
DAT( 0xD0),
DAT( 0x00),
DAT( 0x03),
DAT( 0x09),
DAT( 0x13),
DAT( 0x1C),
DAT( 0x3A),
DAT( 0x55),
DAT( 0x48),
DAT( 0x18),
DAT( 0x12),
DAT( 0x0E),
DAT( 0x20),
DAT( 0x1E),
CMD( 0xE1),
DAT( 0xD0),
DAT( 0x00),
DAT( 0x03),
DAT( 0x09),
DAT( 0x05),
DAT( 0x25),
DAT( 0x3A),
DAT( 0x55),
DAT( 0x50),
DAT( 0x3D),
DAT( 0x1C),
DAT( 0x1D),
DAT( 0x21),
DAT( 0x1E),
CMD( 0x36),
DAT( 0xC0),
DLY( 0X0F),
CMD( 0x11),
DLY( 0x64),
//Display on
CMD( 0x29),
DLY( 0X05),
//Memory Write
END
};
lcddev_t lcdstruct = {
.name = "st7789",
.lcd_bus_type = LCD_BUS_RGB,
.bus_width = LCD_BUS_WIDTH_6,
.color_mode = LCD_MODE_666,
.osd_scan_mode = LCD_ROTATE_90,
.scan_mode = LCD_ROTATE_90,//rotate 90
.te_mode = 0xff,//te mode, 0xff:disable
.colrarray = 0,//0:_RGB_ 1:_RBG_,2:_GBR_,3:_GRB_,4:_BRG_,5:_BGR_
.pclk = 15000000,
.even_order = 0,
.odd_order = 0,
.screen_w = 240,
.screen_h = 320,
.video_x = 0,
.video_y = 0,
.video_w = 240,
.video_h = 320,
.osd_x = 0,
.osd_y = 0,
.osd_w = 240, // 0 : value will set to video_w , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.osd_h = 320, // 0 : value will set to video_h , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.init_table = st7789_register_init_tab,
.pclk_inv = 1,
.vlw = 1,// 0,
.vbp = 0x04,// 12,
.vfp = 8,// 12,
.hlw = 4,// 1,
.hbp = 0x3c,//14,
.hfp = 12,//13,
.de_en = 1,
.vs_en = 1,
.hs_en = 1,
.de_inv = 0,
.hs_inv = 0,
.vs_inv = 0,
};
#endif
sdk/lib/bus/spi/lcd/st7789v_mcu565.c
+196
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#include "lib/lcd/lcd.h"
#if LCD_ST7789V_MCU565_EN
#define CMD(x) {LCD_CMD,x}
#define DAT(x) {LCD_DAT,x}
#define DLY(x) {DELAY_MS,x}
#define END {LCD_TAB_END,LCD_TAB_END}
uint8_t st7789_register_init_tab[][2] = {
//Sleep Out
CMD( 0x11),
DLY( 0x64),
//TEON,and Not consist of HBlanking
CMD( 0x35),
DAT( 0x00),
//Set Tear Scanline,when display 0th line,the TE output
CMD( 0x44),
DAT( 0x00),
DAT( 0x00),
//65K-color RGB interface,and 18bit/pixel
CMD( 0x3A),
DAT( 0x05), // 16bit/pixel
CMD( 0x21),
#if 0
CMD( 0xB0),
DAT( 0x00), //RGB mode
DAT( 0xF4), //6bit bus width 666 mode
#endif
CMD( 0xB1),
DAT( 0x40), //RGB hv mode,vsync low active,hsync low active
DAT( 0x02), //vbp
DAT( 0x14), //hbp
//Porch Setting(set VBlank),back porch 8,front porch 8
CMD( 0xB2),
DAT( 0x08), //bpa
DAT( 0x08),
DAT( 0x00),
DAT( 0x22),
DAT( 0x22),
//Gate Control
CMD( 0xB7),
DAT( 0x35),
//-----------------Power Setting------------------
CMD( 0xBB),
DAT( 0x27),
CMD( 0xC0),
DAT( 0x2C),
CMD( 0xC2),
DAT( 0x01),
CMD( 0xC6),
DAT( 0x18),
CMD( 0xC6),
DAT( 0x0F),
CMD( 0xC4),
DAT( 0x20),
CMD( 0xC3),
DAT( 0x10),
CMD( 0xCA),
DAT( 0x0F),
CMD( 0xD0),
DAT( 0xA4),
DAT( 0xA1),
//-----------------Gamma Setting--------------------
CMD( 0xE0),
DAT( 0xD0),
DAT( 0x00),
DAT( 0x03),
DAT( 0x09),
DAT( 0x13),
DAT( 0x1C),
DAT( 0x3A),
DAT( 0x55),
DAT( 0x48),
DAT( 0x18),
DAT( 0x12),
DAT( 0x0E),
DAT( 0x20),
DAT( 0x1E),
CMD( 0xE1),
DAT( 0xD0),
DAT( 0x00),
DAT( 0x03),
DAT( 0x09),
DAT( 0x05),
DAT( 0x25),
DAT( 0x3A),
DAT( 0x55),
DAT( 0x50),
DAT( 0x3D),
DAT( 0x1C),
DAT( 0x1D),
DAT( 0x21),
DAT( 0x1E),
CMD( 0x36),
DAT( 0x00),
DLY( 0X0F),
CMD(0x2a),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0xef),
CMD(0x2b),
DAT(0x00),
DAT(0x00),
DAT(0x01),
DAT(0x3f),
CMD( 0x11),
DLY( 0x64),
//Display on
CMD( 0x29),
DLY( 0X05),
//Memory Write
CMD(0x2c), //启动写入
END
};
lcddev_t lcdstruct = {
.name = "st7789",
.lcd_bus_type = LCD_BUS_I80,
.bus_width = LCD_BUS_WIDTH_8,
.color_mode = LCD_MODE_565,
.osd_scan_mode = LCD_ROTATE_90,
.scan_mode = LCD_ROTATE_90,//rotate 90
.te_mode = 0xff,//te mode, 0xff:disable
.colrarray = 0,//0:_RGB_ 1:_RBG_,2:_GBR_,3:_GRB_,4:_BRG_,5:_BGR_
.pclk = 10000000,
.even_order = 0,
.odd_order = 0,
.screen_w = 240,
.screen_h = 320,
.video_x = 0,
.video_y = 0,
.video_w = 240,
.video_h = 320,
.osd_x = 0,
.osd_y = 0,
.osd_w = 240, // 0 : value will set to video_w , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.osd_h = 320, // 0 : value will set to video_h , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.init_table = st7789_register_init_tab,
.pclk_inv = 0,
.vlw = 0,// 0,
.vbp = 0,// 12,
.vfp = 0,// 12,
.hlw = 0,// 1,
.hbp = 0,//14,
.hfp = 0,//13,
.de_en = 0,
.vs_en = 0,
.hs_en = 0,
.de_inv = 0,
.hs_inv = 0,
.vs_inv = 0,
.signal_config.mcu.resev = 0,
.signal_config.mcu.wr_inv = 1,
.signal_config.mcu.rd_inv = 0,
.signal_config.mcu.cs_inv = 0,
.signal_config.mcu.dc_inv = 1,
};
#endif
sdk/lib/bus/spi/lcd/st7789v_mcu666.c
+198
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#include "lib/lcd/lcd.h"
#if LCD_ST7789V_MCU666_EN
#define CMD(x) {LCD_CMD,x}
#define DAT(x) {LCD_DAT,x}
#define DLY(x) {DELAY_MS,x}
#define END {LCD_TAB_END,LCD_TAB_END}
uint8_t st7789_register_init_tab[][2] = {
//Sleep Out
CMD( 0x11),
DLY( 0x64),
//TEON,and Not consist of HBlanking
CMD( 0x35),
DAT( 0x00),
//Set Tear Scanline,when display 0th line,the TE output
CMD( 0x44),
DAT( 0x00),
DAT( 0x00),
//65K-color RGB interface,and 18bit/pixel
CMD( 0x3A),
DAT( 0x06), // 16bit/pixel
CMD( 0x21),
#if 0
CMD( 0xB0),
DAT( 0x00), //RGB mode
DAT( 0xF4), //6bit bus width 666 mode
#endif
CMD( 0xB1),
DAT( 0x40), //RGB hv mode,vsync low active,hsync low active
DAT( 0x02), //vbp
DAT( 0x14), //hbp
//Porch Setting(set VBlank),back porch 8,front porch 8
CMD( 0xB2),
DAT( 0x08), //bpa
DAT( 0x08),
DAT( 0x00),
DAT( 0x22),
DAT( 0x22),
//Gate Control
CMD( 0xB7),
DAT( 0x35),
//-----------------Power Setting------------------
CMD( 0xBB),
DAT( 0x27),
CMD( 0xC0),
DAT( 0x2C),
CMD( 0xC2),
DAT( 0x01),
CMD( 0xC6),
DAT( 0x18),
CMD( 0xC6),
DAT( 0x0F),
CMD( 0xC4),
DAT( 0x20),
CMD( 0xC3),
DAT( 0x10),
CMD( 0xCA),
DAT( 0x0F),
CMD( 0xD0),
DAT( 0xA4),
DAT( 0xA1),
//-----------------Gamma Setting--------------------
CMD( 0xE0),
DAT( 0xD0),
DAT( 0x00),
DAT( 0x03),
DAT( 0x09),
DAT( 0x13),
DAT( 0x1C),
DAT( 0x3A),
DAT( 0x55),
DAT( 0x48),
DAT( 0x18),
DAT( 0x12),
DAT( 0x0E),
DAT( 0x20),
DAT( 0x1E),
CMD( 0xE1),
DAT( 0xD0),
DAT( 0x00),
DAT( 0x03),
DAT( 0x09),
DAT( 0x05),
DAT( 0x25),
DAT( 0x3A),
DAT( 0x55),
DAT( 0x50),
DAT( 0x3D),
DAT( 0x1C),
DAT( 0x1D),
DAT( 0x21),
DAT( 0x1E),
CMD( 0x26),
DAT( 0x01),
CMD( 0x36),
DAT( 0x00),
DLY( 0X0F),
CMD(0x2a),
DAT(0x00),
DAT(0x00),
DAT(0x00),
DAT(0xef),
CMD(0x2b),
DAT(0x00),
DAT(0x00),
DAT(0x01),
DAT(0x3f),
CMD( 0x11),
DLY( 0x64),
//Display on
CMD( 0x29),
DLY( 0X05),
//Memory Write
CMD(0x2c), //启动写入
END
};
lcddev_t lcdstruct = {
.name = "st7789",
.lcd_bus_type = LCD_BUS_I80,
.bus_width = LCD_BUS_WIDTH_8,
.color_mode = LCD_MODE_666,
.osd_scan_mode = LCD_ROTATE_90,
.scan_mode = LCD_ROTATE_90,//rotate 90
.te_mode = 0xff,//te mode, 0xff:disable
.colrarray = 0,//0:_RGB_ 1:_RBG_,2:_GBR_,3:_GRB_,4:_BRG_,5:_BGR_
.pclk = 10000000,
.even_order = 0,
.odd_order = 0,
.screen_w = 240,
.screen_h = 320,
.video_x = 0,
.video_y = 0,
.video_w = 240,
.video_h = 320,
.osd_x = 0,
.osd_y = 0,
.osd_w = 240, // 0 : value will set to video_w , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.osd_h = 320, // 0 : value will set to video_h , use for 4:3 LCD +16:9 sensor show UPDOWN BLACK
.init_table = st7789_register_init_tab,
.pclk_inv = 0,
.vlw = 0,// 0,
.vbp = 0,// 12,
.vfp = 0,// 12,
.hlw = 0,// 1,
.hbp = 0,//14,
.hfp = 0,//13,
.de_en = 0,
.vs_en = 0,
.hs_en = 0,
.de_inv = 0,
.hs_inv = 0,
.vs_inv = 0,
.signal_config.mcu.resev = 0,
.signal_config.mcu.wr_inv = 1,
.signal_config.mcu.rd_inv = 0,
.signal_config.mcu.cs_inv = 0,
.signal_config.mcu.dc_inv = 1,
};
#endif
sdk/lib/bus/spi/spi_nor/spi_nor_bus.c
+980
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#include "typesdef.h"
#include "list.h"
#include "errno.h"
#include "dev.h"
#include "hal/spi.h"
#include "hal/spi_nor.h"
#include "osal/sleep.h"
/**
* @brief Standard SPI instructions
*/
#define SPI_NOR_STANDARD_WRITE_ENABLE 0x06
#define SPI_NOR_STANDARD_WRITE_DISABLE 0x04
#define SPI_NOR_STANDARD_READ_STATUS_REG 0x05
#define SPI_NOR_STANDARD_WRITE_STATUS_REG 0x01
#define SPI_NOR_STANDARD_PAGE_PROGRAM 0x02
#define SPI_NOR_STANDARD_SECTOR_ERASE 0x20
#define SPI_NOR_STANDARD_BLOCK_ERASE 0xD8
#define SPI_NOR_STANDARD_CHIP_ERASE 0xC7//0x60
#define SPI_NOR_STANDARD_ERASE_SUSPEND 0x75
#define SPI_NOR_STANDARD_ERASE_RESUME 0x7A
#define SPI_NOR_STANDARD_READ_DATA 0x03
#define SPI_NOR_STANDARD_FAST_READ 0x0B
#define SPI_NOR_STANDARD_RELEASE_POWERDOWN_ID 0xAB
#define SPI_NOR_STANDARD_DEVICE_ID 0x90
#define SPI_NOR_STANDARD_JEDEC_ID 0x9F
#define SPI_NOR_STANDARD_ENABLE_QPI 0x38
#define SPI_NOR_STANDARD_POWER_DOWN 0xB9
#define SPI_NOR_STANDARD_RELEASE_POWER_DOWN 0xAB
#define SPI_NOR_STANDARD_ERASE_SECURITY_REG 0x44
#define SPI_NOR_STANDARD_PROGRAM_SECURITY_REG 0x42
#define SPI_NOR_STANDARD_READ_SECURITY_REG 0x48
/**
* @}
*/
/**
* @brief Dual SPI instructions
*/
#define SPI_NOR_DUAL_FAST_READ_DUAL_OUTPUT 0x3B
#define SPI_NOR_DUAL_FAST_READ_DUAL_IO 0xBB
/**
* @}
*/
/**
* @brief Quad SPI instructions
*/
#define SPI_NOR_QUAD_PAGE_PROGRAM 0x32
#define SPI_NOR_QUAD_FAST_READ_QUAD_OUTPUT 0x6B
#define SPI_NOR_QUAD_FAST_READ_QUAD_IO 0xEB
/**
* @}
*/
/**
* @brief QPI instructions
*/
#define SPI_NOR_QPI_WRITE_ENABLE 0x06
#define SPI_NOR_QPI_WRITE_DISABLE 0x04
#define SPI_NOR_QPI_READ_STATUS_REG 0x05
#define SPI_NOR_QPI_WRITE_STATUS_REG 0x01
#define SPI_NOR_QPI_PAGE_PROGRAM 0x02
#define SPI_NOR_QPI_SECTOR_ERASE 0x20
#define SPI_NOR_QPI_BLOCK_ERASE 0xD8
#define SPI_NOR_QPI_CHIP_ERASE 0xC7
#define SPI_NOR_QPI_ERASE_SUSPEND 0x75
#define SPI_NOR_QPI_ERASE_RESUME 0x7A
#define SPI_NOR_QPI_FAST_READ 0x0B
#define SPI_NOR_QPI_FAST_READ_QUAD_IO 0xEB
#define SPI_NOR_QPI_JEDEC_ID 0x9F
#define SPI_NOR_QPI_DISABLE_QPI 0xFF
/**
* @}
*/
/**
* @brief SPI NOR STATUS register
*/
#define SPI_NOR_STATUS_BUSY 0x01
#define SPI_NOR_STATUS_WEL 0x02
#define SPI_NOR_STATUS2_QUAD_ENABLE 0x200
/**
* @}
*/
/**
* @brief Standard SPI instructions
*/
//JECEC ID
void spi_nor_standard_read_jedec_id(struct spi_nor_flash *flash, uint8 *buf)
{
uint8 instruction = SPI_NOR_STANDARD_JEDEC_ID;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_read(flash->spidev, buf, 3);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//write disable
static void spi_nor_standard_write_disable(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_WRITE_DISABLE;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//write enable
static void spi_nor_standard_write_enable(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_WRITE_ENABLE;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//read status register
static uint8 spi_nor_standard_read_status_register(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_READ_STATUS_REG;
uint8 result;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_read(flash->spidev, &result, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
return result;
}
//write status register
static void spi_nor_standard_write_status_register(struct spi_nor_flash *flash, uint16 data)
{
uint8 write_buf[3];
spi_nor_standard_write_enable(flash);
write_buf[0] = SPI_NOR_STANDARD_WRITE_STATUS_REG;
write_buf[1] = data;
write_buf[2] = data >> 8;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 3);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_nor_standard_write_disable(flash);
}
//read data
static void spi_nor_standard_read_data(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[4];
write_buf[0] = SPI_NOR_STANDARD_READ_DATA;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_read(flash->spidev, buf, buf_size);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//fast read
static void spi_nor_standard_fast_read(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[5];
write_buf[0] = SPI_NOR_STANDARD_FAST_READ;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
write_buf[4] = 0x00; //dummy clock
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 5);
spi_read(flash->spidev, buf, buf_size);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//page program
static void spi_nor_standard_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[4];
spi_nor_standard_write_enable(flash);
write_buf[0] = SPI_NOR_STANDARD_PAGE_PROGRAM;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_write(flash->spidev, buf, buf_size);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
//wait page program done
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_standard_write_disable(flash);
}
//sector erase
static void spi_nor_standard_sector_erase(struct spi_nor_flash *flash, uint32 addr)
{
uint8 write_buf[4];
spi_nor_standard_write_enable(flash);
write_buf[0] = SPI_NOR_STANDARD_SECTOR_ERASE;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
//wait sector erase done
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_standard_write_disable(flash);
}
//block erase
static void spi_nor_standard_block_erase(struct spi_nor_flash *flash, uint32 addr)
{
uint8 write_buf[4];
spi_nor_standard_write_enable(flash);
write_buf[0] = SPI_NOR_STANDARD_BLOCK_ERASE;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
//wait block erase done
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_standard_write_disable(flash);
}
//chip erase
static void spi_nor_standard_chip_erase(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_CHIP_ERASE;
spi_nor_standard_write_enable(flash);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
//wait block erase done
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_standard_write_disable(flash);
}
//enter QPI
static void spi_nor_standard_enter_qpi(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_ENABLE_QPI;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//enter power down
static void spi_nor_standard_power_down(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_POWER_DOWN;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//release power down
static void spi_nor_standard_release_power_down(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_RELEASE_POWER_DOWN;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//erase security registers
static void spi_nor_standard_erase_security_reg(struct spi_nor_flash *flash, uint32 addr)
{
uint8 write_buf[4];
spi_nor_standard_write_enable(flash);
write_buf[0] = SPI_NOR_STANDARD_ERASE_SECURITY_REG;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
//wait block erase done
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_standard_write_disable(flash);
}
//program security registers
static void spi_nor_standard_program_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[4];
spi_nor_standard_write_enable(flash);
write_buf[0] = SPI_NOR_STANDARD_PROGRAM_SECURITY_REG;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_write(flash->spidev, buf, buf_size);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
//wait block erase done
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_standard_write_disable(flash);
}
//read security registers
static void spi_nor_standard_read_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[5];
write_buf[0] = SPI_NOR_STANDARD_READ_SECURITY_REG;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
write_buf[4] = 0; //dummy
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 5);
spi_read(flash->spidev, buf, buf_size);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
static void spi_nor_standard_open(struct spi_nor_flash *flash)
{
//release power down
//spi_nor_standard_release_power_down(flash);
//wait done
//os_sleep_us(100);
}
/**
* @}
*/
/**
* @brief Dual SPI instructions
*/
//fast read dual output
//If flash supports DUAL, this function is also generally supported
static void spi_nor_dual_fast_read_dual_output(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[5];
write_buf[0] = SPI_NOR_DUAL_FAST_READ_DUAL_OUTPUT;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
write_buf[4] = 0x00; //dummy clock
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
//instruction & address & dummy clock should tx in Standard SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_write(flash->spidev, write_buf, 5);
//data rx in DUAL SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_DUAL_MODE, 0);
spi_read(flash->spidev, buf, buf_size);
//Return to normal mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//fast read dual IO
//warning! You need to confirm that nor flash supports this function.
static void spi_nor_dual_fast_read_dual_io(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[5];
write_buf[0] = SPI_NOR_DUAL_FAST_READ_DUAL_IO;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
write_buf[4] = 0x00;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
//instruction should tx in Standard SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_write(flash->spidev, write_buf, 1);
//address & dummy clock should tx in DUAL SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_DUAL_MODE, 0);
spi_write(flash->spidev, &write_buf[1], 4);
//data rx in DUAL SPI mode
spi_read(flash->spidev, buf, buf_size);
//Return to normal mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
static void spi_nor_quad_open(struct spi_nor_flash *flash)
{
uint16 status;
//release power down
spi_nor_standard_release_power_down(flash);
//wait done
os_sleep_us(50);
status = spi_nor_standard_read_status_register(flash);
status |= SPI_NOR_STATUS2_QUAD_ENABLE;
spi_nor_standard_write_status_register(flash, status);
}
/**
* @}
*/
/**
* @brief Quad SPI instructions
* @note warning! You need to confirm that nor flash supports this function.
*/
//fast read quad output
static void spi_nor_quad_fast_read_quad_output(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[5];
write_buf[0] = SPI_NOR_QUAD_FAST_READ_QUAD_OUTPUT;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
write_buf[4] = 0x00; //dummy clock
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
//instruction & address & dummy clock should tx in Standard SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_write(flash->spidev, write_buf, 5);
//data rx in QUAD SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_read(flash->spidev, buf, buf_size);
//Return to normal mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//fast read quad IO
static void spi_nor_quad_fast_read_quad_io(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[7];
write_buf[0] = SPI_NOR_QUAD_FAST_READ_QUAD_IO;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
write_buf[4] = 0x00;
write_buf[5] = 0x00; //dummy clock
write_buf[6] = 0x00; //dummy clock
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
//instruction should tx in Standard SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_write(flash->spidev, write_buf, 1);
//address & dummy clock should tx in QUAD SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_write(flash->spidev, &write_buf[1], 6);
//data rx in DUAL SPI mode
spi_read(flash->spidev, buf, buf_size);
//Return to normal mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//quad input page program
static void spi_nor_quad_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[4];
write_buf[0] = SPI_NOR_QUAD_PAGE_PROGRAM;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_nor_standard_write_enable(flash);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
//data tx in QUAD SPI mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_write(flash->spidev, buf, buf_size);
//Return to normal mode
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
//wait tx done
while (spi_nor_standard_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_standard_write_disable(flash);
}
/**
* @}
*/
/**
* @brief QPI instructions
* @note warning! You need to confirm that nor flash supports this function.
*/
//JECEC ID
static void spi_nor_qpi_read_jedec_id(struct spi_nor_flash *flash, uint8 *buf)
{
uint8 instruction = SPI_NOR_QPI_JEDEC_ID;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_read(flash->spidev, buf, 3);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
}
//write disable
static void spi_nor_qpi_write_disable(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_QPI_WRITE_DISABLE;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
}
//write enable
static void spi_nor_qpi_write_enable(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_QPI_WRITE_ENABLE;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
}
//read status register
static uint8 spi_nor_qpi_read_status_register(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_QPI_READ_STATUS_REG;
uint8 result;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_read(flash->spidev, &result, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
return result;
}
//write status register
static void spi_nor_qpi_write_status_register(struct spi_nor_flash *flash, uint16 data)
{
uint8 write_buf[3];
spi_nor_qpi_write_enable(flash);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
write_buf[0] = SPI_NOR_QPI_WRITE_STATUS_REG;
write_buf[1] = data;
write_buf[2] = data >> 8;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 3);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
spi_nor_qpi_write_disable(flash);
}
//fast read quad io
static void spi_nor_qpi_fast_read_quad_io(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[5];
write_buf[0] = SPI_NOR_QPI_FAST_READ_QUAD_IO;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
write_buf[4] = 0x00;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 5);
spi_read(flash->spidev, buf, buf_size);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
}
//page program
static void spi_nor_qpi_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
uint8 write_buf[4];
spi_nor_qpi_write_enable(flash);
write_buf[0] = SPI_NOR_QPI_PAGE_PROGRAM;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_write(flash->spidev, buf, buf_size);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
//wait page program done
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_qpi_write_disable(flash);
}
//sector erase
static void spi_nor_qpi_sector_erase(struct spi_nor_flash *flash, uint32 addr)
{
uint8 write_buf[4];
spi_nor_qpi_write_enable(flash);
write_buf[0] = SPI_NOR_QPI_SECTOR_ERASE;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
//wait sector erase done
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_qpi_write_disable(flash);
}
//block erase
static void spi_nor_qpi_block_erase(struct spi_nor_flash *flash, uint32 addr)
{
uint8 write_buf[4];
spi_nor_qpi_write_enable(flash);
write_buf[0] = SPI_NOR_QPI_BLOCK_ERASE;
write_buf[1] = addr >> 16;
write_buf[2] = addr >> 8;
write_buf[3] = addr;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, write_buf, 4);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
//wait block erase done
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_qpi_write_disable(flash);
}
//chip erase
static void spi_nor_qpi_chip_erase(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_QPI_CHIP_ERASE;
spi_nor_qpi_write_enable(flash);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
//wait block erase done
while (spi_nor_qpi_read_status_register(flash) & SPI_NOR_STATUS_BUSY);
spi_nor_qpi_write_disable(flash);
}
//disable QPI
static void spi_nor_standard_disable_qpi(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_QPI_DISABLE_QPI;
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_QUAD_MODE, 0);
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
spi_ioctl(flash->spidev, SPI_WIRE_MODE_SET, SPI_WIRE_NORMAL_MODE, 0);
}
//enter power down
static void spi_nor_qpi_power_down(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_POWER_DOWN;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
//release power down
static void spi_nor_qpi_release_power_down(struct spi_nor_flash *flash)
{
uint8 instruction = SPI_NOR_STANDARD_RELEASE_POWER_DOWN;
spi_set_cs(flash->spidev, flash->spi_config.cs, 0);
spi_write(flash->spidev, &instruction, 1);
spi_set_cs(flash->spidev, flash->spi_config.cs, 1);
}
static void spi_nor_qpi_open(struct spi_nor_flash *flash)
{
uint16 status;
//release power down
spi_nor_qpi_release_power_down(flash);
//wait done
os_sleep_us(50);
status = spi_nor_standard_read_status_register(flash);
status |= SPI_NOR_STATUS2_QUAD_ENABLE;
spi_nor_standard_write_status_register(flash, status);
spi_nor_standard_enter_qpi(flash);
}
static void spi_nor_qpi_close(struct spi_nor_flash *flash)
{
spi_nor_standard_disable_qpi(flash);
}
static void spi_nor_xip_open(struct spi_nor_flash *flash)
{
}
static void spi_nor_xip_close(struct spi_nor_flash *flash)
{
}
static void spi_nor_xip_read_data(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_READ);
spi_read(flash->spidev, buf, buf_size);
}
static void spi_nor_xip_page_program(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_WRITE);
spi_write(flash->spidev, buf, buf_size);
}
static void spi_nor_xip_sector_erase(struct spi_nor_flash *flash, uint32 addr)
{
spi_ioctl(flash->spidev,SPI_XIP_ERASE_4KB,addr, XIP_ERASE);
}
static void spi_nor_xip_block_erase(struct spi_nor_flash *flash, uint32 addr)
{
spi_ioctl(flash->spidev,SPI_XIP_ERASE_64KB,addr, 0);
}
//erase security registers
static void spi_nor_xip_erase_security_reg(struct spi_nor_flash *flash, uint32 addr)
{
spi_ioctl(flash->spidev,SPI_XIP_ERASE_SECURITY_REG,addr, 0);
}
//program security registers
static void spi_nor_xip_program_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_SECURITY_WRITE);
spi_ioctl(flash->spidev,SPI_XIP_PROGRAM_SECURITY_REG, (uint32)buf, buf_size);
}
//read security registers
static void spi_nor_xip_read_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 buf_size)
{
spi_ioctl(flash->spidev,SPI_XIP_SET_ADR,addr, XIP_SECURITY_READ);
spi_ioctl(flash->spidev,SPI_XIP_READ_SECURITY_REG, (uint32)buf, buf_size);
}
static void spi_nor_xip_custom_read_data(struct spi_nor_flash *flash, uint32_t param)
{
spi_ioctl(flash->spidev,SPI_XIP_CUSTOM_READ_CMD,param,0);
}
static void spi_nor_xip_custom_write_data(struct spi_nor_flash *flash, uint32_t param)
{
spi_ioctl(flash->spidev,SPI_XIP_CUSTOM_WRITE_CMD,param,0);
}
static void spi_nor_xip_custom_erase(struct spi_nor_flash *flash, uint32_t param)
{
spi_ioctl(flash->spidev,SPI_XIP_CUSTOM_ERASE_CMD,param,0);
}
static void spi_nor_xip_reg_opt(struct spi_nor_flash *flash, uint32_t param)
{
spi_ioctl(flash->spidev,SPI_XIP_REG_OPT, param, 0);
}
static int32 spi_nor_xip_ioctl(struct spi_nor_flash *flash, uint32_t cmd,uint32_t param1,uint32_t param2)
{
return spi_ioctl(flash->spidev,cmd,param1,param2);
}
/**
* @}
*/
//SPI NOR function
static const struct spi_nor_bus spinor_bus_list[] = {
//NORMAL SPI
{
spi_nor_standard_open,
NULL,
spi_nor_standard_read_data,
spi_nor_standard_page_program,
spi_nor_standard_sector_erase,
spi_nor_standard_block_erase,
spi_nor_standard_chip_erase,
spi_nor_standard_power_down,
spi_nor_standard_release_power_down,
spi_nor_standard_erase_security_reg,
spi_nor_standard_program_security_reg,
spi_nor_standard_read_security_reg,
},
//DUAL SPI
{
spi_nor_standard_open,
NULL,
spi_nor_dual_fast_read_dual_output,
spi_nor_standard_page_program,
spi_nor_standard_sector_erase,
spi_nor_standard_block_erase,
spi_nor_standard_chip_erase,
spi_nor_standard_power_down,
spi_nor_standard_release_power_down,
spi_nor_standard_erase_security_reg,
spi_nor_standard_program_security_reg,
spi_nor_standard_read_security_reg,
},
//QUAD SPI
{
spi_nor_quad_open,
NULL,
spi_nor_quad_fast_read_quad_output,
spi_nor_quad_page_program,
spi_nor_standard_sector_erase,
spi_nor_standard_block_erase,
spi_nor_standard_chip_erase,
spi_nor_standard_power_down,
spi_nor_standard_release_power_down,
spi_nor_standard_erase_security_reg,
spi_nor_standard_program_security_reg,
spi_nor_standard_read_security_reg,
},
//QPI
{
spi_nor_qpi_open,
spi_nor_qpi_close,
spi_nor_qpi_fast_read_quad_io,
spi_nor_qpi_page_program,
spi_nor_qpi_sector_erase,
spi_nor_qpi_block_erase,
spi_nor_qpi_chip_erase,
spi_nor_qpi_power_down,
spi_nor_qpi_release_power_down,
spi_nor_standard_erase_security_reg,
spi_nor_standard_program_security_reg,
spi_nor_standard_read_security_reg,
},
//XIP
{
spi_nor_xip_open,
spi_nor_xip_close,
spi_nor_xip_read_data,
spi_nor_xip_page_program,
spi_nor_xip_sector_erase,
spi_nor_xip_block_erase,
NULL,
NULL,
NULL,
spi_nor_xip_erase_security_reg,
spi_nor_xip_program_security_reg,
spi_nor_xip_read_security_reg,
spi_nor_xip_custom_read_data,
spi_nor_xip_custom_write_data,
spi_nor_xip_custom_erase,
spi_nor_xip_ioctl,
},
};
const struct spi_nor_bus * spi_nor_bus_get(enum spi_nor_mode mode)
{
ASSERT(mode < ARRAY_SIZE(spinor_bus_list));
return &spinor_bus_list[mode];
}