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pure sdk for main

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divadiow
2025-08-27 09:51:58 +01:00
parent f0d033f1c9
commit 0571416e7c
3283 changed files with 1577720 additions and 1 deletions
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sdk/include/hal/adc.h
+196
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@@ -0,0 +1,196 @@
#ifndef _HAL_ADC_H_
#define _HAL_ADC_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief ADC ioctl_cmd type
*/
enum adc_ioctl_cmd {
RESERVE,
};
/**
* @brief ADC irq_flag type
*/
enum adc_irq_flag {
/*! Compatible version: V0;
*@ Describe:
*
*/
ADC_IRQ_FLAG_SAMPLE_DONE = BIT(0),
};
/* User interrupt handle */
typedef void (*adc_irq_hdl)(uint32 irq, uint32 channel, uint32 irq_data);
/* ADC api for user */
struct adc_device {
struct dev_obj dev;
};
struct adc_hal_ops{
struct devobj_ops ops;
int32(*open)(struct adc_device *adc);
int32(*close)(struct adc_device *adc);
int32(*add_channel)(struct adc_device *adc, uint32 channel);
int32(*delete_channel)(struct adc_device *adc, uint32 channel);
int32(*get_value)(struct adc_device *adc, uint32 channel, uint32 *raw_data);
int32(*ioctl)(struct adc_device *adc, enum adc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct adc_device *adc, enum adc_irq_flag irq_flag, adc_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct adc_device *adc, enum adc_irq_flag irq_flag);
};
/* ADC API functions */
/**
* @brief adc_open
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_open(struct adc_device *adc);
/**
* @brief adc_close
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_close(struct adc_device *adc);
/**
* @brief adc_add_channel
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_add_channel(struct adc_device *adc, uint32 channel);
/**
* @brief adc_delete_channel
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_delete_channel(struct adc_device *adc, uint32 channel);
/**
* @brief adc_get_value
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_get_value(struct adc_device *adc, uint32 channel, uint32 *raw_data);
/**
* @brief adc_ioctl
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_ioctl(struct adc_device *adc, enum adc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief adc_request_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_request_irq(struct adc_device *adc, enum adc_irq_flag irq_flag, adc_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief adc_release_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param adc The address of adc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 adc_release_irq(struct adc_device *adc, enum adc_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/auadc.h
+204
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#ifndef _AUADC_H
#define _AUADC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUADC sample_rate type
*/
enum auadc_sample_rate {
AUADC_SAMPLE_RATE_8K,
AUADC_SAMPLE_RATE_11_025K,
AUADC_SAMPLE_RATE_16K,
AUADC_SAMPLE_RATE_22_05K,
AUADC_SAMPLE_RATE_32K,
AUADC_SAMPLE_RATE_44_1K,
AUADC_SAMPLE_RATE_48K,
};
/**
* @brief AUADC irq_flag type
*/
enum auadc_irq_flag {
/*!
* @brief:
*
*/
AUADC_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUADC_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUADC ioctl_cmd type
*/
enum auadc_ioctl_cmd {
/*!
* @brief:
*
*/
AUADC_IOCTL_CMD_SET_SAMPLE_RATE,
/*!
* @brief:
*
*/
AUADC_IOCTL_CMD_SET_SOUND_CHANNEL,
/*!
* @brief: Adjust the power digital gain
*
*/
AUADC_IOCTL_CMD_SET_DIGITAL_GAIN,
/*!
* @brief: Adjust the power analog gain
*
*/
AUADC_IOCTL_CMD_SET_ANALOG_GAIN,
};
/* User interrupt handle */
typedef void (*auadc_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUADCC api for user */
struct auadc_device {
struct dev_obj dev;
};
/* AUADC api for user */
struct auadc_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
int32(*close)(struct auadc_device *auadc);
int32(*read)(struct auadc_device *auadc, void* buf, uint32 bytes);
int32(*ioctl)(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
};
/* AUADC API functions */
/**
* @brief auadc_open
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
/**
* @brief auadc_close
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_close(struct auadc_device *auadc);
/**
* @brief auadc_read
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_read(struct auadc_device *auadc, void* buf, uint32 bytes);
/**
* @brief auadc_ioctl
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief auadc_request_irq
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief auadc_release_irq
*
*
* @note .
*
* @param auadc The address of auadc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auadc_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/audac.h
+224
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#ifndef _AUDAC_H
#define _AUDAC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUDAC sample_rate type
*/
enum audac_sample_rate {
AUDAC_SAMPLE_RATE_8K,
AUDAC_SAMPLE_RATE_11_025K,
AUDAC_SAMPLE_RATE_16K,
AUDAC_SAMPLE_RATE_22_05K,
AUDAC_SAMPLE_RATE_32K,
AUDAC_SAMPLE_RATE_44_1K,
AUDAC_SAMPLE_RATE_48K,
AUDAC_SAMPLE_RATE_12K,
AUDAC_SAMPLE_RATE_24K,
};
/**
* @brief AUDAC irq_flag type
*/
enum audac_irq_flag {
/*!
* @brief:
*
*/
AUDAC_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUDAC_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUDAC ioctl_cmd type
*/
enum audac_ioctl_cmd {
/*!
* @brief:
*
*/
AUDAC_IOCTL_CMD_SET_SAMPLE_RATE,
/*!
* @brief:
*
*/
AUDAC_IOCTL_CMD_SET_SOUND_CHANNEL,
/*!
* @brief: Adjust the power digital gain
*
*/
AUDAC_IOCTL_CMD_SET_DIGITAL_GAIN,
/*!
* @brief: Adjust the power analog gain
*
*/
AUDAC_IOCTL_CMD_SET_ANALOG_GAIN,
/*!
* @brief: Soft mute
*
*/
AUDAC_IOCTL_CMD_SOFT_MUTE,
/*!
* @brief: Change sample rate
* @note :
* 1.Ensure DAC is muted by special method
* 2.You should call "audac_write" API after using this cmd
*
*/
AUDAC_IOCTL_CMD_CHANGE_SAMPLE_RATE,
AUDAC_IOCTL_CMD_GET_DIGITAL_GAIN,
};
/* User interrupt handle */
typedef void (*audac_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUDAC api for user */
struct audac_device {
struct dev_obj dev;
};
struct audac_hal_ops {
struct devobj_ops ops;
int32(*open)(struct audac_device *audac, enum audac_sample_rate sample_rate);
int32(*close)(struct audac_device *audac);
int32(*write)(struct audac_device *audac, void* buf, uint32 bytes);
int32(*ioctl)(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag);
};
/* AUDAC API functions */
/**
* @brief audac_open
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
/**
* @brief audac_close
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_close(struct audac_device *audac);
/**
* @brief audac_write
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_write(struct audac_device *audac, void* buf, uint32 bytes);
/**
* @brief audac_ioctl
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief audac_request_irq
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief audac_release_irq
*
*
* @note .
*
* @param audac The address of audac device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 audac_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/capture.h
+272
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#ifndef _HAL_CAPTURE_H_
#define _HAL_CAPTURE_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief CAPTURE channel type
*/
enum capture_channel {
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_CHANNEL_0,
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_CHANNEL_1,
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_CHANNEL_2,
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_CHANNEL_3,
};
/**
* @brief CAPTURE mode type
*/
enum capture_mode {
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_MODE_RISE,
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_MODE_FALL,
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_MODE_ALL,
};
/**
* @brief CAPTURE irq_flag type
*/
enum capture_irq_flag {
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_IRQ_FLAG_CAPTURE,
/*! Compatible version: V0;
*@ Describe:
*
*/
CAPTURE_IRQ_FLAG_OVERFLOW,
};
/**
* @brief CAPTURE ioctl_cmd type
*/
enum capture_ioctl_cmd {
NONE,
};
/* User interrupt handle */
typedef void (*capture_irq_hdl)(uint32 irq, uint32 irq_data);
/* CAPTURE api for user */
struct capture_device {
struct dev_obj dev;
};
struct capture_hal_ops{
struct devobj_ops ops;
int32(*init)(struct capture_device *cap, enum capture_channel channel, enum capture_mode mode);
int32(*deinit)(struct capture_device *cap, enum capture_channel channel);
int32(*start)(struct capture_device *cap, enum capture_channel channel);
int32(*stop)(struct capture_device *cap, enum capture_channel channel);
int32(*suspend)(struct capture_device *cap, enum capture_channel channel);
int32(*resume)(struct capture_device *cap, enum capture_channel channel);
int32(*ioctl)(struct capture_device *cap, enum capture_channel channel, enum capture_ioctl_cmd cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct capture_device *cap, enum capture_channel channel, enum capture_irq_flag irq_flag, capture_irq_hdl irq_hdl, uint32 data);
int32(*release_irq)(struct capture_device *cap, enum capture_channel channel);
};
/* CAPTURE API functions */
/**
* @brief capture_init
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_init(struct capture_device *capture, enum capture_channel channel, enum capture_mode mode);
/**
* @brief capture_deinit
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_deinit(struct capture_device *capture, enum capture_channel channel);
/**
* @brief capture_start
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_start(struct capture_device *capture, enum capture_channel channel);
/**
* @brief capture_stop
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_stop(struct capture_device *capture, enum capture_channel channel);
/**
* @brief capture_suspend channel
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_suspend(struct capture_device *capture, enum capture_channel channel);
/**
* @brief capture_resume channel
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_resume(struct capture_device *capture, enum capture_channel channel);
/**
* @brief capture_ioctl
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_ioctl(struct capture_device *capture, enum capture_channel channel, enum capture_ioctl_cmd cmd, uint32 param1, uint32 param2);
/**
* @brief capture_request_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_request_irq(struct capture_device *capture, enum capture_channel channel, enum capture_irq_flag irq_flag, capture_irq_hdl irq_hdl, uint32 data);
/**
* @brief capture_release_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param capture The address of capture device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 capture_release_irq(struct capture_device *capture, enum capture_channel channel);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/crc.h
+70
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@@ -0,0 +1,70 @@
#ifndef _HAL_CRC_H_
#define _HAL_CRC_H_
#ifdef __cplusplus
extern "C" {
#endif
enum CRC_DEV_FLAGS {
CRC_DEV_FLAGS_CONTINUE_CALC = BIT(0),
};
enum CRC_DEV_TYPE {
CRC_TYPE_CRC5_USB = 0,
CRC_TYPE_CRC7_MMC,
CRC_TYPE_CRC8_MAXIM,
CRC_TYPE_CRC8,
CRC_TYPE_CRC16,
CRC_TYPE_CRC16_CCITT,
CRC_TYPE_CRC16_MODBUS,
CRC_TYPE_CRC32_WINRAR,
CRC_TYPE_TCPIP_CHKSUM,
CRC_TYPE_MAX,
};
/**
* CRC len 512KB for TXW81x； 64KB for TXW80x
*/
struct crc_dev_req {
uint16 type;
uint16 cookie;
uint8 *data;
uint32 len;
uint32 crc_last; //use when CRC_DEV_FLAGS_CONTINUE_CALC
};
struct crc_dev {
struct dev_obj dev;
};
struct crc_hal_ops{
struct devobj_ops ops;
int32(*calc)(struct crc_dev *dev, struct crc_dev_req *req, uint32 *crc_val, uint32 flags);
};
/**
* @brief Hold CRC .
* @param dev : crc_dev use @ref dev_get() function to get the handle.
* @param req : req(type\addr\len) for crc dev.
* 1、req crc_last must set when flags:CRC_DEV_FLAGS_CONTINUE_CALC
* @param crc_val : crc result.
* @param flags : CRC_DEV_FLAGS .
* @return
* - RET_OK : Successfully.
* - RET_ERR : Failed.
* @note
*/
static inline int32 crc_dev_calc(struct crc_dev *dev, struct crc_dev_req *req, uint32 *crc_val, uint32 flags)
{
const struct crc_hal_ops *ops = (const struct crc_hal_ops *)dev->dev.ops;
return (dev && ops->calc) ? ops->calc(dev, req, crc_val, flags) : RET_ERR;
}
extern uint32 hw_crc(enum CRC_DEV_TYPE type, uint8 *data, uint32 len);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/dma.h
+161
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@@ -0,0 +1,161 @@
#ifndef _HAL_DMA_H_
#define _HAL_DMA_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* enum dma_status - DMA transaction status
* @DMA_SUCCESS: transaction completed successfully
* @DMA_IN_PROGRESS: transaction not yet processed
* @DMA_PAUSED: transaction is paused
* @DMA_ERROR: transaction failed
*/
enum dma_status {
DMA_SUCCESS,
DMA_IN_PROGRESS,
DMA_PAUSED,
DMA_ERROR,
};
enum dma_xfer_direct {
/*! xfer directiont: NONE
*/
DMA_XFER_DIR_NONE,
/*! xfer directiont: memory to memory
*/
DMA_XFER_DIR_M2M,
/*! xfer directiont: memory to device
*/
DMA_XFER_DIR_M2D,
/*! xfer directiont: device to memory
*/
DMA_XFER_DIR_D2M,
/*! xfer directiont: device to device
*/
DMA_XFER_DIR_D2D,
};
enum dma_xfer_mode {
/*! xfer mode: source address increase
*/
DMA_XFER_MODE_INCREASE,
/*! xfer mode: source address recycling
*/
DMA_XFER_MODE_RECYCLE,
/*! xfer mode: source address block copy
*/
DMA_XFER_MODE_BLKCPY,
};
/**
* enum dma_slave_buswidth - defines bus with of the DMA slave
* device, source or target buses
*/
enum dma_slave_buswidth {
DMA_SLAVE_BUSWIDTH_1_BYTE = 0,
DMA_SLAVE_BUSWIDTH_2_BYTES = 1,
DMA_SLAVE_BUSWIDTH_4_BYTES = 2,
DMA_SLAVE_BUSWIDTH_8_BYTES = 3,
DMA_SLAVE_BUSWIDTH_UNDEFINED = 4,
};
enum dma_irq_type {
DMA_IRQ_TYPE_DONE,
DMA_IRQ_TYPE_ERROR,
};
enum dma_endian_type{
DMA_ENDIAN_TYPE_NO_OVERTURN,
DMA_ENDIAN_TYPE_16BIT_OVERTURN,
DMA_ENDIAN_TYPE_32BIT_OVERTURN,
};
enum dma_ioctl_cmd{
DMA_IOCTL_CMD_ENDIAN,
DMA_IOCTL_CMD_CHECK_DMA1_STATUS,
DMA_IOCTL_CMD_DMA1_LOCK,
DMA_IOCTL_CMD_DMA1_UNLOCK,
};
struct dma_device;
typedef void (*dma_irq_hdl)(struct dma_device *p_dma, uint32 ch, enum dma_irq_type irq, uint32 data);
struct dma_xfer_data {
uint32 dest;
uint32 src;
uint32 blk_width : 16,
blk_height : 12,
src_addr_mode : 2, //enum dma_xfer_mode
dst_addr_mode : 2; //enum dma_xfer_mode
uint32 src_width : 12,
dst_width : 12,
src_id : 8;
uint32 dir : 3, //enum dma_xfer_direct
endian : 2,
dst_id : 8,
reserved : 19;
uint32 element_per_width;
uint32 element_num;
uint32 irq_data;
dma_irq_hdl irq_hdl;
};
struct dma_blkcpy_cfg{
uint32 dest;
uint32 src;
uint32 blk_width : 20,
blk_height : 12;
uint32 src_width : 12,
dst_width : 12,
reserved : 8;
};
struct dma_device {
struct dev_obj dev;
};
struct dma_hal_ops{
struct devobj_ops ops;
int32(*pause)(struct dma_device *dma, uint32 ch);
int32(*resume)(struct dma_device *dma, uint32 ch);
int32(*xfer)(struct dma_device *dma, struct dma_xfer_data *data);
int32(*get_status)(struct dma_device *dma, uint32 ch);
int32(*stop)(struct dma_device *dma, uint32 ch);
int32(*ioctl)(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
};
int32 dma_pause(struct dma_device *dma, uint32 ch);
int32 dma_resume(struct dma_device *dma, uint32 ch);
void dma_memcpy(struct dma_device *dma, void *dst, const void *src, uint32 n);
void dma_memset(struct dma_device *dma, void *dst, uint8 c, uint32 n);
void dma_blkcpy(struct dma_device *dma , struct dma_blkcpy_cfg *cfg);
int32 dma_ioctl(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
int32 dma_xfer(struct dma_device *dma, struct dma_xfer_data *data);
int32 dma_status(struct dma_device *dma, uint32 ch);
int32 dma_stop(struct dma_device *dma, uint32 ch);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/dvp.h
+145
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#ifndef HAL_DVP_H
#define HAL_DVP_H
/* User interrupt handle */
typedef int32(*dvp_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
/**
* @brief UART ioctl_cmd type
*/
enum dvp_ioctl_cmd {
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_FORMAT,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_RGB_2_YUV,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_ADR_1,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_ADR_2,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_SCEN,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_HSYNC_VAILD,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_VSYNC_VAILD,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_ONE_SAMPLE,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_DEBOUNCE,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_YCBCR_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_DIS_UV_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_FRAME_RATE,
/*! Compatible version: V2;
*@ Describe:
*
*/
DVP_IOCTL_CMD_SET_THRESHOLD,
DVP_IOCTL_CMD_EX_D5_D6,
DVP_IOCTL_CMD_SET_JPEG_LEN,
};
struct dvp_device {
struct dev_obj dev;
};
struct dvp_hal_ops{
struct devobj_ops ops;
int32(*init)(struct dvp_device *dvp_dev);
int32(*suspend)(struct dvp_device *dvp_dev);
int32(*resume)(struct dvp_device *dvp_dev);
int32(*baudrate)(struct dvp_device *dvp_dev, uint32 baudrate);
int32(*open)(struct dvp_device *dvp_dev);
int32(*close)(struct dvp_device *dvp_dev);
int32(*ioctl)(struct dvp_device *dvp_dev, enum dvp_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct dvp_device *dvp_dev, uint32 irq_flag, dvp_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct dvp_device *dvp_dev, uint32 irq_flag);
};
int32 dvp_open(struct dvp_device *p_dvp);
int32 dvp_close(struct dvp_device *p_dvp);
int32 dvp_suspend(struct dvp_device *p_dvp);
int32 dvp_resume(struct dvp_device *p_dvp);
int32 dvp_init(struct dvp_device *p_dvp);
int32 dvp_set_baudrate(struct dvp_device *p_dvp, uint32 mclk);
int32 dvp_set_size(struct dvp_device *p_dvp, uint32 x_s, uint32 y_s, uint32 x_e, uint32 y_e);
int32 dvp_set_addr1(struct dvp_device *p_dvp, uint32 yuv_addr);
int32 dvp_set_addr2(struct dvp_device *p_dvp, uint32 yuv_addr);
int32 dvp_set_rgb2yuv(struct dvp_device *p_dvp, uint8 en);
int32 dvp_set_format(struct dvp_device *p_dvp, uint8 format);
int32 dvp_set_half_size(struct dvp_device *p_dvp, uint8 en);
int32 dvp_set_vsync_polarity(struct dvp_device *p_dvp, uint8 high_valid);
int32 dvp_set_hsync_polarity(struct dvp_device *p_dvp, uint8 high_valid);
int32 dvp_set_once_sampling(struct dvp_device *p_dvp, uint8 en);
int32 dvp_debounce_enable(struct dvp_device *p_dvp, uint8 en, uint8 pixel);
int32 dvp_set_ycbcr(struct dvp_device *p_dvp, uint8 mode);
int32 dvp_unload_uv(struct dvp_device *p_dvp, uint8 en);
int32 dvp_frame_load_precent(struct dvp_device *p_dvp, uint8 precent);
int32 dvp_low_high_threshold(struct dvp_device *p_dvp, bool low_high);
int32 dvp_jpeg_mode_set_len(struct dvp_device *p_dvp, uint32 len);
int32 dvp_request_irq(struct dvp_device *p_dvp, uint32 irq_flag, dvp_irq_hdl irq_hdl, uint32 irq_data);
int32 dvp_release_irq(struct dvp_device *p_dvp, uint32 irq_flag);
int32 dvp_set_exchange_d5_d6(struct dvp_device *p_dvp, uint8 en);
#endif
sdk/include/hal/gpio.h
+156
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/**
* @file gpio.h
* @author HUGE-IC Application Team
* @brief GPIO HAL driver
* @version 1.0.0
* @date 2021-9-8
*
* @copyright Copyright (c) 2021 HUGE-IC
*/
#ifndef _HAL_GPIO_H_
#define _HAL_GPIO_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enumeration constant for GPIO pin direction select
* @note : this enum must mapping to OS @PinDirection
*/
enum gpio_pin_direction {
/*! Set GPIO to input mode.
*/
GPIO_DIR_INPUT,
/*! Set GPIO to output mode.
*/
GPIO_DIR_OUTPUT,
};
/**
* @breif : enum of GPIO pin mode
* @note : this enum must mapping to OS @PinMode
*/
enum gpio_pin_mode {
/*! gpio mode : push-pull & pull none
*/
GPIO_PULL_NONE,
/*! gpio mode : push-pull & pull up
*/
GPIO_PULL_UP,
/*! gpio mode : push-pull & pull down
*/
GPIO_PULL_DOWN,
/*! gpio mode : open-drain & pull none
*/
GPIO_OPENDRAIN_PULL_NONE,
/*! gpio mode : open-drain & pull up
*/
GPIO_OPENDRAIN_PULL_UP,
/*! Set the GPIO drop open-drain mode to NO.
*/
GPIO_OPENDRAIN_DROP_NONE,
/*! Set the GPIO drop open-drain mode to down mode.
*/
GPIO_OPENDRAIN_DROP_DOWN,
};
/**
* @breif : Enumeration constant for GPIO pin interrupt event.
*/
enum gpio_irq_event {
/*! None interrupt event.
*/
GPIO_IRQ_EVENT_NONE,
/*! Rising interrupt event.
*/
GPIO_IRQ_EVENT_RISE,
/*! Falling interrupt event.
*/
GPIO_IRQ_EVENT_FALL,
/*! Rising and falling interrupt event.
*/
GPIO_IRQ_EVENT_ALL ,
};
/**
* @breif : enum of io control cmd
*/
enum gpio_ioctl_cmd {
/*! switch GPIO input delay on or off
*/
GPIO_INPUT_DELAY_ON_OFF,
/*! Atomic operation in GPIO direction.
*/
GPIO_DIR_ATOMIC,
/*! Atomic operation in GPIO vaule.
*/
GPIO_VALUE_ATOMIC,
/*! LOCK GPIO config exclude I/O DAT register until MCU reset or peripheral reset.
*/
GPIO_LOCK,
/*! GPIO debunce
*/
GPIO_DEBUNCE,
/*! GPIO toggle, use for output data toggle
*/
GPIO_OUTPUT_TOGGLE,
/*! Set GPIO pin to general analog function
*/
GPIO_GENERAL_ANALOG,
GPIO_CMD_SET_IEEN,
};
typedef void (*gpio_irq_hdl)(int32 id, enum gpio_irq_event event);
struct gpio_device {
struct dev_obj dev;
};
struct gpio_hal_ops{
struct devobj_ops ops;
int32(*mode)(struct gpio_device *gpio, uint32 pin, enum gpio_pin_mode mode, enum gpio_pull_level level);
int32(*dir)(struct gpio_device *gpio, uint32 pin, enum gpio_pin_direction direction);
int32(*set)(struct gpio_device *gpio, uint32 pin, int32 val);
int32(*get)(struct gpio_device *gpio, int32 pin);
int32(*request_pin_irq)(struct gpio_device *gpio, uint32 pin, gpio_irq_hdl handler, uint32 data, enum gpio_irq_event evt);
int32(*release_pin_irq)(struct gpio_device *gpio, uint32 pin, enum gpio_irq_event evt);
int32(*ioctl)(struct gpio_device *gpio, uint32 pin, int32 cmd, int32 param1, int32 param2);
};
int32 gpio_set_mode(uint32 pin, enum gpio_pin_mode mode, enum gpio_pull_level level);
int32 gpio_set_dir(uint32 pin, enum gpio_pin_direction direction);
int32 gpio_set_val(uint32 pin, int32 value);
int32 gpio_get_val(uint32 pin);
int32 gpio_request_pin_irq(uint32 pin, gpio_irq_hdl handler, uint32 data, enum gpio_irq_event evt);
int32 gpio_release_pin_irq(uint32 pin, enum gpio_irq_event evt);
int32 gpio_ioctl(uint32 pin, int32 cmd, int32 param1, int32 param2);
extern struct gpio_device *gpio_get(uint32 pin);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/i2c.h
+160
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@@ -0,0 +1,160 @@
/**
******************************************************************************
* @file sdk/include/hal/i2c.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 01-08-2018
* @brief Main program body header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2018 HUGE-IC</center></h2>
*
*
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _HAL_I2C_H_
#define _HAL_I2C_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/** @addtogroup Template_Project
* @{
*/
/**
* @brief Enumeration constant for IIC ioctrl cmd
*/
enum i2c_ioctl_cmd {
/*! IIC SDA output delay
*/
IIC_SDA_OUTPUT_DELAY,
/*! IIC SCL strong output
*@note: I/O cannot be configured when the strong output is on
*/
IIC_STRONG_OUTPUT,
IIC_FILTERING,
IIC_SET_DEVICE_ADDR,
};
/**
* @brief Enumeration constant for IIC mode selection
*/
enum i2c_mode {
/*! IIC selects the master mode.
*/
IIC_MODE_MASTER,
/*! IIC selects the slave mode.
*/
IIC_MODE_SLAVE,
};
/**
* @brief Enumeration constant for IIC address bit selection
*/
enum i2c_addr_mode {
/*! The IIC communication address selects the 7-bit mode.
*/
IIC_ADDR_7BIT,
/*! The IIC communication address selects the 10-bit mode.
*/
IIC_ADDR_10BIT,
};
enum i2c_irq_flag {
/*!
* @brief Interrupt: IIC send data completed.
* @Note
* This interrupt is only used for IIC transmit.
*/
I2C_IRQ_FLAG_TX_DONE = BIT(0),
/*!
* @brief Interrupt: IIC receive data completed.
* @Note:
* This interrupt is only used for IIC receive.
*/
I2C_IRQ_FLAG_RX_DONE = BIT(1),
/*!
* @brief Interrupt: IIC slave nack to IIC master
*/
I2C_IRQ_FLAG_RX_NACK = BIT(2),
/*!
* @brief Interrupt: IIC rececive error
* @Note:
* IIC buf overflow means rx error
*/
I2C_IRQ_FLAG_RX_ERROR = BIT(3),
/*!
* @brief Interrupt: IIC detect stop
* @Note:
* IIC has detected the stop signal on the bus
*/
I2C_IRQ_FLAG_DETECT_STOP = BIT(4),
};
typedef void (*i2c_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param);
struct i2c_device {
struct dev_obj dev;
};
struct i2c_hal_ops{
struct devobj_ops ops;
int32(*open)(struct i2c_device *i2c, enum i2c_mode mode, enum i2c_addr_mode addr_mode, uint32 addr);
int32(*close)(struct i2c_device *i2c);
int32(*ioctl)(struct i2c_device *i2c, int32 cmd, uint32 param);
int32(*baudrate)(struct i2c_device *i2c, uint32 baudrate);
int32(*read)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 len);
int32(*write)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 len);
int32(*write_scatter)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, scatter_data *data, uint32 count);
int32(*request_irq)(struct i2c_device *i2c, i2c_irq_hdl irqhdl, uint32 irq_data, uint32 irq_flag);
int32(*release_irq)(struct i2c_device *i2c, uint32 irq_flag);
};
/**
* @}
*/
/** @defgroup HGI2C_DW_Exported_Functions
* @{
*/
int32 i2c_open(struct i2c_device *i2c, enum i2c_mode mode, enum i2c_addr_mode addr_mode, uint32 addr);
int32 i2c_close(struct i2c_device *i2c);
int32 i2c_set_baudrate(struct i2c_device *i2c, uint32 baudrate);
int32 i2c_ioctl(struct i2c_device *i2c, uint32 cmd, uint32 param);
int32 i2c_read(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len);
int32 i2c_write(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len);
int32 i2c_write_scatter(struct i2c_device *i2c, int8 *addr, uint32 addr_len, scatter_data *data, uint32 count);
int32 i2c_request_irq(struct i2c_device *i2c, i2c_irq_hdl handle, uint32 irq_data, uint32 irq_flag);
int32 i2c_release_irq(struct i2c_device *i2c, uint32 irq_flag);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/i2s.h
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#ifndef _HAL_I2S_H_
#define _HAL_I2S_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief i2s bit width per sample type
*/
enum i2s_sample_bits {
/*! Compatible version: V0
*@Describe:
* i2s bit width per sample: 8bits
*/
I2S_SAMPLE_BITS_8BITS,
/*! Compatible version: V0
*@Describe:
* i2s bit width per sample: 16bits
*/
I2S_SAMPLE_BITS_16BITS,
/*! Compatible version: V0
*@Describe:
* i2s bit width per sample: 24bits
*/
I2S_SAMPLE_BITS_24BITS,
};
/**
* @brief i2s sample frequency type
*/
enum i2s_sample_freq {
I2S_SAMPLE_FREQ_8K,
I2S_SAMPLE_FREQ_16K,
/*! Compatible version: V0
*@Describe:
* i2s sample frequency: 44.1K(WS frequency)
*/
I2S_SAMPLE_FREQ_44_1K,
/*! Compatible version: V0
*@Describe:
* i2s sample frequency: 48K(WS frequency)
*/
I2S_SAMPLE_FREQ_48K,
};
/**
* @brief i2s channel type
*/
enum i2s_channel {
/*! Compatible version: V0
*@Describe:
* i2s mono channel
*/
I2S_CHANNEL_MONO,
/*! Compatible version: V0
*@Describe:
* i2s stereo channel
*/
I2S_CHANNEL_STEREO,
};
/**
* @brief i2s data format type
*/
enum i2s_data_fmt {
/*! Compatible version: V0
*@Describe:
* I2S communication format I2S
*/
I2S_DATA_FMT_I2S,
/*! Compatible version: V0
*@Describe:
* I2S communication format MSB(right justified)
*/
I2S_DATA_FMT_MSB,
/*! Compatible version: V0
*@Describe:
* I2S communication format LSB(left justified)
*/
I2S_DATA_FMT_LSB,
/*! Compatible version: V0
*@Describe:
* I2S communication format PCM
*/
I2S_DATA_FMT_PCM,
};
/**
* @brief i2s mode type
*/
enum i2s_mode {
/*! Compatible version: V0
*@Describe:
* I2S master mode setting
*/
I2S_MODE_MASTER,
/*! Compatible version: V0
*@Describe:
* I2S slave mode setting
*/
I2S_MODE_SLAVE,
};
/**
* @brief spi ioctl cmd
*
*/
enum i2s_ioctl_cmd {
/*! Compatible version: V0
*@Describe:
* Set the polarity of WSCLK
*@The specific Settings:
* (1)left channel WSCLK level is low , right channel WSCLK level is high
* (2)left channel WSCLK level is high, right channel WSCLK level is low
*/
I2S_IOCTL_CMD_SET_WSCLK_POL,
/*! Compatible version: V0
*@Describe:
* i2s bit width per sample
*@The specific Settings:
* (1)I2S_SAMPLE_BITS_8BITS
* (2)I2S_SAMPLE_BITS_16BITS
* (3)I2S_SAMPLE_BITS_24BITS
*/
I2S_IOCTL_CMD_SET_SAMPLE_BITS,
/*! Compatible version: V0
*@Describe:
* i2s bit width per sample
*@The specific Settings:
* (1)I2S_CHANNEL_MONO
* (2)I2S_CHANNEL_STEREO
*/
I2S_IOCTL_CMD_SET_CHANNEL,
/*! Compatible version: V0
*@Describe:
* i2s communication format
*@The specific Settings:
* (1)I2S_DATA_FMT_I2S
* (2)I2S_DATA_FMT_MSB
* (3)I2S_DATA_FMT_LSB
*/
I2S_IOCTL_CMD_SET_DATA_FMT,
/*! Compatible version: V0
*@Describe:
* i2s open WSCLK & BCLK & DATA debounce
* (Only for i2s slave)
*/
I2S_IOCTL_CMD_SET_DEBOUNCE,
/*! Compatible version: V0
*@Describe:
* i2s open duplex using iis0 & iis1
*/
I2S_IOCTL_CMD_SET_DUPLEX,
};
/**
* @brief spi request interrupt flag
*
*/
enum i2s_irq_flag {
/*! Compatible version: V0
*@Describe:
* I2S interrupt signal that transmits half of the data
*/
I2S_IRQ_FLAG_HALF = BIT(0),
/*! Compatible version: V0
*@Describe:
* I2S interrupt signal that transmits all data
*/
I2S_IRQ_FLAG_FULL = BIT(1),
};
/* User interrupt handle */
typedef void (*i2s_irq_hdl)(uint32 irq, uint32 irq_data);
/* I2S api for user */
struct i2s_device {
struct dev_obj dev;
};
struct i2s_hal_ops{
struct devobj_ops ops;
int32(*open)(struct i2s_device *i2s, enum i2s_mode mode, enum i2s_sample_freq frequency, enum i2s_sample_bits bits);
int32(*close)(struct i2s_device *i2s);
int32(*ioctl)(struct i2s_device *i2s, uint32 cmd, uint32 param);
int32(*read)(struct i2s_device *i2s, void *buf, uint32 len);
int32(*write)(struct i2s_device *i2s, const void *buf, uint32 len);
int32(*write_scatter)(struct i2s_device *i2s, const scatter_data *data, uint32 count);
int32(*request_irq)(struct i2s_device *i2s, uint32 irq_flag, i2s_irq_hdl irqhdl, uint32 irq_data);
int32(*release_irq)(struct i2s_device *i2s, uint32 irq_flag);
};
/* I2S API functions */
/**
* @brief i2s_open.
*
* @Compatible version: V0
*
* @note This function must be called before any I2S driver operations.
*
* @param i2s The address of I2S device in the RTOS.
* @param mode I2S work mode setting - see "enum i2s_mode".
* @param frequency I2S sample frequency setting - see "enum i2s_sample_freq".
* @param bits I2S sample bits setting - see "enum i2s_sample_bits".
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 i2s_open(struct i2s_device *i2s, enum i2s_mode mode, enum i2s_sample_freq frequency, enum i2s_sample_bits bits);
/**
* @brief i2s_close.
*
* @Compatible version: V0
*
* @param i2s The address of I2S device in the RTOS.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 i2s_close(struct i2s_device *i2s);
/**
* @brief i2s_write.
*
* @Compatible version: V0
*
* @param i2s The address of I2S device in the RTOS.
* @param buf Write the start address of buf.
* @param len Write length, uint: byte.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 i2s_write(struct i2s_device *i2s, const void *buf, uint32 len);
int32 i2s_write_scatter(struct i2s_device *i2s, const scatter_data *data, uint32 count);
/**
* @brief i2s_read.
*
* @Compatible version: V0
*
* @param i2s The address of I2S device in the RTOS.
* @param buf Read the start address of buf.
* @param len Read length, uint: byte.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 i2s_read(struct i2s_device *i2s, void *buf, uint32 len);
/**
* @brief i2s_ioctl.
*
* @Compatible version: V0
*
* @param i2s The address of I2S device in the RTOS.
* @param cmd Control command - see"enum i2s_ioctl_cmd".
* @param param Parameters required to execute the current Control command.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 i2s_ioctl(struct i2s_device *i2s, uint32 cmd, uint32 param);
/**
* @brief i2s_request_irq.
*
* @Compatible version: V0
*
* @param i2s The address of I2S device in the RTOS.
* @param irq_flag The type of interrupt - see"enum i2s_irq_flag".
* @param irqhdl The interrupt function.
* @param irq_data The parameters of the interrupt function
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 i2s_request_irq(struct i2s_device *i2s, uint32 irq_flag, i2s_irq_hdl irqhdl, uint32 irq_data);
/**
* @brief i2s_release_irq.
*
* @Compatible version: V0
*
* @param i2s The address of I2S device in the RTOS.
* @param irq_flag The type of interrupt - see"enum i2s_irq_flag".
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 i2s_release_irq(struct i2s_device *i2s, uint32 irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/jpeg.h
+79
View File
@@ -0,0 +1,79 @@
#ifndef _HAL_JPEG_H_
#define _HAL_JPEG_H_
enum jpg_device_irq_flag {
JPG_IRQ_FLAG_JPG_DONE = BIT(0),
JPG_IRQ_FLAG_JPG_BUF_FULL = BIT(1),
JPG_IRQ_FLAG_ERROR = BIT(2),
JPG_IRQ_FLAG_PIXEL_DONE = BIT(3),
};
enum jpg_ioctl_cmd {
JPG_IOCTL_CMD_IS_ONLINE,
JPG_IOCTL_CMD_SET_ADR,
JPG_IOCTL_CMD_SET_QT,
JPG_IOCTL_CMD_SET_SIZE,
JPG_IOCTL_CMD_SET_SRC_FROM,
JPG_IOCTL_CMD_UPDATE_QT,
JPG_IOCTL_CMD_DECODE_TAG,
JPG_IOCTL_CMD_OPEN_DBG,
JPG_IOCTL_CMD_SOFT_KICK,
JPG_IOCTL_CMD_HW_CHK,
JPG_IOCTL_CMD_IS_IDLE,
JPG_IOCTL_CMD_SET_INIT_FINISH,
JPG_IOCTL_CMD_GET_INIT_FLAG,
};
typedef int32(*jpg_irq_hdl)(uint32 irq_flag, uint32 irq_data, uint32 param1, uint32 param2);
struct jpg_device {
struct dev_obj dev;
};
struct jpeg_hal_ops{
struct devobj_ops ops;
int32(*open)(struct jpg_device *jpg);
int32(*close)(struct jpg_device *jpg);
int32(*suspend)(struct jpg_device *jpg);
int32(*resume)(struct jpg_device *jpg);
int32(*init)(struct jpg_device *jpg, uint32 table_idx, uint32 qt);
int32(*decode)(struct jpg_device *jpg,uint32 photo);
int32(*ioctl)(struct jpg_device *jpg, enum jpg_ioctl_cmd cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct jpg_device *jpg, jpg_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
int32(*release_irq)(struct jpg_device *jpg, uint32 irq_flag);
};
#ifdef TXW80X
#define JPG_NUM 1
#endif
#ifdef TXW81X
#define JPG_NUM 2
#endif
int32 jpg_open(struct jpg_device *jpg);
int32 jpg_close(struct jpg_device *jpg);
int32 jpg_init(struct jpg_device *jpg, uint32 table_idx, uint32 qt);
int32 jpg_updata_dqt(struct jpg_device *p_jpg, uint32 *dqtbuf);
int32 jpg_suspend(struct jpg_device *jpg);
int32 jpg_resume(struct jpg_device *jpg);
int32 jpg_set_size(struct jpg_device *p_jpg, uint32 h, uint32 w);
int32 jpg_set_addr(struct jpg_device *jpg, uint32 addr, uint32 buflen);
int32 jpg_set_qt(struct jpg_device *jpg, uint32 qt);
int32 jpg_open_debug(struct jpg_device *p_jpg, uint8 enable);
int32 jpg_soft_kick(struct jpg_device *p_jpg, uint8 kick);
int32 jpg_decode_target(struct jpg_device *p_jpg, uint8 to_scaler);
int32 jpg_decode_photo(struct jpg_device *p_jpg, uint32 photo);
int32 jpg_request_irq(struct jpg_device *jpg, jpg_irq_hdl irq_hdl, uint32 irq_flags, void *irq_data);
int32 jpg_release_irq(struct jpg_device *jpg, uint32 irq_flags);
int32 jpg_set_data_from(struct jpg_device *p_jpg, uint8 src_from);
int32 jpg_set_hw_check(struct jpg_device *p_jpg, uint8 enable);
int32 jpg_is_online(struct jpg_device *p_jpg);
int32 jpg_is_idle(struct jpg_device *p_jpg);
int32 jpg_set_init_finish(struct jpg_device *p_jpg,uint32_t value);
int32 jpg_get_init_flag(struct jpg_device *p_jpg);
#endif
sdk/include/hal/lcdc.h
+580
View File
@@ -0,0 +1,580 @@
#ifndef HAL_LCDC_H
#define HAL_LCDC_H
/* User interrupt handle */
typedef int32(*lcdc_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
/**
* @brief UART ioctl_cmd type
*/
enum lcdc_ioctl_cmd {
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_TIMEOUT_INF,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_AUTO_KICK_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_GAMMA_SATURATION_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_GAMMA_SATURATION_VAL,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_CCM_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_COLOR_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_BUS_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_INTERFACE_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_COLRARRAY,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_LCD_VAILD_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_LCD_VISIBLE_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_SIGNAL_CONFIG,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_MCU_SIGNAL_CONFIG,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_INVALID_LINE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_VALID_DOT,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_HLW_VLW,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_VIDEO_BIG_ENDIAN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_VIDEO_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_P0_ROTATE_Y_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_P0_ROTATE_U_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_P0_ROTATE_V_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_P1_ROTATE_Y_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_P1_ROTATE_U_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_P1_ROTATE_V_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_P0P1_ROTATE_START_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_P0_UP,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_P0_P1_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_LINE_BUF_NUM,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_LINE_BUF_Y,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_LINE_BUF_U,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_LINE_BUF_V,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_MIRROR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_ROTATE_SET_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_VIDEO_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_VIDEO_START_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_VIDEO_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_START_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_LUTDMA_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_DMA_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_DMA_LEN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_FORMAT,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_ALPHA,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_ENC_HEAD,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_ENC_DIAP,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_ENC_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_ENC_DST_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_ENC_SRC_LEN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_GET_OSD_ENC_DST_LEN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_OSD_ENC_START,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_MCU_CPU_WRITE,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_MCU_CPU_READ,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_START_RUN,
/*! Compatible version: V2;
*@ Describe:
*
*/
LCDC_SET_TE_EDGE,
/*! Compatible version: V2;
*@ Describe:饱和度使能
*
*/
LCDC_SET_SATURATION_EN,
/*! Compatible version: V2;
*@ Describe:饱和度的值
0x0：0%
0x1：12.5%
0x2：25.0%
0x3：37.5%
0x4：50.0%
0x5：62.5%
0x6：75.0%
0x7：87.5%
0x8：100.0%
0x9：112.5%
0xA：125.0%
0xB：137.5%
0xC：150.0%
0xD：162.5%
0xE：175.0%
0xF：187.5%
0x10：200.0%
*
*/
LCDC_SET_SATURATION_VALUE,
/*! Compatible version: V2;
*@ Describe:对比度使能
*
*/
LCDC_SET_CONSTRAST_EN,
/*! Compatible version: V2;
*@ Describe:对比度的值
0x0：50%
0x1：53.125%
0x2：56.25%
0x3：59.375%
0x4：62.5%
0x5：65.625%
0x6：68.75%
0x7：71.875%
0x8：75.0%
0x9：78.125%
0xA：81.25%
0xB：84.375%
0xC：87.5%
0xD：90.625%
0xE：93.75%
0xF：96.875%
0x10：100%
0x11：103.125%
0x12：106.25%
0x13：109.375%
0x14：112.5%
0x15：115.625%
0x16：118.75%
0x17：121.875%
0x18：125%
0x19：128.125%
0x1A：131.25%
0x1B：134.375%
0x1C：137.5%
0x1D：140.625%
0x1E：143.75%
0x1F：146.875%
*
*/
LCDC_SET_CONSTRAST_VALUE,
/*! Compatible version: V2;
*@ Describe:gamma的使能
*
*/
LCDC_SET_GAMMA_EN,
/*! Compatible version: V2;
*@ Describe:配置GAMMA的rgb索引表
表大小是256byte,只支持sram地址
*
*/
LCDC_SET_GAMMA_R,
LCDC_SET_GAMMA_G,
LCDC_SET_GAMMA_B,
LCDC_SET_CCM_COEF1,
LCDC_SET_CCM_COEF0,
LCDC_SET_CCM_COEF2,
LCDC_SET_CCM_COEF3,
LCDC_GET_CON,
};
enum lcdc_color_mode {
LCD_MODE_565 = 16,
LCD_MODE_666 = 18,
LCD_MODE_888 = 24,
};
enum lcdc_bus_width {
LCD_BUS_WIDTH_6 = 6,
LCD_BUS_WIDTH_8 = 8,
LCD_BUS_WIDTH_9 = 9,
LCD_BUS_WIDTH_12 = 12,
LCD_BUS_WIDTH_16 = 16,
LCD_BUS_WIDTH_18 = 18,
LCD_BUS_WIDTH_24 = 24,
};
enum lcdc_interface_mode {
LCD_BUS_RGB,
LCD_BUS_I80,
LCD_BUS_I68,
};
enum lcdc_rotate_mode {
LCD_ROTATE_0,
LCD_ROTATE_90,
LCD_ROTATE_180,
LCD_ROTATE_270,
};
enum lcdc_video_mode {
VIDEO_FROM_SCALE,
VIDEO_FROM_MEMORY_NO_ROTATE,
VIDEO_FROM_MEMORY_ROTATE,
};
enum lcdc_osd_format {
OSD_RGB_256,
OSD_RGB_565,
OSD_RGB_888,
};
struct lcdc_device {
struct dev_obj dev;
};
struct lcdc_hal_ops {
struct devobj_ops ops;
int32(*init)(struct lcdc_device *lcdc_dev);
int32(*suspend)(struct lcdc_device *lcdc_dev);
int32(*resume)(struct lcdc_device *lcdc_dev);
int32(*baudrate)(struct lcdc_device *lcdc_dev, uint32 baudrate);
int32(*open)(struct lcdc_device *lcdc_dev);
int32(*close)(struct lcdc_device *lcdc_dev);
int32(*ioctl)(struct lcdc_device *lcdc_dev, enum lcdc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct lcdc_device *lcdc_dev, uint32 irq_flag, lcdc_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct lcdc_device *lcdc_dev, uint32 irq_flag);
};
int32 lcdc_init(struct lcdc_device *p_lcdc);
int32 lcdc_open(struct lcdc_device *p_lcdc);
int32 lcdc_close(struct lcdc_device *p_lcdc);
int32 lcdc_request_irq(struct lcdc_device *p_lcdc, uint32 irq_flags, lcdc_irq_hdl irq_hdl, uint32 irq_data);
int32 lcdc_release_irq(struct lcdc_device *p_lcdc, uint32 irq_flags);
int32 lcdc_set_baudrate(struct lcdc_device *p_lcdc, uint32 mclk);
int32 lcdc_set_color_mode(struct lcdc_device *p_lcdc, enum lcdc_color_mode cm);
int32 lcdc_set_bus_width(struct lcdc_device *p_lcdc, enum lcdc_bus_width bw);
int32 lcdc_set_interface(struct lcdc_device *p_lcdc, enum lcdc_interface_mode im);
int32 lcdc_set_colrarray(struct lcdc_device *p_lcdc, uint8 colrarray);
int32 lcdc_set_lcd_vaild_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num);
int32 lcdc_set_lcd_visible_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num);
int32 lcdc_signal_config(struct lcdc_device *p_lcdc, uint8 vs_en,uint8 hs_en,uint8 de_en,uint8 vs_inv,uint8 hs_inv,uint8 de_inv,uint8 clk_inv);
int32 lcdc_mcu_signal_config(struct lcdc_device *p_lcdc, uint8 value);
int32 lcdc_set_invalid_line(struct lcdc_device *p_lcdc, uint8 invalid_line);
int32 lcdc_set_valid_dot(struct lcdc_device *p_lcdc, uint32 w_start,uint32 h_start);
int32 lcdc_set_hlw_vlw(struct lcdc_device *p_lcdc, uint32 hlw,uint32 vlw);
int32 lcdc_set_bigendian(struct lcdc_device *p_lcdc, uint8 en);
int32 lcdc_set_video_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h);
int32 lcdc_set_p0_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
int32 lcdc_set_p0_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
int32 lcdc_set_p0_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
int32 lcdc_set_p1_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
int32 lcdc_set_p1_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
int32 lcdc_set_p1_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
int32 lcdc_set_rotate_p0_up(struct lcdc_device *p_lcdc, uint8 en);
int32 lcdc_set_rotate_p0p1_start_location(struct lcdc_device *p_lcdc, uint32 x0,uint32 y0,uint32 x1,uint32 y1);
int32 lcdc_set_rotate_linebuf_num(struct lcdc_device *p_lcdc, uint32 linebuf);
int32 lcdc_set_rotate_linebuf_y_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
int32 lcdc_set_rotate_linebuf_u_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
int32 lcdc_set_rotate_linebuf_v_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
int32 lcdc_set_rotate_mirror(struct lcdc_device *p_lcdc, uint8 mirror,enum lcdc_rotate_mode rotate);
int32 lcdc_set_rotate_p0p1_size(struct lcdc_device *p_lcdc, uint32 w0,uint32 h0,uint32 w1,uint32 h1);
int32 lcdc_set_video_data_from(struct lcdc_device *p_lcdc, enum lcdc_video_mode vm);
int32 lcdc_set_video_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y);
int32 lcdc_set_video_en(struct lcdc_device *p_lcdc, uint8 en);
int32 lcdc_set_osd_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h);
int32 lcdc_set_osd_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y);
int32 lcdc_set_osd_dma_addr(struct lcdc_device *p_lcdc, uint32 addr);
int32 lcdc_set_osd_lut_addr(struct lcdc_device *p_lcdc, uint32 addr);
int32 lcdc_set_osd_dma_len(struct lcdc_device *p_lcdc, uint32 len);
int32 lcdc_set_osd_format(struct lcdc_device *p_lcdc, enum lcdc_osd_format osd_format);
int32 lcdc_set_osd_alpha(struct lcdc_device *p_lcdc, uint32 alpha);
int32 lcdc_set_osd_enc_head(struct lcdc_device *p_lcdc, uint32 head, uint32 head_tran);
int32 lcdc_set_osd_enc_diap(struct lcdc_device *p_lcdc, uint32 diap, uint32 diap_tran);
int32 lcdc_set_osd_en(struct lcdc_device *p_lcdc, uint8 en);
int32 lcdc_set_osd_enc_src_addr(struct lcdc_device *p_lcdc, uint32 addr);
int32 lcdc_set_osd_enc_dst_addr(struct lcdc_device *p_lcdc, uint32 addr);
int32 lcdc_set_p0p1_enable(struct lcdc_device *p_lcdc, uint8 p0_en,uint8 p1_en);
int32 lcdc_set_osd_enc_src_len(struct lcdc_device *p_lcdc, uint32 len);
int32 lcdc_get_osd_enc_dst_len(struct lcdc_device *p_lcdc);
int32 lcdc_osd_enc_start_run(struct lcdc_device *p_lcdc,uint8_t en);
int32 lcdc_set_start_run(struct lcdc_device *p_lcdc);
int32 lcdc_video_enable_gamma_saturation(struct lcdc_device *p_lcdc, uint8 gamma,uint8 saturation);
int32 lcdc_video_gamma_saturation_val(struct lcdc_device *p_lcdc, uint32 gamma,uint32 saturation);
int32 lcdc_video_enable_ccm(struct lcdc_device *p_lcdc, uint8 ccm);
int32 lcdc_mcu_write_reg(struct lcdc_device *p_lcdc,uint8 data);
int32 lcdc_mcu_write_data(struct lcdc_device *p_lcdc,uint8 data);
int32 lcdc_video_enable_auto_ks(struct lcdc_device *p_lcdc, uint8 enable);
int32 lcdc_set_timeout_info(struct lcdc_device *p_lcdc, uint8 enable,uint8 timeout);
int32 lcdc_mcu_read_data(struct lcdc_device *p_lcdc,uint8 *read_buf,uint8 cmd,uint8 len);
int32 lcdc_set_te_edge(struct lcdc_device *p_lcdc,uint8 edge);
int32 lcdc_video_enable_saturation(struct lcdc_device *p_lcdc, uint8 en);
int32 lcdc_video_set_saturation_val(struct lcdc_device *p_lcdc, uint8 val);
int32 lcdc_video_enable_constarast(struct lcdc_device *p_lcdc, uint8 en);
int32 lcdc_video_set_constarast_val(struct lcdc_device *p_lcdc, uint8 val);
int32 lcdc_video_enable_gamma(struct lcdc_device *p_lcdc, uint8 en);
int32 lcdc_video_set_gamma_R(struct lcdc_device *p_lcdc, uint32 addr);
int32 lcdc_video_set_gamma_G(struct lcdc_device *p_lcdc, uint32 addr);
int32 lcdc_video_set_gamma_B(struct lcdc_device *p_lcdc, uint32 addr);
int32 lcdc_video_set_CCM_COEF0(struct lcdc_device *p_lcdc, uint32 matrix);
int32 lcdc_video_set_CCM_COEF1(struct lcdc_device *p_lcdc, uint32 matrix);
int32 lcdc_video_set_CCM_COEF2(struct lcdc_device *p_lcdc, uint32 matrix);
int32 lcdc_video_set_CCM_COEF3(struct lcdc_device *p_lcdc, uint32 offset);
int32 lcdc_get_con(struct lcdc_device *p_lcdc);
#endif
sdk/include/hal/led.h
+350
View File
@@ -0,0 +1,350 @@
#ifndef _HAL_LED_H_
#define _HAL_LED_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief LED work_mode type
*/
enum led_work_mode {
/*! Compatible version: V0;
*@ Describe:
* Work mode for common anode digital tube
*/
LED_WORK_MODE_COMMON_ANODE,
/*! Compatible version: V0;
*@ Describe:
* Work mode for common cathode digital tube
*/
LED_WORK_MODE_COMMON_CATHODE,
};
/**
* @brief LED seg_cnt type
*/
enum led_seg_cnt {
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 1 piece
*/
LED_SEG_CNT_1,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 2 piece
*/
LED_SEG_CNT_2,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 3 piece
*/
LED_SEG_CNT_3,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 4 piece
*/
LED_SEG_CNT_4,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 5 piece
*/
LED_SEG_CNT_5,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 6 piece
*/
LED_SEG_CNT_6,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 7 piece
*/
LED_SEG_CNT_7,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 8 piece
*/
LED_SEG_CNT_8,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 9 piece
*/
LED_SEG_CNT_9,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 10 piece
*/
LED_SEG_CNT_10,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 11 piece
*/
LED_SEG_CNT_11,
/*! Compatible version: V0;
*@ Describe:
* Amount of segument: 12 piece
*/
LED_SEG_CNT_12,
};
/**
* @brief LED com_cnt type
*/
enum led_com_cnt {
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 1 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_1,
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 2 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_2,
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 3 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_3,
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 4 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_4,
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 5 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_5,
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 6 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_6,
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 7 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_7,
/*! Compatible version: V0;
*@ Describe:
* Amount of com: 8 piece
*@ Note:
* It is also position for "led_open" function's parameter
*/
LED_COM_CNT_8,
};
/**
* @brief LED irq_flag type
*/
enum led_irq_flag {
/*! Compatible version: V0;
*@ Describe:
* emmm...
*/
LED_IRQ_FLAG_INT = BIT(0),
};
/**
* @brief LED ioctl_cmd type
*/
enum led_ioctl_cmd {
/*! Compatible version: V0;
*@ Describe:
* Set scan frequency and set the length of time
*/
LED_IOCTL_CMD_SET_SCAN_FREQ,
};
/* User interrupt handle */
typedef void (*led_irq_hdl)(uint32 irq, uint32 irq_data);
/* LED api for user */
struct led_device {
struct dev_obj dev;
};
struct led_hal_ops{
struct devobj_ops ops;
int32(*open)(struct led_device *led, enum led_work_mode work_mode, enum led_seg_cnt seg_cnt, enum led_com_cnt com_cnt);
int32(*on)(struct led_device *led, uint32 num, enum led_com_cnt pos);
int32(*off)(struct led_device *led, enum led_com_cnt pos);
int32(*close)(struct led_device *led);
int32(*ioctl)(struct led_device *led, enum led_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct led_device *led, enum led_irq_flag irq_flag, led_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct led_device *led, enum led_irq_flag irq_flag);
};
/* LED API functions */
/**
* @brief led_open
*
* @Compatible version: V0;
*
* @note This function must be called before any led driver operations.
*
* @param led The address of led device in the RTOS.
* @param work_mode The tube.work mode setting - see "enum led_work_mode".
* @param seg_cnt The tube's segmument amounts - see "enum led_seg_cnt".
* @param com_cnt The tube's com amounts - see "enum led_com_cnt".
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 led_open(struct led_device *led, enum led_work_mode work_mode, enum led_seg_cnt seg_cnt, enum led_com_cnt com_cnt);
/**
* @brief led_on
*
* @Compatible version: V0;
*
* @note .
*
* @param led The address of led device in the RTOS.
* @param num What does the user want to display the numbers, must be 0~9.
* @param pos Where does the user want to display the numbers - see "enum led_com_cnt".
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 led_on(struct led_device *led, uint32 num, enum led_com_cnt pos);
/**
* @brief led_off
*
* @Compatible version: V0;
*
* @note .
*
* @param led The address of led device in the RTOS.
* @param num What does the user want to display the numbers, must be 0~9.
* @param pos Where does the user want to display the numbers - see "enum led_com_cnt".
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 led_off(struct led_device *led, enum led_com_cnt pos);
/**
* @brief led_close
*
* @Compatible version: V0;
*
* @note .
*
* @param led The address of led device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 led_close(struct led_device *led);
/**
* @brief led_ioctl
*
* @Compatible version: V0;
*
* @note .
*
* @param led The address of led device in the RTOS.
* @param ioctl_cmd The ioctl command - - see "enum led_ioctl_cmd".
* @param param1 The parameter to function.
* @param param2 The parameter to function.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 led_ioctl(struct led_device *led, enum led_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief led_request_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param led The address of led device in the RTOS.
* @param irq_flag The type of interrupt - see"enum led_irq_flag".
* @param irqhdl The interrupt function.
* @param irq_data The parameter of the interrupt function
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 led_request_irq(struct led_device *led, enum led_irq_flag irq_flag, led_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief led_release_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param led The address of led device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 led_release_irq(struct led_device *led, enum led_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/netdev.h
+82
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@@ -0,0 +1,82 @@
#ifndef _HAL_NETDEVICE_H_
#define _HAL_NETDEVICE_H_
#ifdef __cplusplus
extern "C" {
#endif
enum netdev_events {
NETDEV_EVT_LINK_STATUS_CHANGE,
};
enum netdev_link_status {
LINK_DOWN,
LINK_OK,
};
enum netdev_phy_event {
NETDEV_PHY_EVENT_LINK_CHANGED,
};
enum netdev_ioctl_cmd {
NETDEV_IOCTL_GET_ADDR,
NETDEV_IOCTL_SET_ADDR,
NETDEV_IOCTL_GET_LINK_STATUS,
NETDEV_IOCTL_GET_LINK_SPEED,
NETDEV_IOCTL_FORCE_LINK,
NETDEV_IOCTL_SET_FILTER_MAC,
NETDEV_IOCTL_SET_WIFI_MODE,
NETDEV_IOCTL_HOOK_INPUTDATA,
NETDEV_IOCTL_ENABLE_WIFIBRIDGE,
NETDEV_IOCTL_ENABLE_ICMPMNTR,
NETDEV_IOCTL_CLEAR_ROUTETBL,
};
struct netdev;
typedef void (*netdev_input_cb)(struct netdev *ndev, uint8 *data, uint32 size, void *priv);
typedef void (*netdev_event_cb)(struct netdev *ndev, uint32 event, uint32 param);
struct netdev {
struct dev_obj dev;
void *stack_data;
uint64 rx_bytes, tx_bytes;
};
struct netdev_hal_ops {
struct devobj_ops ops;
int32(*open)(struct netdev *ndev, netdev_input_cb input_cb, netdev_event_cb evt_cb, void *priv);
int32(*close)(struct netdev *ndev);
int32(*ioctl)(struct netdev *ndev, uint32 cmd, uint32 param1, uint32 param2);
int32(*send_data)(struct netdev *ndev, uint8 *p_data, uint32 size);
int32(*send_scatter_data)(struct netdev *ndev, scatter_data *data, uint32 count);
void (*phy_event)(void *phydev, uint32 event, uint32 param1, uint32 param2);
void (*mdio_write)(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr, uint16 data);
int32(*mdio_read)(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr);
};
int32 netdev_open(struct netdev *ndev, netdev_input_cb input_cb, netdev_event_cb evt_cb, void *priv);
int32 netdev_close(struct netdev *ndev);
int32 netdev_send_data(struct netdev *ndev, uint8 *p_data, uint32 size);
int32 netdev_send_scatter_data(struct netdev *ndev, scatter_data *p_data, uint32 count);
int32 netdev_ioctl(struct netdev *ndev, uint32 cmd, uint32 param1, uint32 param2);
void netdev_mdio_write(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr, uint16 data);
int32 netdev_mdio_read(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr);
#define netdev_link_speed(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_GET_LINK_SPEED, 0, 0)
#define netdev_link_status(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_GET_LINK_STATUS, 0, 0)
#define netdev_set_macaddr(ndev, addr) netdev_ioctl(ndev, NETDEV_IOCTL_SET_ADDR, (uint32)addr, 0)
#define netdev_get_macaddr(ndev, addr) netdev_ioctl(ndev, NETDEV_IOCTL_GET_ADDR, (uint32)addr, 0)
#define netdev_force_link(ndev, link_speed, duplex_flag) netdev_ioctl(ndev, NETDEV_IOCTL_FORCE_LINK, link_speed, duplex_flag)
#define netdev_set_filter_mac(ndev, mac_table, size) netdev_ioctl(ndev, NETDEV_IOCTL_SET_FILTER_MAC, (uint32)mac_table, (uint32)size)
#define netdev_set_wifi_mode(ndev, mode) netdev_ioctl(ndev, NETDEV_IOCTL_SET_WIFI_MODE, mode, 0)
#define netdev_hook_inputdata(ndev, data, len) netdev_ioctl(ndev, NETDEV_IOCTL_HOOK_INPUTDATA, data, len)
#define netdev_set_wifi_bridge(ndev, en) netdev_ioctl(ndev, NETDEV_IOCTL_ENABLE_WIFIBRIDGE, en, 0)
#define netdev_clear_routetbl(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_CLEAR_ROUTETBL, 0, 0)
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/of.h
+48
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@@ -0,0 +1,48 @@
#ifndef HAL_OF_H
#define HAL_OF_H
enum of_instr_mode {
CUSADA8_INIT_ZERO,
CUSADA8_INIT_ACC,
CUHADD8_AVG,
};
enum of_ioctl_cmd {
/*! Compatible version: V2;
*@ Describe:
*
*/
OF_INSTR_MODE,
CAL_PIXEL_NUM,
CAL_ROW_NUM,
SET_ROW_SIZE,
SET_OF_ADDR,
GET_CAL_ACC,
};
struct of_device {
struct dev_obj dev;
};
struct of_hal_ops {
struct devobj_ops ops;
int32(*init)(struct of_device *of_dev);
int32(*ioctl)(struct of_device *of_dev, enum of_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
int32 of_init(struct of_device *p_of);
int32 of_set_instr_mode(struct of_device *p_of,enum of_instr_mode instr_format);
int32 of_set_pixel_num(struct of_device *p_of,uint32 pixel_num);
int32 of_set_row_num(struct of_device *p_of,uint32 row_num);
int32 of_set_row_size(struct of_device *p_of,uint32 row_size);
int32 of_set_addr(struct of_device *p_of,uint32 addr0,uint32 addr1);
int32 of_get_acc(struct of_device *p_of);
#endif
sdk/include/hal/pdm.h
+198
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@@ -0,0 +1,198 @@
#ifndef _HAL_PDM_H_
#define _HAL_PDM_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief pdm sample frequency type
*/
enum pdm_sample_freq {
/*! Compatible version: V0
*@Describe:
* pdm sample frequency: 8K
*/
PDM_SAMPLE_FREQ_8K,
/*! Compatible version: V0
*@Describe:
* pdm sample frequency: 16K
*/
PDM_SAMPLE_FREQ_16K,
/*! Compatible version: V0
*@Describe:
* pdm sample frequency: 32K
*/
PDM_SAMPLE_FREQ_32K,
/*! Compatible version: V0
*@Describe:
* pdm sample frequency: 48K
*/
PDM_SAMPLE_FREQ_48K,
};
/**
* @brief pdm channel of working mode type
*/
enum pdm_channel {
/*! Compatible version: V0
*@Describe:
* channel of working mode: left channel
*/
PDM_CHANNEL_LEFT,
/*! Compatible version: V0
*@Describe:
* channel of working mode: right channel
*/
PDM_CHANNEL_RIGHT,
/*! Compatible version: V0
*@Describe:
* channel of working mode: stereo channel
*/
PDM_CHANNEL_STEREO,
};
/**
* @brief pdm interrupt type
*/
enum pdm_irq_flag {
/*! Compatible version: V0
*@Describe:
* pdm module receive data half of buf len
*/
PDM_IRQ_FLAG_DMA_HF = BIT(0),
/*! Compatible version: V0
*@Describe:
* pdm module receive data full of buf len
*/
PDM_IRQ_FLAG_DMA_OV = BIT(1),
};
/**
* @brief pdm ioctl cmd
*/
enum pdm_ioctl_cmd {
/*! Compatible version: V0
*@Describe:
* Left and right channels interchange
*/
PDM_IOCTL_CMD_LR_CHANNEL_INTERCHANGE,
};
/* User interrupt handle */
typedef void (*pdm_irq_hdl)(uint32 irq, uint32 irq_data);
/* PDM api for user */
struct pdm_device {
struct dev_obj dev;
};
struct pdm_hal_ops{
struct devobj_ops ops;
int32 (*open )(struct pdm_device *pdm, enum pdm_sample_freq freq, enum pdm_channel channel);
int32 (*read )(struct pdm_device *pdm, void *buf, uint32 len);
int32 (*close )(struct pdm_device *pdm);
int32 (*request_irq)(struct pdm_device *pdm, enum pdm_irq_flag, pdm_irq_hdl irq_hdl, uint32 data);
int32 (*release_irq)(struct pdm_device *pdm, enum pdm_irq_flag irq_flag);
int32 (*ioctl )(struct pdm_device *pdm, enum pdm_ioctl_cmd cmd, uint32 param);
};
/* PDM API functions */
/**
* @brief pdm_open
*
* @Compatible version: V0
*
* @note This function must be called before any pdm driver operations.
*
* @param pdm The address of pdm device in the RTOS.
* @param freq PDM sample frequency setting - see "enum pdm_sample_freq".
* @param channel PDM channel of working mode setting - see "enum pdm_channel".
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pdm_open(struct pdm_device *pdm, enum pdm_sample_freq freq, enum pdm_channel channel);
/**
* @brief pdm_read
*
* @Compatible version: V0
*
* @note Turn PDM module on.
*
* @param pdm The address of pdm device in the RTOS.
* @param buf The pointer of receive buf.
* @param channel PDM module receive length.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pdm_read(struct pdm_device *pdm, void *buf, uint32 len);
/**
* @brief pdm_close
*
* @Compatible version: V0
*
* @note Turn PDM module off.
*
* @param pdm The address of pdm device in the RTOS.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pdm_close(struct pdm_device *pdm);
/**
* @brief pdm_request_irq.
*
* @Compatible version: V0
*
* @param pdm The address of PDM device in the RTOS.
* @param irq_flag The type of interrupt - see"enum pdm_irq_flag".
* @param irqhdl The interrupt function.
* @param irq_data The parameters of the interrupt function
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pdm_request_irq(struct pdm_device *pdm, enum pdm_irq_flag flag, pdm_irq_hdl irq_hdl, uint32 data);
/**
* @brief pdm_release_irq.
*
* @Compatible version: V0
*
* @param pdm The address of PDM device in the RTOS.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pdm_release_irq(struct pdm_device *pdm, enum pdm_irq_flag irq_flag);
/**
* @brief pdm_ioctl.
*
* @Compatible version: V0
*
* @param pdm The address of PDM device in the RTOS.
* @param cmd Control command - see"enum pdm_ioctl_cmd".
* @param param Parameters required to execute the current Control command.
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pdm_ioctl(struct pdm_device *pdm, enum pdm_ioctl_cmd cmd, uint32 param);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/prc.h
+86
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@@ -0,0 +1,86 @@
#ifndef HAL_PRC_H
#define HAL_PRC_H
/* User interrupt handle */
typedef int32(*prc_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
/**
* @brief UART ioctl_cmd type
*/
enum prc_ioctl_cmd {
/*! Compatible version: V2;
*@ Describe:
*
*/
PRC_IOCTL_CMD_SET_WIDTH,
/*! Compatible version: V2;
*@ Describe:
*
*/
PRC_IOCTL_CMD_SET_YUV_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
PRC_IOCTL_CMD_SET_Y_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
PRC_IOCTL_CMD_SET_U_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
PRC_IOCTL_CMD_SET_V_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
PRC_IOCTL_CMD_SET_SRC_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
PRC_IOCTL_CMD_KICK,
};
struct prc_device {
struct dev_obj dev;
};
struct prc_hal_ops {
struct devobj_ops ops;
int32(*init)(struct prc_device *prc_dev);
int32(*suspend)(struct prc_device *prc_dev);
int32(*resume)(struct prc_device *prc_dev);
int32(*ioctl)(struct prc_device *prc_dev, enum prc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct prc_device *prc_dev, uint32 irq_flag, prc_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct prc_device *prc_dev, uint32 irq_flag);
};
int32 prc_suspend(struct prc_device *p_prc);
int32 prc_resume(struct prc_device *p_prc);
int32 prc_set_width(struct prc_device *p_prc, uint32 width);
int32 prc_set_yuv_mode(struct prc_device *p_prc, uint32 mode);
int32 prc_set_yaddr(struct prc_device *p_prc, uint32 addr);
int32 prc_set_uaddr(struct prc_device *p_prc, uint32 addr);
int32 prc_set_vaddr(struct prc_device *p_prc, uint32 addr);
int32 prc_set_src_addr(struct prc_device *p_prc, uint32 addr);
int32 prc_run(struct prc_device *p_prc);
int32 prc_init(struct prc_device *p_prc);
int32 prc_request_irq(struct prc_device *p_prc, uint32 irq_flags, prc_irq_hdl irq_hdl, uint32 irq_data);
int32 prc_release_irq(struct prc_device *p_prc, uint32 irq_flags);
#endif
sdk/include/hal/pwm.h
+294
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@@ -0,0 +1,294 @@
#ifndef _HAL_PWM_H_
#define _HAL_PWM_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief PWM channel type
*/
enum pwm_channel {
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_CHANNEL_0,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_CHANNEL_1,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_CHANNEL_2,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_CHANNEL_3,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_CHANNEL_4,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_CHANNEL_5,
};
/**
* @brief PWM irq_flag type
*/
enum pwm_irq_flag {
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_IRQ_FLAG_COMPARE,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_IRQ_FLAG_PERIOD,
};
/**
* @brief PWM ioctl_cmd type
*/
enum pwm_ioctl_cmd {
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_IOCTL_CMD_SET_PERIOD_DUTY,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_IOCTL_CMD_SET_SINGLE_INCREAM,
/*! Compatible version: V0;
*@ Describe:
*
*/
PWM_IOCTL_CMD_SET_INCREAM_DECREASE,
/*!
* @brief: Set prescaler
* @note:
* 0x0：1/1
* 0x1：1/2
* 0x2：1/4
* 0x3：1/8
* 0x4：1/16
* 0x5：1/32
* 0x6：1/64
* 0x7：1/128
*/
PWM_IOCTL_CMD_SET_PRESCALER,
/*!
* @brief: Configure period and duty immediately
*/
PWM_IOCTL_CMD_SET_PERIOD_DUTY_IMMEDIATELY,
};
/* User interrupt handle */
typedef void (*pwm_irq_hdl)(uint32 irq, uint32 irq_data);
/* PWM api for user */
struct pwm_device {
struct dev_obj dev;
};
struct pwm_hal_ops{
struct devobj_ops ops;
int32(*init)(struct pwm_device *pwm, enum pwm_channel channel, uint32 period_sysclkpd_cnt, uint32 h_duty_sysclkpd_cnt);
int32(*deinit)(struct pwm_device *pwm, enum pwm_channel channel);
int32(*start)(struct pwm_device *pwm, enum pwm_channel channel);
int32(*stop)(struct pwm_device *pwm, enum pwm_channel channel);
int32(*suspend)(struct pwm_device *pwm, enum pwm_channel channel);
int32(*resume)(struct pwm_device *pwm, enum pwm_channel channel);
int32(*ioctl)(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_irq_flag irq_flag, pwm_irq_hdl irq_hdl, uint32 data);
int32(*release_irq)(struct pwm_device *pwm, enum pwm_channel channel);
};
/* PWM API functions */
/**
* @brief pwm_init
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_init(struct pwm_device *pwm, enum pwm_channel channel, uint32 period_sysclkpd_cnt, uint32 h_duty_sysclkpd_cnt);
/**
* @brief pwm_deinit
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_deinit(struct pwm_device *pwm, enum pwm_channel channel);
/**
* @brief pwm_start
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_start(struct pwm_device *pwm, enum pwm_channel channel);
/**
* @brief pwm_stop
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_stop(struct pwm_device *pwm, enum pwm_channel channel);
/**
* @brief pwm_suspend channel
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_suspend(struct pwm_device *pwm, enum pwm_channel channel);
/**
* @brief pwm_resume channel
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_resume(struct pwm_device *pwm, enum pwm_channel channel);
/**
* @brief pwm_ioctl
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_ioctl(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief pwm_request_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_request_irq(struct pwm_device *pwm, enum pwm_channel channel, enum pwm_irq_flag irq_flag, pwm_irq_hdl irq_hdl, uint32 data);
/**
* @brief pwm_release_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param pwm The address of pwm device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 pwm_release_irq(struct pwm_device *pwm, enum pwm_channel channel);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/rtc.h
+203
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@@ -0,0 +1,203 @@
#ifndef _RTC_H
#define _RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief RTC week type
*/
enum rtc_week_type {
MONDAY = 1,
TUESDAY = 2,
WEDNESDAY = 3,
THURSDAY = 4,
FRIDAY = 5,
SATURDAY = 6,
SUNDAY = 0,
};
/**
* @brief RTC time type
*/
struct rtc_time_type {
uint16 year;
uint8 month;
uint8 date;
uint8 week;
uint8 hour;
uint8 minute;
uint8 second;
};
/**
* @brief RTC ioctl_cmd type
*/
enum rtc_ioctl_cmd {
RES,
};
/**
* @brief RTC irq_flag type
*/
enum rtc_irq_flag {
/*! Compatible version: V0;
*@ Describe:
*
*/
RTC_IRQ_FLAG_SECOND = BIT(0),
};
/* User interrupt handle */
typedef void (*rtc_irq_hdl)(uint32 irq, uint32 irq_data);
/* RTC api for user */
struct rtc_device {
struct dev_obj dev;
};
struct rtc_hal_ops{
struct devobj_ops ops;
int32(*open)(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
int32(*close)(struct rtc_device *rtc);
int32(*set_time)(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
int32(*get_time)(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
int32(*ioctl)(struct rtc_device *rtc, uint32 cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct rtc_device *rtc, uint32 irq_flag, rtc_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct rtc_device *rtc, uint32 irq_flag);
};
/* RTC API functions */
/**
* @brief rtc_open
*
* @Compatible version: V0;
*
* @note .
*
* @param rtc The address of rtc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 rtc_open(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
/**
* @brief rtc_close
*
* @Compatible version: V0;
*
* @note .
*
* @param rtc The address of rtc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 rtc_close(struct rtc_device *rtc);
/**
* @brief rtc_set_time
*
* @Compatible version: V0;
*
* @note .
*
* @param rtc The address of rtc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 rtc_set_time(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
/**
* @brief rtc_get_time
*
* @Compatible version: V0;
*
* @note .
*
* @param rtc The address of rtc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 rtc_get_time(struct rtc_device *rtc, struct rtc_time_type *rtc_time);
/**
* @brief rtc_ioctl
*
* @Compatible version: V0;
*
* @note .
*
* @param rtc The address of rtc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 rtc_ioctl(struct rtc_device *rtc, uint32 cmd, uint32 param1, uint32 param2);
/**
* @brief rtc_request_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param rtc The address of rtc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 rtc_request_irq(struct rtc_device *rtc, uint32 irq_flag, rtc_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief rtc_release_irq
*
* @Compatible version: V0;
*
* @note .
*
* @param rtc The address of rtc device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 rtc_release_irq(struct rtc_device *rtc, uint32 irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/scale.h
+175
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@@ -0,0 +1,175 @@
#ifndef HAL_SCALE_H
#define HAL_SCALE_H
/* User interrupt handle */
typedef int32(*scale_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
enum scale_ioctl_cmd {
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_IN_OUT_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_STEP,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_START_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_SRAMBUF_WLEN,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_IN_Y_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_IN_U_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_IN_V_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_OUT_Y_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_OUT_U_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_OUT_V_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_LINE_BUF_NUM,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_SRAM_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_DMA_TO_MEMORY,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_DATA_FROM,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_GET_INBUF_NUM,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_INBUF_NUM,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_HIGH_NUM,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_NEW_FRAME,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_SET_END_FRAME,
/*! Compatible version: V2;
*@ Describe:
*
*/
SCALE_IOCTL_CMD_GET_HEIGH_CNT,
};
struct scale_device {
struct dev_obj dev;
};
struct scale_hal_ops{
struct devobj_ops ops;
int32(*open)(struct scale_device *scale_dev);
int32(*suspend)(struct scale_device *scale_dev);
int32(*resume)(struct scale_device *scale_dev);
int32(*close)(struct scale_device *scale_dev);
int32(*ioctl)(struct scale_device *scale_dev, enum scale_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct scale_device *scale_dev, uint32 irq_flag, scale_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct scale_device *scale_dev, uint32 irq_flag);
};
int32 scale_open(struct scale_device *p_scale);
int32 scale_close(struct scale_device *p_scale);
int32 scale_suspend(struct scale_device *p_scale);
int32 scale_resume(struct scale_device *p_scale);
int32 scale_request_irq(struct scale_device *p_scale, uint32 irq_flags, scale_irq_hdl irq_hdl, uint32 irq_data);
int32 scale_release_irq(struct scale_device *p_scale, uint32 irq_flags);
int32 scale_set_in_out_size(struct scale_device *p_scale, uint32 s_w,uint32 s_h,uint32 o_w,uint32 o_h);
int32 scale_set_step(struct scale_device *p_scale, uint32 s_w,uint32 s_h,uint32 o_w,uint32 o_h);
int32 scale_set_start_addr(struct scale_device *p_scale, uint32 s_x,uint32 s_y);
int32 scale_set_srambuf_wlen(struct scale_device *p_scale, uint32 wlen);
int32 scale_set_in_yaddr(struct scale_device *p_scale, uint32 yaddr);
int32 scale_set_in_uaddr(struct scale_device *p_scale, uint32 uaddr);
int32 scale_set_in_vaddr(struct scale_device *p_scale, uint32 vaddr);
int32 scale_set_out_yaddr(struct scale_device *p_scale, uint32 yaddr);
int32 scale_set_out_uaddr(struct scale_device *p_scale, uint32 uaddr);
int32 scale_set_out_vaddr(struct scale_device *p_scale, uint32 vaddr);
int32 scale_set_line_buf_num(struct scale_device *p_scale, uint32 num);
int32 scale_set_line_buf_addr(struct scale_device *p_scale, uint32 addr);
int32 scale_set_dma_to_memory(struct scale_device *p_scale, uint32 en);
int32 scale_set_data_from_vpp(struct scale_device *p_scale, uint32 en);
int32 scale_get_inbuf_num(struct scale_device *p_scale);
int32 scale_set_inbuf_num(struct scale_device *p_scale,uint32 num,uint32 start_line);
int32 scale_set_new_frame(struct scale_device *p_scale,uint8 en);
int32 scale_set_end_frame(struct scale_device *p_scale,uint8 en);
int32 scale_get_heigh_cnt(struct scale_device *p_scale);
#endif
sdk/include/hal/sdio_slave.h
+68
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@@ -0,0 +1,68 @@
#ifndef _HAL_SDIO_SLAVE_H_
#define _HAL_SDIO_SLAVE_H_
#ifdef __cplusplus
extern "C" {
#endif
enum sdio_slave_flags {
SDIO_SLAVE_FLAG_4BIT = BIT(0),
};
enum sdio_slave_speed {
SDIO_SLAVE_SPEED_1M,
SDIO_SLAVE_SPEED_2M,
SDIO_SLAVE_SPEED_4M,
SDIO_SLAVE_SPEED_8M,
SDIO_SLAVE_SPEED_12M,
SDIO_SLAVE_SPEED_24M,
SDIO_SLAVE_SPEED_48M,
SDIO_SLAVE_SPEED_NUM,
};
enum sdio_slave_irqs {
SDIO_SLAVE_IRQ_RX,
SDIO_SLAVE_IRQ_RX_OVERFLOW,
SDIO_SLAVE_IRQ_RX_CRC_ERR,
SDIO_SLAVE_IRQ_TX_DONE,
SDIO_SLAVE_IRQ_TX_ERR,
SDIO_SLAVE_IRQ_RESET,
};
enum sdio_slave_ioctl_cmd {
SDIO_SLAVE_IO_CMD_SET_USER_REG0,
SDIO_SLAVE_IO_CMD_SET_USER_REG1,
SDIO_SLAVE_IO_CMD_SET_USER_REG2,
};
typedef void (*sdio_slave_irq_hdl)(uint32 irq, uint32 param1, uint32 param2, uint32 param3);
struct sdio_slave {
struct dev_obj dev;
};
struct sdios_hal_ops{
struct devobj_ops ops;
int32(*open)(struct sdio_slave *slave, enum sdio_slave_speed speed, uint32 flags);
int32(*close)(struct sdio_slave *slave);
int32(*ioctl)(struct sdio_slave *slave, int32 cmd, uint32 param);
int32(*read)(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
int32(*write)(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
int32(*write_scatter)(struct sdio_slave *slave, scatter_data *data, uint32 count, int8 sync);
int32(*request_irq)(struct sdio_slave *slave, sdio_slave_irq_hdl irqhdl, uint32 data);
};
int32 sdio_slave_open(struct sdio_slave *slave, enum sdio_slave_speed speed, uint32 flags);
int32 sdio_slave_close(struct sdio_slave *slave);
int32 sdio_slave_write(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
int32 sdio_slave_write_scatter(struct sdio_slave *slave, scatter_data *data, uint32 count, int8 sync);
int32 sdio_slave_read(struct sdio_slave *slave, uint8 *buff, uint32 len, int8 sync);
int32 sdio_slave_ioctl(struct sdio_slave *slave, uint32 cmd, uint32 param);
int32 sdio_slave_request_irq(struct sdio_slave *slave, sdio_slave_irq_hdl handle, uint32 data);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/sha.h
+67
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@@ -0,0 +1,67 @@
#ifndef _HAL_SHA_H_
#define _HAL_SHA_H_
struct sha_dev
{
struct dev_obj dev;
};
enum SHA_CALC_FLAGS{
SHA_CALC_LAST_DATA = 0x01,
SHA_CALC_SHA256 = 0x02,
SHA_CALC_SHA384 = 0x04,
SHA_CALC_SHA512 = 0x08,
};
enum SHA_TYPE {
SHA_SHA256 = 0x01,
SHA_SHA384 = 0x02,
SHA_SHA512 = 0x04,
};
struct sha_desc{
void *state;
uint32 type;
};
struct sha256_state {
uint8 buf[64];
uint32 cnt;
uint8 output[32];
};
enum sha_ioctl_cmd {
SHA_IOCTL_CMD_START,
SHA_IOCTL_CMD_END,
SHA_IOCTL_CMD_RESET,
};
struct sha_hal_ops
{
struct devobj_ops ops;
int32 (*calc)(struct sha_dev *dev, uint8 input[], uint32 len, enum SHA_CALC_FLAGS flags);
int32 (*read)(struct sha_dev *dev, uint8 output[], uint32 timeout);
int32 (*ioctl)(struct sha_dev *dev, uint32 cmd, uint32 para);
int32 (*requset_irq)(struct sha_dev *dev, void *irq_handle, void *args);
int32 (*release_irq)(struct sha_dev *dev);
};
/*
使用cache_clean去确保input对应的数据总是最新的
sha_calc和sha_read已经淘汰了，请使用init->update*n->final
*/
int32 sha_calc(struct sha_dev *dev, uint8 input[], uint32 len, enum SHA_CALC_FLAGS flags);
int32 sha_read(struct sha_dev *dev, uint8 output[], uint32 timeout);
int32 sha_ioctl(struct sha_dev *dev, uint32 cmd, uint32 para);
int32 sha_init(struct sha_dev *dev, enum SHA_CALC_FLAGS flags);
int32 sha_update(struct sha_dev *dev, uint8 *input, uint32 len);
int32 sha_final(struct sha_dev *dev, uint8 *output);
int32 sha_requset_irq(struct sha_dev *dev, void *irq_handle, void *args);
int32 sha_release_irq(struct sha_dev *dev);
#endif
sdk/include/hal/spi.h
+331
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@@ -0,0 +1,331 @@
#ifndef _HAL_SPI_H_
#define _HAL_SPI_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief spi working mode type
*/
enum spi_work_mode {
/*! Compatible version: V0; V1; V2
*@Describe:
* The host mode of SPI
*/
SPI_MASTER_MODE,
/*! Compatible version: V0; V1; V2
*@Describe:
* The slave mode of SPI
*/
SPI_SLAVE_MODE,
/*! Compatible version: V1
*@Describe:
* The slave FSM mode of SPI0, only for spi0
*/
SPI_SLAVE_FSM_MODE,
};
/**
* @brief spi wire mode
*/
enum spi_wire_mode {
/*! Compatible version: V0; V1; V2
*@Describe:
* The wire_single_mode of SPI, contain: CLK; CS; IO0
* A CLK transmits 1bit of data
*/
SPI_WIRE_SINGLE_MODE,
/*! Compatible version: V0; V1; V2
*@Describe:
* The wire_normal_mode of SPI, contain: CLK; CS; IO0; IO1
* A CLK transmits 1bit of data
*/
SPI_WIRE_NORMAL_MODE,
/*! Compatible version: V0; V1
*@Describe:
* The wire_normal_mode of SPI, contain: CLK; CS; IO0; IO1
* A CLK transmits 2bit of data
*/
SPI_WIRE_DUAL_MODE,
/*! Compatible version: V0; V1
*@Describe:
* The wire_normal_mode of SPI, contain: CLK; CS; IO0; IO1; IO2; IO3
* A CLK transmits 4bit of data
*/
SPI_WIRE_QUAD_MODE,
};
/**
* @brief spi clock mode
*/
enum spi_clk_mode {
/*! Compatible version: V0; V1; V2
*@Describe:
* Inactive state of serial clock is low, serial clock toggles in middle of first data bit
*/
SPI_CPOL_0_CPHA_0 = 0,
/*! Compatible version: V0; V1; V2
*@Describe:
* Inactive state of serial clock is low, serial clock toggles at start of first data bit
*/
SPI_CPOL_0_CPHA_1 = 1,
/*! Compatible version: V0; V1; V2
*@Describe:
* Inactive state of serial clock is high, serial clock toggles in middle of first data bit
*/
SPI_CPOL_1_CPHA_0 = 2,
/*! Compatible version: V0; V1; V2
*@Describe:
* Inactive state of serial clock is high, serial clock toggles at start of first data bit
*/
SPI_CPOL_1_CPHA_1 = 3,
SPI_CLK_MODE_0 = SPI_CPOL_0_CPHA_0, /*!< Equal to \ref SPI_CPOL_0_CPHA_0 */
SPI_CLK_MODE_1 = SPI_CPOL_0_CPHA_1, /*!< Equal to \ref SPI_CPOL_0_CPHA_1 */
SPI_CLK_MODE_2 = SPI_CPOL_1_CPHA_0, /*!< Equal to \ref SPI_CPOL_1_CPHA_0 */
SPI_CLK_MODE_3 = SPI_CPOL_1_CPHA_1 /*!< Equal to \ref SPI_CPOL_1_CPHA_1 */
};
/**
* @brief spi ioctl cmd
*
*/
enum spi_ioctl_cmd {
/*! Compatible version: V0; V1
*@Describe:
* SPI line mode setting
*/
SPI_WIRE_MODE_SET,
/*! Compatible version: V0; V1
*@Describe:
* Get SPI line mode current setting
*/
SPI_WIRE_MODE_GET,
/*! Compatible version: V1
*@Describe:
* SPI host sampling delay
*/
SPI_SAMPLE_DELAY,
/*! Compatible version: V0; V1
*@Describe:
* Set SPI frame size
*/
SPI_SET_FRAME_SIZE,
/*! Compatible version: V1
*@Describe:
* Sets the length threshold for using DMA, unit: byte
*/
SPI_SET_LEN_THRESHOLD,
/*! Set SPI CS value.
*/
SPI_SET_CS,
/*! Set SPI uses none cs pin.
*/
SPI_CFG_SET_NONE_CS,
/*! Read DMA RX cnt.
*/
SPI_READ_DMA_RX_CNT,
/*! Kick SPI dma rx.
*/
SPI_KICK_DMA_RX,
/*! Kick SPI dma tx.
*/
SPI_KICK_DMA_TX,
/*! set SPI write/read timeout.
*/
SPI_SET_TIMEOUT,
/*! set SPI LSB/MSB first.
*/
SPI_SET_LSB_FIRST,
/*!
* Only for XIP
*/
SPI_XIP_SET_ADR,
/*!
* Only for XIP
*/
SPI_XIP_ERASE_4KB,
/*!
* Only for XIP
*/
SPI_XIP_ERASE_64KB,
/*!
* Only for XIP
*/
SPI_XIP_ERASE_SECURITY_REG,
/*!
* Only for XIP
*/
SPI_XIP_PROGRAM_SECURITY_REG,
/*!
* Only for XIP
*/
SPI_XIP_READ_SECURITY_REG,
SPI_SET_SLAVE_SW_RESERVED,
/*
* spi sensor
*/
SPI_SENSOR_VSYNC_TIMEOUT,
SPI_SENSOR_VSYNC_HEAD_CNT,
SPI_SENSOR_VSYNC_EN,
SPI_SENSOR_HSYNC_TIMEOUT,
SPI_SENSOR_HSYNC_HEAD_CNT,
SPI_SENSOR_BUF_LEN,
SPI_SENSOR_SET_ADR0,
SPI_SENSOR_SET_ADR1,
SPI_SENSOR_PINGPANG_EN,
SPI_HIGH_SPEED_CFG,
SPI_KICK_DMA_EN,
SPI_RX_TIMEOUT_CFG,
//新增加命令都往后添加
SPI_XIP_CUSTOM_READ_CMD,
SPI_XIP_CUSTOM_WRITE_CMD,
SPI_XIP_CUSTOM_ERASE_CMD,
SPI_GET_DMA_PENDING,
SPI_CLEAR_DMA_PENDING,
SPI_XIP_CUSTOM_SET_REMAP, //配置reamp地址,SPI_XIP_CUSTOM_SET_ENCRYPT要配置1才能生效
SPI_XIP_CUSTOM_SET_ENCRYPT, //配置是否要强行加密
SPI_XIP_CUSTOM_CFG_RUN_OFFSET,
SPI_XIP_CUSTOM_CFG_ENCRYPT,
SPI_XIP_GET_SPI_ADDR, //传入flash绝对地址,返回代码相对地址(比如传入0,返回0x18000000,如果返回0,就是错误的意思,remap一定要比绝对地址小)
SPI_XIP_REG_OPT,
};
enum xip_opcode_cmd
{
XIP_READ,
XIP_WRITE,
XIP_ERASE,
XIP_SECURITY_ERASE,
XIP_SECURITY_WRITE,
XIP_SECURITY_READ,
};
/**
* @brief spi interrupt
*
*/
enum spi_irq_flag {
/*! Compatible version: V0; V1; V2
*@Describe:
* Transmits the currently configured length of tx data done
*/
SPI_IRQ_FLAG_TX_DONE = BIT(0),
/*! Compatible version: V0; V1; V2
*@Describe:
* Transmits the currently configured length of rx data done
*/
SPI_IRQ_FLAG_RX_DONE = BIT(1),
/*! Compatible version: V0; V1
*@Describe:
* The received buffer is full, max: 40bit
*/
SPI_IRQ_FLAG_FIFO_OVERFLOW = BIT(2),
/*! Compatible version: V0; V1
*@Describe:
* Dectect the CS rising
*/
SPI_IRQ_FLAG_CS_RISING = BIT(3),
SPI_IRQ_FLAG_SLAVE_FSM_READ_STATUS = BIT(4),
SPI_IRQ_FLAG_SLAVE_FSM_WRONG_CMD = BIT(5),
SPI_IRQ_FLAG_RX_TIMEOUT = BIT(6),
};
typedef void (*spi_irq_hdl)(uint32 irq, uint32 irq_data);
struct spi_device {
struct dev_obj dev;
};
struct spi_hal_ops{
struct devobj_ops ops;
int32(*open)(struct spi_device *p_spi, uint32 clk_freq, uint32 work_mode, uint32 wire_mode, uint32 clk_mode);
int32(*close)(struct spi_device *p_spi);
int32(*ioctl)(struct spi_device *p_spi, uint32 cmd, uint32 param1, uint32 param2);
int32(*read)(struct spi_device *p_spi, void *buf, uint32 size);
int32(*write)(struct spi_device *p_spi, const void *buf, uint32 size);
int32(*write_scatter)(struct spi_device *p_spi, const scatter_data *data, uint32 count);
int32(*request_irq)(struct spi_device *p_spi, uint32 irq_flag, spi_irq_hdl irqhdl, uint32 irq_data);
int32(*release_irq)(struct spi_device *spi, uint32 irq_flag);
};
int32 spi_open(struct spi_device *p_spi, uint32 clk_freq, uint32 work_mode, uint32 wire_mode, uint32 clk_mode);
int32 spi_close(struct spi_device *p_spi);
int32 spi_ioctl(struct spi_device *p_spi, uint32 cmd, uint32 param1, uint32 param2);
int32 spi_read(struct spi_device *p_spi, void *buf, uint32 size);
int32 spi_write(struct spi_device *p_spi, const void *buf, uint32 size);
int32 spi_write_scatter(struct spi_device *p_spi, const scatter_data *data, uint32 count);
int32 spi_set_cs(struct spi_device *p_spi, uint32 cs, uint32 value);
int32 spi_request_irq(struct spi_device *p_spi, uint32 irq_flag, spi_irq_hdl irqhdl, uint32 irq_data);
int32 spi_release_irq(struct spi_device *spi, uint32 irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/spi_nor.h
+80
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@@ -0,0 +1,80 @@
#ifndef _HAL_SPI_NOR_H_
#define _HAL_SPI_NOR_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "osal/mutex.h"
#include "osal/atomic.h"
/**
* @brief spi nor mode
*/
enum spi_nor_mode {
SPI_NOR_NORMAL_SPI_MODE,
SPI_NOR_DUAL_SPI_MODE,
SPI_NOR_QUAD_SPI_MODE,
SPI_NOR_QPI_MODE,
SPI_NOR_XIP_MODE,
};
struct spi_nor_flash;
struct spi_nor_bus {
void (*open)(struct spi_nor_flash *flash);
void (*close)(struct spi_nor_flash *flash);
void (*read)(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
void (*program)(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
void (*sector_erase)(struct spi_nor_flash *flash, uint32 addr);
void (*block_erase)(struct spi_nor_flash *flash, uint32 addr);
void (*chip_erase)(struct spi_nor_flash *flash);
void (*enter_power_down)(struct spi_nor_flash *flash);
void (*release_power_down)(struct spi_nor_flash *flash);
void (*erase_security_reg)(struct spi_nor_flash *flash, uint32 addr);
void (*program_security_reg)(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
void (*read_security_reg)(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
void (*custom_read)(struct spi_nor_flash *flash, uint32_t param);
void (*custom_write)(struct spi_nor_flash *flash, uint32_t param);
void (*custom_erase)(struct spi_nor_flash *flash, uint32_t param);
int32 (*ioctl)(struct spi_nor_flash *flash, uint32_t cmd,uint32_t param1,uint32_t param2);
};
struct spi_nor_flash {
struct dev_obj dev;
struct spi_device *spidev;
struct {
uint32 clk, clk_mode, wire_mode, cs;
} spi_config;
uint32 size, sector_size, page_size,block_size;
uint32 vendor_id, product_id;
enum spi_nor_mode mode;
struct os_mutex lock;
atomic_t ref;
const struct spi_nor_bus *bus;
};
const struct spi_nor_bus *spi_nor_bus_get(enum spi_nor_mode mode);
void spi_nor_standard_read_jedec_id(struct spi_nor_flash *flash, uint8 *buf);
int32 spi_nor_open(struct spi_nor_flash *flash);
void spi_nor_close(struct spi_nor_flash *flash);
void spi_nor_read(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 len);
void spi_nor_write(struct spi_nor_flash *flash, uint32 addr, uint8 *data, uint32 len);
void spi_nor_sector_erase(struct spi_nor_flash *flash, uint32 sector_addr);
void spi_nor_block_erase(struct spi_nor_flash *flash, uint32 block_addr);
void spi_nor_chip_erase(struct spi_nor_flash *flash);
void spi_nor_erase_security_reg(struct spi_nor_flash *flash, uint32 addr);
void spi_nor_program_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
void spi_nor_read_security_reg(struct spi_nor_flash *flash, uint32 addr, uint8 *buf, uint32 size);
int32 spi_nor_attach(struct spi_nor_flash *flash, uint32 dev_id);
void spi_nor_enter_power_down(struct spi_nor_flash *flash);
void spi_nor_release_power_down(struct spi_nor_flash *flash);
void spi_nor_custom_read(struct spi_nor_flash *flash, uint32_t param);
void spi_nor_custom_write(struct spi_nor_flash *flash, uint32_t param);
void spi_nor_custom_erase(struct spi_nor_flash *flash, uint32_t param);
int32 spi_nor_ioctl(struct spi_nor_flash *flash, uint32_t cmd,uint32_t param1,uint32_t param2);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/sysaes.h
+66
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#ifndef _HAL_SYSAES_H_
#define _HAL_SYSAES_H_
#ifdef __cplusplus
extern "C" {
#endif
#define SYS_AES_DEBUG_ERR_ENABLE 1
#if SYS_AES_DEBUG_ERR_ENABLE
#define SYS_AES_ERR_PRINTF(fmt, args...) os_printf(fmt, ##args)
#else
#define SYS_AES_ERR_PRINTF(fmt, args...)
#endif
/*----- AES Control Codes: Mode Parameters: Key length -----*/
enum SYSAES_KEY_LEN {
AES_KEY_LEN_BIT_128,
AES_KEY_LEN_BIT_192,
AES_KEY_LEN_BIT_256,
};
enum SYSAES_MODE {
AES_MODE_ECB,
AES_MODE_CBC,
AES_MODE_CTR,
// AES_MODE_CFB1,
// AES_MODE_CFB8,
// AES_MODE_CFB128,
// AES_MODE_OFB,
// AES_MODE_CTR,
};
#define AES_BLOCK_SIZE 16
struct sysaes_para {
uint8 mode; /* enum SYSAES_MODE */
uint8 key_len; /* enum SYSAES_KEY_LEN */
uint8 *src;
uint8 *dest;
uint32 aes_len; /* v1-v2 blocks, v3 bytes */
uint8 key[32];
uint8 *iv; /* AES_BLOCK_SIZE : 16 */
};
struct sysaes_dev {
struct dev_obj dev;
};
struct aes_hal_ops{
struct devobj_ops ops;
int32(*encrypt)(struct sysaes_dev *dev, struct sysaes_para *para);
int32(*decrypt)(struct sysaes_dev *dev, struct sysaes_para *para);
};
int32 sysaes_encrypt(struct sysaes_dev *dev, struct sysaes_para *para);
int32 sysaes_decrypt(struct sysaes_dev *dev, struct sysaes_para *para);
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SYSAES_H_ */
sdk/include/hal/timer_device.h
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#ifndef _HAL_TIMER_DEVICE_H_
#define _HAL_TIMER_DEVICE_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief timer type
*/
enum timer_type {
TIMER_TYPE_ONCE,
TIMER_TYPE_PERIODIC,
};
enum timer_ioctl_cmd {
TIMER_GET_TIMESTAMP,
TIMER_CALC_TIME_DIFF_US,
/*
* configure the prescaler of clk
*/
TIMER_SET_CLK_PSC,
/*
* configure type the slave mode
*/
TIMER_SET_SLAVE_MODE,
TIMER_SET_PERIOD,
TIMER_SET_CLK_SRC,
};
enum timer_irq_flag {
TIMER_INTR_PERIOD = BIT(0),
};
typedef void (*timer_cb_hdl)(uint32 cb_data, uint32 irq_flag);
struct timer_device {
struct dev_obj dev;
};
struct timer_hal_ops{
struct devobj_ops ops;
int32(*open)(struct timer_device *timer, enum timer_type type, uint32 flags);
int32(*close)(struct timer_device *timer);
int32(*start)(struct timer_device *timer, uint32 tmo_us, timer_cb_hdl cb, uint32 cb_data);
int32(*stop)(struct timer_device *timer);
int32(*suspend)(struct timer_device *timer);
int32(*resume)(struct timer_device *timer);
int32(*ioctl)(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct timer_device *timer, uint32 irq_flag, timer_cb_hdl cb, uint32 data);
int32(*release_irq)(struct timer_device *timer, uint32 irq_flag);
};
int32 timer_device_open(struct timer_device *timer, enum timer_type mode, uint32 flags);
int32 timer_device_close(struct timer_device *timer);
int32 timer_device_start(struct timer_device *timer, uint32 period_sysclkpd_cnt, timer_cb_hdl cb, uint32 cb_data);
int32 timer_device_stop(struct timer_device *timer);
int32 timer_device_suspend(struct timer_device *timer);
int32 timer_device_resume(struct timer_device *timer);
int32 timer_device_ioctl(struct timer_device *timer, uint32 cmd, uint32 param1, uint32 param2);
int32 timer_request_irq(struct timer_device *timer, uint32 irq_flag, timer_cb_hdl cb, uint32 cb_data);
int32 timer_release_irq(struct timer_device *timer, uint32 irq_flag);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/tk.h
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#ifndef _HAL_TK_H_
#define _HAL_TK_H_
#include "typesdef.h"
#ifdef __cplusplus
extern "C" {
#endif
enum touchkey_ioctl_cmd
{
TK_IOCTL_CMD_NONE = 0,
};
enum touchkey_irq_flag
{
TK_IRQ_FLAG_GET_KEY_VALUE = BIT(0),
};
enum touchkey_key_num
{
TK_KEY_TYPE_LONG = BIT(26),
TK_KEY_TYPE_NONE = BIT(27),
};
/* User interrupt handle */
typedef int32 (*tk_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2, uint32 param3);
struct hgtk_param
{
unsigned char __tk_index ;
unsigned char __tk_cs_en ;
unsigned char __tk_use_num ;
unsigned char __tk_long_key ;
unsigned char __tk_adjust_en ;
unsigned char param [14] ;
unsigned char config[17] ;
volatile unsigned char __time_base_cnt ;
volatile unsigned char __tk_ch_cnt_0[6];
volatile unsigned char __tk_ch_cnt_1[6];
volatile unsigned char __tk_ch_cnt_2[6];
volatile unsigned char __tk_ch_cnt_3[6];
volatile unsigned char __tk_ch_cnt_4[6];
volatile unsigned char __tk_ch_cnt_5[6];
volatile unsigned char __tk_ch_cnt_6[6];
volatile unsigned char __tk_ch_cnt_7[6];
volatile unsigned char __tk_ch_index[6];
unsigned short __tk_adjust_time ;
unsigned short __tk_adjust_diff_valu ;
unsigned short __tk_valid_time ;
unsigned short __tk_long_key_time ;
unsigned short __tk_noise_value ;
volatile unsigned short __tk_i_set[6] ;
volatile unsigned short __tk_ch_fth[6] ;
volatile unsigned short __tk_ch_data_0[6] ;
volatile unsigned short __tk_ch_data_1[6] ;
volatile unsigned short __tk_ch_data_2[6] ;
volatile unsigned short __tk_ch_data_3[6] ;
volatile unsigned short __tk_ch_data_4[6] ;
volatile unsigned short __tk_ch_data_5[6] ;
volatile unsigned short __tk_ch_data_6[6] ;
volatile unsigned short __tk_ch_data_7[6] ;
volatile unsigned short __tk_ch_data_8[6] ;
unsigned long __tk_adjust_line ;
};
struct tk_device {
struct dev_obj dev;
};
struct tk_hal_ops {
struct devobj_ops ops;
int32(*open) (struct tk_device *tk);
int32(*close) (struct tk_device *tk);
int32(*ioctl) (struct tk_device *tk, enum touchkey_ioctl_cmd ioctl_cmd, uint32 param);
int32(*request_irq)(struct tk_device *tk, tk_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
int32(*release_irq)(struct tk_device *tk, enum touchkey_irq_flag irq_flag);
};
int32 tk_open(struct tk_device *tk);
int32 tk_ioctl(struct tk_device *tk, enum touchkey_ioctl_cmd ioctl_cmd, uint32 param);
int32 tk_irq_request(struct tk_device *tk, tk_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
int32 tk_irq_release(struct tk_device *tk, uint32 irq_flag);
int32 tk_close(struct tk_device *tk);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/uart.h
+315
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/**
* @file uart.h
* @author HUGE-IC Application Team
* @brief UART HAL driver
* @version 1.0.0
* @date 2021-8-30
*
* @copyright Copyright (c) 2021 HUGE-IC
*/
#ifndef _HAL_UART_H_
#define _HAL_UART_H_
#include "typesdef.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup Docxygenid_UART_enum UART enum
* @ingroup Docxygenid_UART_Driver
* @brief UART enumeration description.
* @{
*/
/**
* @brief Enumeration constant for UART mode.
*/
enum uart_mode {
/*! Set UART to full duplex mode.
*/
UART_MODE_DUPLEX,
/*! Set UART to simplex_tx mode.
*/
UART_MODE_SIMPLEX_TX,
/*! Set UART to simplex_rx mode.
*/
UART_MODE_SIMPLEX_RX,
};
/**
* @brief Enumeration constant for UART parity.
*/
enum uart_parity {
/*! Set UART to no parity mode.
*/
UART_PARITY_NONE,
/*! Set UART to odd parity mode.
*/
UART_PARITY_ODD,
/*! Set UART to even parity mode.
*/
UART_PARITY_EVEN,
};
/**
* @brief Enumeration constant for UART stop bit.
*/
enum uart_stop_bit {
/*! Set UART stop bit to 1bit.
*/
UART_STOP_BIT_1,
/*! Set UART stop bit to 1.5bit.
*/
UART_STOP_BIT_1_5,
/*! Set UART stop bit to 2bit.
*/
UART_STOP_BIT_2,
};
/**
* @brief Enumeration constant for UART data bit.
*/
enum uart_data_bit {
/*! Set UART data bit to 5bit.
*/
UART_DATA_BIT_5,
/*! Set UART data bit to 6bit.
*/
UART_DATA_BIT_6,
/*! Set UART data bit to 7bit.
*/
UART_DATA_BIT_7,
/*! Set UART data bit to 8bit.
*/
UART_DATA_BIT_8,
/*! Set UART data bit to 9bit.
*/
UART_DATA_BIT_9,
};
/**
* @brief Enumeration constant for UART irq flag.
*/
enum uart_irq_flag {
/*!
* @brief Interrupt: send a frame of data done.
* @note
* If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
* if the data bit is 9bit, one frame of data is 9bit.
*/
UART_IRQ_FLAG_TX_BYTE = BIT(0),
/*!
* @brief Interrupt: time is up, no data has been received yet.
* @note
* This interrupt is only used for UART receive.
*/
UART_IRQ_FLAG_TIME_OUT = BIT(1),
/*!
* @brief Interrupt: UART send done using DMA.
* @note
* Before configuring this interrupt,\n
* you need to use @ref uart_ioctl() function to enable DMA.
*/
UART_IRQ_FLAG_DMA_TX_DONE = BIT(2),
/*!
* @brief Interrupt: UART receive done using DMA.
* @note
* Before configuring this interrupt,\n
* you need to use @ref uart_ioctl() function to enable DMA.
*/
UART_IRQ_FLAG_DMA_RX_DONE = BIT(3),
/*!
* @brief Interrupt: UART receives a frame of data error.
* @note
* - If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
* if the data bit is 9bit, one frame of data is 9bit.
* - A frame of data error, usually means that the number of stop bits of \n
* a frame of data does not match the expected number of bits.
*/
UART_IRQ_FLAG_FRAME_ERR = BIT(4),
/*!
* @brief Interrupt: UART receives a frame of data done.
* @note
* If the UART configuration data bit is 8bit, one frame of data is 8bit;\n
* if the data bit is 9bit, one frame of data is 9bit.
*/
UART_IRQ_FLAG_RX_BYTE = BIT(5),
UART_IRQ_FLAG_RESET = BIT(6),
};
/**
* @brief Enumeration constant for UART irq flag
*/
enum uart_ioctl_cmd {
/*!
* @brief Set the baudrate of the UART.
*/
UART_IOCTL_CMD_SET_BAUDRATE,
/*!
* @brief Set the UART data bits.
* @note
* reference @ref uart_data_bit.
*/
UART_IOCTL_CMD_SET_DATA_BIT,
/*!
* @brief Set the UART parity mode.
* @note
* reference @ref uart_parity.
*/
UART_IOCTL_CMD_SET_PARITY,
/*!
* @brief Set the UART stop bit.
* @note
* reference @ref uart_stop_bit.
*/
UART_IOCTL_CMD_SET_STOP_BIT,
/*!
* @brief Set the timeout.
*/
UART_IOCTL_CMD_SET_TIME_OUT,
/*!
* @brief Set whether the UART uses DMA to send.
*/
UART_IOCTL_CMD_USE_DMA,
/*!
* @brief Set UART work mode.
* @note
* reference @ref uart_mode.
*/
UART_IOCTL_CMD_SET_WORK_MODE,
/*!
* @brief Query whether the UART DATA reg ready.
*/
UART_IOCTL_CMD_DATA_RDY,
/*!
* @brief
* Disable this uart tx by cpu, and turn to use dma.
* @note
* Only use for UART4/5.
*/
UART_IOCTL_CMD_DISABLE_DEBUG_SELECTION,
/*!
* @brief Enable the UART rs485 mode.
*/
UART_IOCTL_CMD_SET_RS485_EN,
/*!
* @brief Set the UART rs485 DET.
*/
UART_IOCTL_CMD_SET_RS485_DET,
/*!
* @brief Set the UART rs485 TAT.
*/
UART_IOCTL_CMD_SET_RS485_TAT,
/*!
* @brief Set the UART rs485 DE and RE polarity.
*/
UART_IOCTL_CMD_SET_RS485DRE_POL,
};
/** @} Docxygenid_UART_enum*/
/* User interrupt handle */
typedef int32 (*uart_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
/** @defgroup Docxygenid_UART_structure UART structure
* @ingroup Docxygenid_UART_Driver
* @brief UART structure description
* @note
* User better not modify the structure.
* @{
*/
struct uart_device {
struct dev_obj dev;
};
struct uart_hal_ops{
struct devobj_ops ops;
int32(*open)(struct uart_device *uart, uint32 baudrate);
int32(*close)(struct uart_device *uart);
int32(*putc)(struct uart_device *uart, int8 value);
uint8(*getc)(struct uart_device *uart);
int32(*puts)(struct uart_device *uart, uint8* buf, uint32 len);
int32(*gets)(struct uart_device *uart, uint8* buf, uint32 len);
int32(*ioctl)(struct uart_device *uart, enum uart_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct uart_device *uart, uart_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
int32(*release_irq)(struct uart_device *uart, uint32 irq_flag);
};
/** @} Docxygenid_UART_structure*/
/** @addtogroup Docxygenid_UART_Driver
* @{
*/
/**
* @brief Open uart with baudrate and the default configuration.
* @param uart : UART handle. Usually use @ref dev_get() function to get the handle.
* @param baudrate : Configure the baudrate for UART.
* @return
* - RET_OK : UART module open successfully.
* - RET_ERR : UART module open unsuccessfully.
* @note
* The default configuration is full duplex mode, no parity mode,\n
* data bit is 8bit, stop bit is 1bit.If you need to change the configuration,\n
* you can use the @ref uart_ioctl function to make changes after initialization is complete.
*/
int32 uart_open(struct uart_device *uart, uint32 baudrate);
int32 uart_close(struct uart_device *uart);
int32 uart_putc(struct uart_device *uart, int8 value);
uint8 uart_getc(struct uart_device *uart);
int32 uart_puts(struct uart_device *uart, uint8* buf, uint32 len);
int32 uart_gets(struct uart_device *uart, uint8* buf, uint32 len);
int32 uart_ioctl(struct uart_device *uart, enum uart_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 uart_request_irq(struct uart_device *uart, uart_irq_hdl irq_hdl, uint32 irq_flag, uint32 irq_data);
int32 uart_release_irq(struct uart_device *uart, uint32 irq_flag);
/** @} Docxygenid_UART_functions*/
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/usb_ch9.h
+1027
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sdk/include/hal/usb_device.h
+103
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#ifndef _HAL_USB_DEVICE_H_
#define _HAL_USB_DEVICE_H_
#include "usb_ch9.h"
#ifdef __cplusplus
extern "C" {
#endif
enum usb_dev_irqs {
USB_DEV_RESET_IRQ,
USB_DEV_SUSPEND_IRQ,
USB_DEV_RESUME_IRQ,
USB_DEV_SOF_IRQ,
USB_DEV_CTL_IRQ,
USB_EP_RX_IRQ,
USB_EP_TX_IRQ,
USB_CONNECT,
USB_DISCONNECT,
USB_BABBLE,
USB_XACT_ERR,
};
enum usb_dev_io_cmd {
USB_DEV_IO_CMD_AUTO_TX_NULL_PKT_ENABLE,
USB_DEV_IO_CMD_AUTO_TX_NULL_PKT_DISABLE,
USB_DEV_IO_CMD_REMOTE_WAKEUP,
/* this function need call after attatch & before open
* msg[1:0] : vid
* msg[3:2] : pid
*/
USB_DEV_IO_CMD_SET_ID,
USB_HOST_HY_TUNE_EN,
USB_HOST_SET_HY_TUNE,
USB_HOST_SET_TX_VERF,
USB_HOST_SET_TX_SLIVER,
USB_HOST_GET_TX_SLIVER,
USB_HOST_SET_SLIVER_TOG_EN,
USB_HOST_SET_RX_SLIVER,
USB_HOST_GET_RX_SLIVER,
};
struct usb_device_ep_cfg {
uint8 ep_id;
uint8 ep_type;
uint8 ep_dir_tx;
uint16 max_packet_size_hs;
uint16 max_packet_size_fs;
};
struct usb_device_cfg {
uint16 vid; /* usb device VID */
uint16 pid; /* usb device PID */
uint8 speed; /* not used */
uint8 *p_device_descriptor; /* usb device descriptor */
uint8 *p_config_desc_hs; /* usb config descriptor */
uint8 *p_config_desc_fs; /* usb config descriptor */
uint16 config_desc_len; /* usb config descriptor total len */
uint8 interface_num;
uint8 ep_nums;
struct usb_device_ep_cfg ep_cfg[8]; /* must same with config_desc */
};
typedef uint32 (*usbdev_irq_hdl)(uint32 irq, uint32 param1, uint32 param2, uint32 param3);
struct usb_device {
struct dev_obj dev;
};
struct usb_hal_ops{
struct devobj_ops ops;
int32(*open)(struct usb_device *p_usb_d, struct usb_device_cfg *p_usbdev_cfg);
int32(*close)(struct usb_device *p_usb_d);
int32(*read)(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32(*write)(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32(*write_scatter)(struct usb_device *p_usb_d, uint8 ep, scatter_data *data, uint32 count, uint8 sync);
int32(*ioctl)(struct usb_device *p_usb_d, uint32 cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct usb_device *p_usb_d, usbdev_irq_hdl irqhdl, uint32 data);
};
int32 usb_device_open(struct usb_device *p_usb_d, struct usb_device_cfg * p_usbdev_cfg);
int32 usb_device_close(struct usb_device *p_usb_d);
int32 usb_device_write(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32 usb_device_write_scatter(struct usb_device *p_usb_d, uint8 ep, scatter_data *data, uint32 count, uint8 sync);
int32 usb_device_read(struct usb_device *p_usb_d, uint8 ep, uint8 *buff, uint32 len, uint8 sync);
int32 usb_device_ioctl(struct usb_device *p_usb_d, uint32 cmd, uint32 param1, uint32 param2);
int32 usb_device_request_irq(struct usb_device *p_usb_d, usbdev_irq_hdl handle, uint32 data);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/hal/vpp.h
+364
View File
@@ -0,0 +1,364 @@
#ifndef HAL_VPP_H
#define HAL_VPP_H
/* User interrupt handle */
typedef int32(*vpp_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
/**
* @brief UART ioctl_cmd type
*/
enum vpp_ioctl_cmd {
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_DIS_UV_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_THRESHOLD,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_RC,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_RC,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_COLOR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_COLOR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_BMPADR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_BMPADR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_LOCATED,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_LOCATED,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_CONTRAST,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_CONTRAST,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_CHAR_SIZE_AND_NUM,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_CHAR_IDX,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_TAKE_PHOTO_LINEBUF,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_PHOTO_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK0_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_WATERMARK1_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_MOTION_DET_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_MOTION_CALBUF,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_MOTION_RANGE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_MOTION_BLK_THRESHOLD,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_MOTION_FRAME_THRESHOLD,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_IFP_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_IFP_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_MODE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_SIZE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_SET_YCBCR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF0_CNT,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF1_CNT,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF1_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF1_SHRINK,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_INPUT_INTERFACE,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF0_Y_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF0_U_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF0_V_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF1_Y_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF1_U_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_BUF1_V_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_ITP_Y_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_ITP_U_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_ITP_V_ADDR,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_ITP_EN,
/*! Compatible version: V2;
*@ Describe:
*
*/
VPP_IOCTL_CMD_ITP_AUTO_CLOSE,
};
struct vpp_device {
struct dev_obj dev;
};
struct vpp_hal_ops {
struct devobj_ops ops;
int32(*open)(struct vpp_device *vpp_dev);
int32(*suspend)(struct vpp_device *vpp_dev);
int32(*resume)(struct vpp_device *vpp_dev);
int32(*close)(struct vpp_device *vpp_dev);
int32(*ioctl)(struct vpp_device *vpp_dev, enum vpp_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct vpp_device *vpp_dev, uint32 irq_flag, vpp_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct vpp_device *vpp_dev, uint32 irq_flag);
};
int32 vpp_request_irq(struct vpp_device *p_vpp, uint32 irq_flags, vpp_irq_hdl irq_hdl, uint32 irq_data);
int32 vpp_release_irq(struct vpp_device *p_vpp, uint32 irq_flags);
int32 vpp_open(struct vpp_device *p_vpp);
int32 vpp_close(struct vpp_device *p_vpp);
int32 vpp_suspend(struct vpp_device *p_vpp);
int32 vpp_resume(struct vpp_device *p_vpp);
int32 vpp_dis_uv_mode(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_threshold(struct vpp_device *p_vpp,uint32 dlt,uint32 dht);
int32 vpp_set_water0_rc(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_water1_rc(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_water0_color(struct vpp_device *p_vpp,uint8 y,uint8 u,uint8 v);
int32 vpp_set_water1_color(struct vpp_device *p_vpp,uint8 y,uint8 u,uint8 v);
int32 vpp_set_water0_bitmap(struct vpp_device *p_vpp,uint32 bitmap);
int32 vpp_set_water1_bitmap(struct vpp_device *p_vpp,uint32 bitmap);
int32 vpp_set_water0_locate(struct vpp_device *p_vpp,uint8 x,uint8 y);
int32 vpp_set_water1_locate(struct vpp_device *p_vpp,uint8 x,uint8 y);
int32 vpp_set_water0_contrast(struct vpp_device *p_vpp,uint8 contrast);
int32 vpp_set_water1_contrast(struct vpp_device *p_vpp,uint8 contrast);
int32 vpp_set_watermark0_charsize_and_num(struct vpp_device *p_vpp,uint8 w,uint8 h,uint8 num);
int32 vpp_set_watermark0_idx(struct vpp_device *p_vpp,uint8 index_num,uint8 index);
int32 vpp_set_watermark1_size(struct vpp_device *p_vpp,uint8 w,uint8 h);
int32 vpp_set_watermark0_mode(struct vpp_device *p_vpp,uint8 mode);
int32 vpp_set_watermark1_mode(struct vpp_device *p_vpp,uint8 mode);
int32 vpp_set_watermark0_enable(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_watermark1_enable(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_motion_det_enable(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_motion_calbuf(struct vpp_device *p_vpp,uint32 calbuf);
int32 vpp_set_motion_range(struct vpp_device *p_vpp,uint16 x_s,uint16 y_s,uint16 x_e,uint16 y_e);
int32 vpp_set_motion_blk_threshold(struct vpp_device *p_vpp,uint8 threshold);
int32 vpp_set_motion_frame_threshold(struct vpp_device *p_vpp,uint32 threshold);
int32 vpp_set_ifp_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_ifp_en(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_mode(struct vpp_device *p_vpp,uint8 mode);
int32 vpp_set_video_size(struct vpp_device *p_vpp,uint32 w,uint32 h);
int32 vpp_set_ycbcr(struct vpp_device *p_vpp,uint8 ycbcr);
int32 vpp_set_buf0_count(struct vpp_device *p_vpp,uint8 cnt);
int32 vpp_set_buf1_count(struct vpp_device *p_vpp,uint8 cnt);
int32 vpp_set_buf1_en(struct vpp_device *p_vpp,uint8 enable);
int32 vpp_set_buf1_shrink(struct vpp_device *p_vpp,uint8 half);
int32 vpp_set_input_interface(struct vpp_device *p_vpp,uint8 mode);
int32 vpp_set_buf0_y_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_buf0_u_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_buf0_v_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_buf1_y_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_buf1_u_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_buf1_v_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_itp_y_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_itp_u_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_itp_v_addr(struct vpp_device *p_vpp,uint32 addr);
int32 vpp_set_itp_linebuf(struct vpp_device *p_vpp,uint32 linebuf);
int32 vpp_set_itp_enable(struct vpp_device *p_vpp,uint8 en);
int32 vpp_set_itp_auto_close(struct vpp_device *p_vpp,uint8 en);
void vpp_itp_done(uint32 irq,uint32 dev,uint32 param);
void vpp_itp_vfx_done(uint32 irq,uint32 dev,uint32 param);
#endif