pure sdk for main

This commit is contained in:
divadiow
2025-08-27 09:51:58 +01:00
parent f0d033f1c9
commit 0571416e7c
3283 changed files with 1577720 additions and 1 deletions
@@ -0,0 +1,181 @@
#ifndef _AUALAW_H
#define _AUALAW_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUALAW irq_flag type
*/
enum aualaw_irq_flag {
/*!
* @brief:
*
*/
AUALAW_IRQ_FLAG_HALF = BIT(0),
/*!
* @brief:
*
*/
AUALAW_IRQ_FLAG_FULL = BIT(1),
};
/**
* @brief AUALAW ioctl_cmd type
*/
enum aualaw_ioctl_cmd {
/*!
* @brief:
*
*/
AUALAW_IOCTL_CMD_NONE,
};
/* User interrupt handle */
typedef void (*aualaw_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUALAW api for user */
struct aualaw_device {
struct dev_obj dev;
};
struct aualaw_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aualaw_device *aualaw);
int32(*close)(struct aualaw_device *aualaw);
int32(*encode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32(*decode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32(*ioctl)(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
};
/* AUALAW API functions */
/**
* @brief aualaw_open
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_open(struct aualaw_device *aualaw);
/**
* @brief aualaw_close
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_close(struct aualaw_device *aualaw);
/**
* @brief aualaw_encode
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief aualaw_decode
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief aualaw_ioctl
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief aualaw_request_irq
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief aualaw_release_irq
*
*
* @note .
*
* @param aualaw The address of aualaw device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aualaw_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,22 @@
#ifndef _HG_AUALAW_V0_H_
#define _HG_AUALAW_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aualaw_v0_init(void);
int32 hg_aualaw_v0_open(struct aualaw_device *aualaw);
int32 hg_aualaw_v0_close(struct aualaw_device *aualaw);
int32 hg_aualaw_v0_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32 hg_aualaw_v0_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
int32 hg_aualaw_v0_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_aualaw_v0_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_aualaw_v0_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */
+126
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@@ -0,0 +1,126 @@
#ifndef _AUEQ_H
#define _AUEQ_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUEQ ioctl_cmd type
*/
enum aueq_ioctl_cmd {
/*!
* @brief:
*
*/
AUEQ_IOCTL_CMD_NONE,
};
/*!
* @brief coefficient configuration
* @note
* a example of coefficient for 5 band:
* struct aueq_cfg cfg[5];
* cfg[0].b[0] = 0.1;
* cfg[0].b[1] = 0.3;
* ...
* cfg[1].b[1] = 0.6;
*/
struct aueq_cfg{
double b[3];
double a[2];
};
/* AUEQ api for user */
struct aueq_device {
struct dev_obj dev;
};
struct aueq_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aueq_device *aueq, struct aueq_cfg *p_cfg);
int32(*close)(struct aueq_device *aueq);
int32(*run)(struct aueq_device *aueq, void* dat_buf, uint32 bytes);
int32(*ioctl)(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
};
/* AUEQ API functions */
/**
* @brief aueq_open
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_open(struct aueq_device *aueq, struct aueq_cfg *p_cfg);
/**
* @brief aueq_close
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_close(struct aueq_device *aueq);
/**
* @brief aueq_encode
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_run(struct aueq_device *aueq, void* dat_buf, uint32 bytes);
/**
* @brief aueq_ioctl
*
*
* @note .
*
* @param aueq The address of aueq device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aueq_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,59 @@
#ifndef BIQUAD_FILTER_H
#define BIQUAD_FILTER_H
typedef int s32, S32;
typedef unsigned int u32, U32, uint;
typedef long long int s64, S64;
typedef unsigned long long u64, U64;
typedef short int s16, S16;
typedef unsigned short int u16, U16;
typedef signed char s8, S8;
typedef unsigned char u8, U8;
//模拟64bit芯片运算
int CLIP_INT24(int in);
int CLIP_INT16(int in);
void ML0(s32 x, s32 y);
void MLA(s32 x, s32 y);
void MSB(s32 x, s32 y);
s32 MLZ(s32 n);
s32 MLZ_QUICK(s32 n);
s32 MLZ_FIX(s32 n);
u32 get_acc_64_high_32(void);
u32 get_acc_64_low_32(void);
typedef struct {
int b[3];
int a[2];
int x[2];
int y[2];
int fixed_point_num;
} TYPE_BIQUAD_FILTER;
int biquad_filter_calc(TYPE_BIQUAD_FILTER *filter_ctl, int x);
//void biquad_filter_ctl_init(TYPE_BIQUAD_FILTER *filter_ctl, int fixed_point_num);
#if 0
void eq_lpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_hpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_bpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_notch_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_apf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double q);
void eq_peaking_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
void eq_low_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
void eq_high_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
double fs, double f0, double gain, double q);
#endif
#endif /* BIQUAD_FILTER_H */
@@ -0,0 +1,19 @@
#ifndef _HG_AUEQ_V0_H_
#define _HG_AUEQ_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_aueq_v0_init(void);
int32 hg_aueq_v0_open(struct aueq_device *aueq, struct aueq_cfg *p_cfg);
int32 hg_aueq_v0_close(struct aueq_device *aueq);
int32 hg_aueq_v0_run(struct aueq_device *aueq, void* dat_buf, uint32 bytes);
int32 hg_aueq_v0_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUEQ_V0_H_ */
@@ -0,0 +1,192 @@
#ifndef _AUFADE_H
#define _AUFADE_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUFADE calculate mode types
*/
enum aufade_mode {
AUFADE_IN = BIT(0),
AUFADE_OUT = BIT(1),
};
/**
* @brief AUFADE step types
*/
enum aufade_step {
AUFADE_STEP_1,
AUFADE_STEP_2,
AUFADE_STEP_4,
AUFADE_STEP_8,
};
/**
* @brief AUFADE sample types
*/
enum aufade_sample {
AUFADE_SAMPLE_1,
AUFADE_SAMPLE_2,
AUFADE_SAMPLE_3,
AUFADE_SAMPLE_4,
};
/**
* @brief AUFADE irq_flag type
*/
enum aufade_irq_flag {
/*!
* @brief:
*
*/
AUFADE_IRQ_FLAG_NONE = BIT(0),
};
/**
* @brief AUFADE ioctl_cmd type
*/
enum aufade_ioctl_cmd {
AUFADE_IOCTL_CMD_SET_STEP = BIT(0),
AUFADE_IOCTL_CMD_SET_SAMPLE = BIT(1),
};
/* User interrupt handle */
typedef void (*aufade_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUFADE api for user */
struct aufade_device {
struct dev_obj dev;
};
struct aufade_hal_ops {
struct devobj_ops ops;
int32(*open)(struct aufade_device *aufade);
int32(*close)(struct aufade_device *aufade);
int32(*start)(struct aufade_device *aufade, enum aufade_mode mode);
int32(*ioctl)(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
};
/* AUFADE API functions */
/**
* @brief aufade_open
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_open(struct aufade_device *aufade);
/**
* @brief aufade_close
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_close(struct aufade_device *aufade);
/**
* @brief aufade_start
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_start(struct aufade_device *aufade, enum aufade_mode mode);
/**
* @brief aufade_ioctl
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief aufade_request_irq
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief aufade_release_irq
*
*
* @note .
*
* @param aufade The address of aufade device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 aufade_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,23 @@
#ifndef _HG_AUFADE_V0_H_
#define _HG_AUFADE_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "dev/audio/components/fade/aufade.h"
#include "hg_audio_v0_hw.h"
int32 hg_aufade_v0_init(void);
int32 hg_aufade_v0_open(struct aufade_device *aufade);
int32 hg_aufade_v0_close(struct aufade_device *aufade);
int32 hg_aufade_v0_start(struct aufade_device *aufade, enum aufade_mode mode);
int32 hg_aufade_v0_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_aufade_v0_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_aufade_v0_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
int32 hg_aufade_v0_set_gain(struct hg_audio_hw_v0 *audio_hw, uint32 gain);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUFADE_V0_H_ */
@@ -0,0 +1,203 @@
#ifndef _AUVAD_H
#define _AUVAD_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief AUVAD calculate mode types
*/
enum auvad_calc_mode {
AUVAD_CALC_MODE_ENERGY = BIT(0),
AUVAD_CALC_MODE_ZCR = BIT(1),
};
/**
* @brief AUVAD irq_flag type
*/
enum auvad_irq_flag {
/*!
* @brief:
*
*/
NONE = BIT(0),
};
/**
* @brief AUVAD ioctl_cmd type
*/
enum auvad_ioctl_cmd {
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_CALC_MODE,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_TH0,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_TH1,
/*!
* @brief:
*
*/
AUVAD_IOCTL_CMD_SET_THRESHOLD_ZCR,
};
/* User interrupt handle */
typedef void (*auvad_irq_hdl)(uint32 irq, uint32 irq_data);
/* AUVAD api for user */
struct auvad_device {
struct dev_obj dev;
};
struct auvad_hal_ops {
struct devobj_ops ops;
int32(*open)(struct auvad_device *auvad, enum auvad_calc_mode mode);
int32(*close)(struct auvad_device *auvad);
int32(*calc)(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
int32(*ioctl)(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32(*request_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
int32(*release_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
};
/* AUVAD API functions */
/**
* @brief auvad_open
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
/**
* @brief auvad_close
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_close(struct auvad_device *auvad);
/**
* @brief auvad_encode
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_encode(struct auvad_device *auvad, void* dat_buf, uint32 bytes, void* result_buf);
/**
* @brief auvad_decode
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
/**
* @brief auvad_ioctl
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
/**
* @brief auvad_request_irq
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
/**
* @brief auvad_release_irq
*
*
* @note .
*
* @param auvad The address of auvad device in the RTOS.
* @param .
* @param .
*
* @return
* - RET_OK Success
* - RET_ERR Fail
*/
int32 auvad_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif
@@ -0,0 +1,21 @@
#ifndef _HG_AUVAD_V0_H_
#define _HG_AUVAD_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auvad_v0_init(void);
int32 hg_auvad_v0_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
int32 hg_auvad_v0_close(struct auvad_device *auvad);
int32 hg_auvad_v0_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
int32 hg_auvad_v0_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_auvad_v0_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_auvad_v0_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HG_AUVAD_V0_H_ */
+21
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@@ -0,0 +1,21 @@
#ifndef _HG_AUADC_V0_H_
#define _HG_AUADC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_auadc_v0_init(struct auadc_device *auadc);
int32 hg_auadc_v0_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
int32 hg_auadc_v0_close(struct auadc_device *auadc);
int32 hg_auadc_v0_read(struct auadc_device *auadc, void* buf, uint32 bytes);
int32 hg_auadc_v0_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_auadc_v0_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_auadc_v0_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */
+22
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@@ -0,0 +1,22 @@
#ifndef _HG_AUDAC_V0_H_
#define _HG_AUDAC_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 hg_audac_v0_init(struct audac_device *audac);
int32 hg_audac_v0_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
int32 hg_audac_v0_close(struct audac_device *audac);
int32 hg_audac_v0_write(struct audac_device *audac, void* buf, uint32 bytes);
int32 hg_audac_v0_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
int32 hg_audac_v0_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
int32 hg_audac_v0_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */
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#ifndef _HG_AUDIO_V0_H_
#define _HG_AUDIO_V0_H_
#ifdef __cplusplus
extern "C" {
#endif
/*!
* Type of device
*/
#define AUDIO_TYPE_AUADC BIT(0)
#define AUDIO_TYPE_AUDAC BIT(1)
#define AUDIO_TYPE_AUHS BIT(2)
#define AUDIO_TYPE_AUVAD BIT(3)
#define AUDIO_TYPE_AUALAW BIT(4)
#define AUDIO_TYPE_AUFADE BIT(5)
#define AUDIO_TYPE_AUEQ BIT(6)
/** @brief AUDIO operating handle structure
* @{
*/
/*!
* Common dat areas struct
*/
union __comm_dat{
uint32 comm;
struct {
uint32 adc_en :1,
dac_en :1,
hs_en :1,
alaw_en :1,
vad_en :1,
aufade_en :1,
eq_en :1,
ana_power_on :1,
ana_power_adc_on :1,
ana_power_dac_on :1;
} comm_bits;
};
struct hg_audio_v0 {
/* Pointer of device */
struct dev_obj dev;
uint32 hw;
/* common areas */
union __comm_dat comm_dat;
/* Pointer of common areas */
void *p_comm;
void *irq_hdl;
uint32 irq_data;
uint16 irq_num;
/* Type of device */
uint16 dev_type;
};
int32 hg_audio_v0_attach(uint32 dev_id, struct hg_audio_v0 *audio);
#ifdef __cplusplus
}
#endif
#endif /* _HGI2S_V0_H_ */