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pure sdk for main

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This commit is contained in:
divadiow
2025-08-27 09:51:58 +01:00
parent f0d033f1c9
commit 0571416e7c
3283 changed files with 1577720 additions and 1 deletions
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sdk/include/chip/soc.h
+9
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#ifndef __SOC_H__
#define __SOC_H__
#include "tx_platform.h"
#define CONFIG_KERNEL_RHINO 1
#define SYSTEM_CLOCK DEFAULT_SYS_CLK
#endif
sdk/include/chip/tx_platform.h
+62
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#ifndef _HUGE_IC_PLATFORM_H_
#define _HUGE_IC_PLATFORM_H_
#define PRO_TYPE_LMAC 1
#define PRO_TYPE_UMAC 2
#define PRO_TYPE_WNB 3
#define PRO_TYPE_UAV 4
#define PRO_TYPE_FMAC 5
#define PRO_TYPE_IOT 6
#define PRO_TYPE_FPV 7
#define PRO_TYPE_MCU 8
#define PRO_TYPE_QA 66
#define PRO_TYPE_QC 88
#ifdef TXW4002ACK803
#include "txw4002ack803/txw4002ack803.h"
#include "txw4002ack803/io_function.h"
#include "txw4002ack803/pin_names.h"
#include "txw4002ack803/sysctrl.h"
#include "txw4002ack803/test_atcmd.h"
#endif
#ifdef TXW80X
#include "txw80x/txw80x.h"
#include "txw80x/pin_names.h"
#include "txw80x/io_function.h"
#include "txw80x/adc_voltage_type.h"
#include "txw80x/sysctrl.h"
#include "txw80x/pmu.h"
#include "txw80x/misc.h"
#include "txw80x/boot_lib.h"
#include "txw80x/test_atcmd.h"
#endif
#ifdef TXW81X
#include "txw81x/txw81x.h"
#include "txw81x/pin_names.h"
#include "txw81x/io_mask.h"
#include "txw81x/io_function.h"
#include "txw81x/adc_voltage_type.h"
#include "txw81x/sysctrl.h"
#include "txw81x/pmu.h"
#include "txw81x/misc.h"
#include "txw81x/boot_lib.h"
#include "txw81x/test_atcmd.h"
#endif
#ifdef TXW8000
#include "txw8000/txw8000.h"
#include "txw8000/pin_names.h"
#include "txw8000/io_function.h"
#include "txw8000/adc_voltage_type.h"
#include "txw8000/sysctrl.h"
#include "txw8000/pmu.h"
#include "txw8000/misc.h"
#include "txw8000/test_atcmd.h"
#endif
#endif
sdk/include/chip/txw81x/adc_voltage_type.h
+72
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/**
******************************************************************************
* @file sdk\include\chip\txw80x\adc_voltage_type.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2022-03-18
* @brief This file contains all the adc_voltage_type.
* @copyright Copyright (c) 2016-2022 HUGE-IC
******************************************************************************
* @attention
* Only used for txw80x.
*
*
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __ADC_VOLTAGE_TYPE_H
#define __ADC_VOLTAGE_TYPE_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Docxygenid_ADC_voltage_type_enum
* @{
*/
/**
* @brief Enumeration constant for ADC voltage type.
* @note
* Enum number start from 0x101.
*/
enum adc_voltage_type {
/*! RF temperature
*/
ADC_CHANNEL_RF_TEMPERATURE = 0x101,
/*! Vtune电压
*/
ADC_CHANNEL_VTUNE = 0x102,
/*!
* VCO VDD电压
*/
ADC_CHANNEL_VCO_VDD = 0x103,
/*!
* VDD DIV电压
*/
ADC_CHANNEL_VDD_DIV = 0x104,
/*!
* VDDI电压
*/
ADC_CHANNEL_VDDI = 0x105,
/*!
* VDDI电压
*/
ADC_CHANNEL_VDD_PFD = 0x106,
};
/** @} Docxygenid_ADC_voltage_type_enum_enum*/
#ifdef __cplusplus
}
#endif
#endif
/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/
sdk/include/chip/txw81x/boot_lib.h
+19
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#ifndef __BOOT_LIB_H
#define __BOOT_LIB_H
#include "typesdef.h"
uint32 get_boot_loader_addr();
void save_boot_loader_addr();
uint32 get_boot_total_size();
uint32 get_boot_version();
void increase_boot_version();
void set_boot_msg(uint8 *msg);
uint32 get_boot_svn_version();
#endif
sdk/include/chip/txw81x/io_function.h
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/**
******************************************************************************
* @file sdk\include\chip\txw81x\io_function.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2022-01-11
* @brief This file contains all the GPIO functions.
* @copyright Copyright (c) 2016-2024 HUGE-IC
******************************************************************************
* @attention
* Only used for txw81x.
*
*
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __IO_FUNCTION_H
#define __IO_FUNCTION_H
#ifdef __cplusplus
extern "C" {
#endif
#include "typesdef.h"
/** @addtogroup Docxygenid_GPIO_enum
* @{
*/
/**
* @brief Enumeration constant for GPIO command.
* @note
* Enum number start from 0x101.
*/
enum gpio_cmd {
/*! GPIO cmd afio set
*/
GPIO_CMD_AFIO_SET = 0x101,
/*! GPIO cmd iomap output
*/
GPIO_CMD_IOMAP_OUT_FUNC,
/*! GPIO cmd iomap input
*/
GPIO_CMD_IOMAP_IN_FUNC,
/*! GPIO cmd iomap inout
*/
GPIO_CMD_IOMAP_INOUT_FUNC,
/*! GPIO pin driver strength config
*/
GPIO_CMD_DRIVER_STRENGTH,
};
/**
* @brief Enumeration constant for GPIO afio set.
*/
enum gpio_afio_set{
/*! gpio cmd afio 0
*/
GPIO_AF_0 = 0,
/*! gpio cmd afio 1
*/
GPIO_AF_1 ,
/*! gpio cmd afio 2
*/
GPIO_AF_2 ,
/*! gpio cmd afio 3
*/
GPIO_AF_3 ,
};
/**
* @breif : Enumeration constant for GPIO pull level.
*/
enum gpio_pull_level {
/*! gpio pull level : NONE
*/
GPIO_PULL_LEVEL_NONE = 0,
/*! gpio pull level : 4.7K
*/
GPIO_PULL_LEVEL_4_7K ,
/*! gpio pull level : 100k
*/
GPIO_PULL_LEVEL_100K ,
};
/**
* @breif : Enumeration constant for GPIO driver strength
*/
enum pin_driver_strength {
/*! Compatible version: V4
*/
GPIO_DS_4MA ,
/*! Compatible version: V4
*/
GPIO_DS_12MA,
/*! Compatible version: V4
*/
GPIO_DS_20MA,
/*! Compatible version: V4
*/
GPIO_DS_28MA,
} ;
/** @defgroup Enumeration constant for GPIO IO map output function selection
* @{
*/
enum gpio_iomap_out_func{
GPIO_IOMAP_OUTPUT,
/**
* @A : iofuncmask0[14]
* @B : iofuncmask0[8]
*
* @(A=0) & (B=0) : comp_dout_dig0
* @(A=1) & (B=0) : ospi_cs_io
* @(A=0) & (B=1) : dbgpath_dbgo[8]
*/
GPIO_IOMAP_OUT_COMP_DOUT_DIG0_VAL,
/**
* @A : iofuncmask0[20]
* @B : iofuncmask0[9]
*
* @(A=0) & (B=0) : comp_dout_dig1
* @(A=1) & (B=0) : lcd_data_o[0]
* @(A=0) & (B=1) : dbgpath_dbgo[9]
*/
GPIO_IOMAP_OUT_COMP_DOUT_DIG1_VAL,
/**
* @A : iofuncmask0[16]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : antenna_sel
* @(A=1) & (B=0) : lcd_de_or_erd
* @(A=0) & (B=1) : grant_ble
*/
GPIO_IOMAP_OUT_ANTENNA_SEL_VAL,
/**
* @A : iofuncmask0[17]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : pa_en
* @(A=1) & (B=0) : lcd_hsync_or_dc
* @(A=0) & (B=1) : grant_ble_switch_o
*/
GPIO_IOMAP_OUT_PA_EN_VAL,
/**
* @A : iofuncmask0[18]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : rf_ext_lna_en
* @(A=1) & (B=0) : lcd_vsync_or_cs
* @(A=0) & (B=1) : grant_wifi_switch_o
*/
GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL,
/**
* @A : iofuncmask0[19]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : rf_tx_en_fem
* @(A=1) & (B=0) : lcd_dotclk_or_rwr
* @(A=0) & (B=1) : rf_switch_en1
*/
GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL,
/**
* @A : iofuncmask0[15]
*
* @(A=0): rf_rx_en_fem
* @(A=1): rf_switch_en0
*/
GPIO_IOMAP_OUT_RF_RX_EN_FEM_VAL,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_LCD_DATA_O_1,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_LCD_DATA_O_2,
/**
* @A : iofuncmask0[21]
* @B : iofuncmask0[0]
* @C : rtc_calib_oe
*
* @(A=0) & (B=0) & (C=0): uart1_rts_re_o
* @(A=1) & (B=0) & (C=0): lcd_data_o[3]
* @(A=0) & (B=1) & (C=0): dbgpath_dbgo[0]
* @(A=0) & (B=0) & (C=1): rtc_calib
*/
GPIO_IOMAP_OUT_UART1_RTS_RE_O_VAL,
/**
* @A : iofuncmask0[22]
* @B : iofuncmask0[1]
* @C : rtc_calib_oe
*
* @(A=0) & (B=0) & (C=0): uart1_cts_de_out
* @(A=1) & (B=0) & (C=0): lcd_data_o[4]
* @(A=0) & (B=1) & (C=0): dbgpath_dbgo[1]
* @(A=0) & (B=0) & (C=1): rtc_calib_pul
*/
GPIO_IOMAP_OUT_UART1_CTS_DE_OUT_VAL,
/**
* @A : iofuncmask0[23]
*
* @(A=0): uart1_out
* @(A=1): lcd_data_o[5]
*/
GPIO_IOMAP_OUT_UART1_OUT_VAL,
/**
* @A : iofuncmask0[2]
*
* @(A=0): uart0_rts_re_o
* @(A=1): dbgpath_dbgo[2]
*/
GPIO_IOMAP_OUT_UART0_RTS_RE_O,
/**
* @A : iofuncmask0[3]
*
* @(A=0): uart0_cts_de_out
* @(A=1): dbgpath_dbgo[3]
*/
GPIO_IOMAP_OUT_UART0_CTS_DE_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_UART0_TX,
/**
* @A : Iofuncmask0[24]
*
* @(A=0): stmr3_pwm_out
* @(A=1): lcd_data_o[6]
*/
GPIO_IOMAP_OUT_STMR3_PWM_OUT_VAL,
/**
* @A : Iofuncmask0[25]
*
* @(A=0): stmr2_pwm_out
* @(A=1): lcd_data_o[7]
*/
GPIO_IOMAP_OUT_STMR2_PWM_OUT_VAL,
/**
* @A : Iofuncmask0[26]
*
* @(A=0): stmr1_pwm_out
* @(A=1): lcd_data_o[8]
*/
GPIO_IOMAP_OUT_STMR1_PWM_OUT_VAL,
/**
* @A : Iofuncmask0[27]
*
* @(A=0): stmr0_pwm_out
* @(A=1): lcd_data_o[9]
*/
GPIO_IOMAP_OUT_STMR0_PWM_OUT_VAL,
/**
* @A : Iofuncmask0[28]
*
* @(A=0): stmr4_pwm_out
* @(A=1): lcd_data_o[10]
*/
GPIO_IOMAP_OUT_STMR4_PWM_OUT_VAL,
/**
* @A : iofuncmask1[8]
* @B : iofuncmask1[6]
*
* @(A=0) & (B=0) : stmr5_pwm_out
* @(A=1) & (B=0) : lcd_data_o[11]
* @(A=0) & (B=1) : qspi_ospi_mnt_o[6]
*/
GPIO_IOMAP_OUT_STMR5_PWM_OUT_VAL,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SDHOST_SCLK_O,
/**
* @A : mjpeg_dma_dbg[3]
*
* @(A=0): tmr3_pwm_out
* @(A=1): mjpeg_dma_dbg[0]
*/
GPIO_IOMAP_OUT_TMR3_PWM_OUT,
/**
* @A : usb20_phy_cfg3[22]
* @B : mjpeg_dma_dbg[3]
*
* @(A=0) & (B=0) : tmr2_pwm_out
* @(A=1) & (B=0) : comp_dis_dbg
* @(A=0) & (B=1) : mjpeg_dma_dbg[1]
*/
GPIO_IOMAP_OUT_TMR2_PWM_OUT,
/**
* @A : usb20_phy_cfg3[22]
* @B : mjpeg_dma_dbg[3]
*
* @(A=0) & (B=0) : tmr1_pwm_out
* @(A=1) & (B=0) : comp_clk_dbg
* @(A=0) & (B=1) : mjpeg_dma_dbg[2]
*/
GPIO_IOMAP_OUT_TMR1_PWM_OUT,
/**
* @A : mjpeg_dma_dbg[3]
*
* @(A=0): tmr0_pwm_out
* @(A=1): lcd_data_o[12]
*/
GPIO_IOMAP_OUT_TMR0_PWM_OUT,
/**
* @A : iofuncmask0[4]
*
* @(A=0): led_tmr0_pwm_out
* @(A=1): dbgpath_dbgo[4]
*/
GPIO_IOMAP_OUT_LED_TMR0_PWM_OUT,
/**
* @A : iofuncmask1[10]
* @B : iofuncmask0[5]
*
* @(A=0) & (B=0) : led_tmr1_pwm_out
* @(A=1) & (B=0) : lcd_data_o[13]
* @(A=0) & (B=1) : dbgpath_dbgo[5]
*/
GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT_VAL,
/**
* @A : iofuncmask1[11]
* @B : iofuncmask0[6]
*
* @(A=0) & (B=0) : led_tmr2_pwm_out
* @(A=1) & (B=0) : lcd_data_o[14]
* @(A=0) & (B=1) : dbgpath_dbgo[6]
*/
GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT_VAL,
/**
* @A : iofuncmask1[12]
* @B : iofuncmask0[7]
*
* @(A=0) & (B=0) : led_tmr3_pwm_out
* @(A=1) & (B=0) : lcd_data_o[15]
* @(A=0) & (B=1) : dbgpath_dbgo[7]
*/
GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT_VAL,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_PDM_MCLK,
/**
* @A : iofuncmask0[11]
*
* @(A=0): qspi_nss1_out
* @(A=1): ospi_cs_io
*/
GPIO_IOMAP_OUT_QSPI_NSS1_OUT_VAL,
/**
* @A : iofuncmask1[0]
*
* @(A=0): spi0_nss_out
* @(A=1): qspi_ospi_mnt_o[0]
*/
GPIO_IOMAP_OUT_SPI0_NSS_OUT,
/**
* @A : iofuncmask1[1]
*
* @(A=0): spi0_sck_out
* @(A=1): qspi_ospi_mnt_o[1]
*/
GPIO_IOMAP_OUT_SPI0_SCK_OUT,
/**
* @A : iofuncmask1[2]
*
* @(A=0): spi0_io0_out
* @(A=1): qspi_ospi_mnt_o[2]
*/
GPIO_IOMAP_OUT_SPI0_IO0_OUT,
/**
* @A : iofuncmask1[3]
*
* @(A=0): spi0_io1_out
* @(A=1): qspi_ospi_mnt_o[3]
*/
GPIO_IOMAP_OUT_SPI0_IO1_OUT,
/**
* @A : iofuncmask1[4]
*
* @(A=0): spi0_io2_out
* @(A=1): qspi_ospi_mnt_o[4]
*/
GPIO_IOMAP_OUT_SPI0_IO2_OUT,
/**
* @A : iofuncmask1[5]
*
* @(A=0): spi0_io3_out
* @(A=1): qspi_ospi_mnt_o[5]
*/
GPIO_IOMAP_OUT_SPI0_IO3_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SPI1_NSS_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SPI1_SCK_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SPI1_IO0_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SPI1_IO1_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_LCD_DATA_O_16,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_LCD_DATA_O_17,
/**
* @A : iofuncmask1[13]
*
* @(A=0): spi2_nss_out
* @(A=1): lcd_data_o[18]
*/
GPIO_IOMAP_OUT_SPI2_NSS_OUT_VAL,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SPI2_SCK_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SPI2_IO0_OUT,
/**
* @A : iofuncmask1[14]
*
* @(A=0): spi2_io1_out
* @(A=1): lcd_data_o[19]
*/
GPIO_IOMAP_OUT_SPI2_IO1_OUT_VAL,
/**
* @A : iofuncmask1[15]
*
* @(A=0): spi2_io2_out
* @(A=1): lcd_data_o[20]
*/
GPIO_IOMAP_OUT_SPI2_IO2_OUT_VAL,
/**
* @A : iofuncmask1[16]
*
* @(A=0): spi2_io3_out
* @(A=1): lcd_data_o[21]
*/
GPIO_IOMAP_OUT_SPI2_IO3_OUT_VAL,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SDHOST_CMD_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SDHOST_DAT0_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SDHOST_DAT1_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SDHOST_DAT2_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_SDHOST_DAT3_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_IIS0_MCLK_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_IIS0_WSCLK_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_IIS0_BCLK_OUT,
/**
* @NONE
*
*/
GPIO_IOMAP_OUT_IIS0_DO,
/**
* @A : iofuncmask0[31]
* @B : iofuncmask1[17]
*
* @(A=0) & (B=0) : iis1_mclk_out
* @(A=1) & (B=0) : uart5_tx
* @(A=0) & (B=1) : lcd_data_o[22]
*/
GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL,
/**
* @A : iofuncmask1[18]
*
* @(A=0): iis1_wsclk_out
* @(A=1): lcd_data_o[23]
*/
GPIO_IOMAP_OUT_IIS1_WSCLK_OUT_VAL,
/**
* @A : iofuncmask0[30]
*
* @(A=0): iis1_bclk_out
* @(A=1): spi1_io2_out
*/
GPIO_IOMAP_OUT_IIS1_BCLK_OUT_VAL,
/**
* @A : iofuncmask0[29]
*
* @(A=0): iis1_do
* @(A=1): spi1_io3_out
*/
GPIO_IOMAP_OUT_IIS1_DO_VAL,
/**
* @A : iofuncmask0[13]
*
* @(A=0): clk_to_io
* @(A=1): uart4_tx
*/
GPIO_IOMAP_OUT_CLK_TO_IO_VAL,
};
/** @defgroup Enumeration constant for GPIO IO map input function selection
* @{
*/
enum gpio_iomap_in_func{
GPIO_IOMAP_INPUT = 0xF000,
GPIO_IOMAP_IN_TMR0_CAP_IN = 0x0,
GPIO_IOMAP_IN_TMR0_SYNC_IN__EXT_RFSWITCH_EN0_IN ,
GPIO_IOMAP_IN_TMR1_CAP_IN ,
GPIO_IOMAP_IN_TMR2_CAP_IN ,
GPIO_IOMAP_IN_TMR3_CAP_IN ,
GPIO_IOMAP_IN_PDM_DATA_IN ,
GPIO_IOMAP_IN_PTA_REQ_IN ,
GPIO_IOMAP_IN_PTA_PRI_IN ,
GPIO_IOMAP_IN_FREQ_IND_IN ,
GPIO_IOMAP_IN_STMR0_CAP_IN__LCD_D3_IN_MASK1_22 ,
GPIO_IOMAP_IN_STMR1_CAP_IN__LCD_D4_IN_MASK1_23 ,
GPIO_IOMAP_IN_STMR2_CAP_IN__LCD_D5_IN_MASK1_24 ,
GPIO_IOMAP_IN_STMR3_CAP_IN__LCD_D6_IN_MASK1_25 ,
GPIO_IOMAP_IN_PORT_WKUP_IN0 ,
GPIO_IOMAP_IN_PORT_WKUP_IN1__LCD_D7_IN_MASK1_26 ,
GPIO_IOMAP_IN_PORT_WKUP_IN2__LCD_D8_IN_MASK1_27 ,
GPIO_IOMAP_IN_PORT_WKUP_IN3__LCD_TE_MASK0_10 ,
GPIO_IOMAP_IN_UART0_IN ,
GPIO_IOMAP_IN_UART0_CTS_DE_IN ,
GPIO_IOMAP_IN_UART1_IN__LCD_D9_IN_MASK1_28 ,
GPIO_IOMAP_IN_UART1_CTS_DE_IN__LCD_D10_IN_MASK1_29 ,
GPIO_IOMAP_IN_FB_IN__EXT_PA_EN__SYS_NMI ,
GPIO_IOMAP_IN_UART4_IN ,
GPIO_IOMAP_IN_LCD_D0_IN_MASK1_19 ,
GPIO_IOMAP_IN_SPI0_NSS_IN ,
GPIO_IOMAP_IN_SPI0_SCK_IN ,
GPIO_IOMAP_IN_SPI0_IO0_IN ,
GPIO_IOMAP_IN_SPI0_IO1_IN ,
GPIO_IOMAP_IN_SPI0_IO2_IN ,
GPIO_IOMAP_IN_SPI0_IO3_IN ,
GPIO_IOMAP_IN_SPI1_NSS_IN__LCD_D11_IN_MASK1_30 ,
GPIO_IOMAP_IN_SPI1_SCK_IN ,
GPIO_IOMAP_IN_SPI1_IO0_IN ,
GPIO_IOMAP_IN_SPI1_IO1_IN__LCD_D12_IN_MASK1_31 ,
GPIO_IOMAP_IN_LCD_D1_IN_MASK1_20 ,
GPIO_IOMAP_IN_LCD_D2_IN_MASK1_21 ,
GPIO_IOMAP_IN_SPI2_NSS_IN__LCD_D13_IN_MASK2_0 ,
GPIO_IOMAP_IN_SPI2_SCK_IN ,
GPIO_IOMAP_IN_SPI2_IO0_IN ,
GPIO_IOMAP_IN_SPI2_IO1_IN__LCD_D14_IN_MASK2_1 ,
GPIO_IOMAP_IN_SPI2_IO2_IN__LCD_D15_IN_MASK2_2 ,
GPIO_IOMAP_IN_SPI2_IO3_IN__LCD_D16_IN_MASK2_3 ,
GPIO_IOMAP_IN_STMR4_CAP_IN__LCD_D17_IN_MASK2_4 ,
GPIO_IOMAP_IN_STMR5_CAP_IN__LCD_D18_IN_MASK2_5 ,
GPIO_IOMAP_IN_SDHOST_CMD_IN ,
GPIO_IOMAP_IN_SDHOST_DAT0_IN ,
GPIO_IOMAP_IN_SDHOST_DAT1_IN ,
GPIO_IOMAP_IN_SDHOST_DAT2_IN ,
GPIO_IOMAP_IN_SDHOST_DAT3_IN ,
GPIO_IOMAP_IN_IIS0_MCLK_IN__LCD_D19_IN_MASK2_6 ,
GPIO_IOMAP_IN_IIS0_WSCLK_IN__LCD_D20_IN_MASK2_7 ,
GPIO_IOMAP_IN_IIS0_BCLK_IN__LCD_D21_IN_MASK2_8 ,
GPIO_IOMAP_IN_IIS0_DAT_IN ,
GPIO_IOMAP_IN_IIS1_MCLK_IN__UART5_IN__LCD_D22_IN_MASK2_9,
GPIO_IOMAP_IN_IIS1_WSCLK_IN__LCD_D23_IN_MASK2_10 ,
GPIO_IOMAP_IN_SPI1_IO2_IN__IIS1_BCLK_IN ,
GPIO_IOMAP_IN_SPI1_IO3_IN__IIS1_DAT_IN ,
};
/** @} Docxygenid_IO_function_enum*/
int32 gpio_driver_strength(uint32 pin, enum pin_driver_strength strength);
int32 gpio_set_altnt_func(uint32 pin, enum gpio_afio_set afio);
int32 gpio_iomap_output(uint32 pin, enum gpio_iomap_out_func func_sel);
int32 gpio_iomap_input(uint32 pin, enum gpio_iomap_in_func func_sel);
int32 gpio_iomap_inout(uint32 pin, enum gpio_iomap_in_func in_func_sel, enum gpio_iomap_out_func out_func_sel);
#ifdef __cplusplus
}
#endif
#endif
/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/
sdk/include/chip/txw81x/io_mask.h
+623
View File
@@ -0,0 +1,623 @@
/**
******************************************************************************
* @file sdk\include\chip\txw80x\io_mask.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2024-01-04
* @brief This file contains all the GPIO functions.
* @copyright Copyright (c) 2016-2022 HUGE-IC
******************************************************************************
* @attention
* Only used for txw81x.
*
*
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __IO_MASK_H
#define __IO_MASK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "typesdef.h"
#include "io_function.h"
#define IO_INDEX0(index) ((index&0x3)<<26)
#define IO_INDEX0_GET(io_func) ((io_func&IO_INDEX0(3))>>26)
#define IO_INDEX1(index) ((index&0x3)<<28)
#define IO_INDEX1_GET(io_func) ((io_func&IO_INDEX1(3))>>28)
#define IO_INDEX2(index) ((index&0x3)<<30)
#define IO_INDEX2_GET(io_func) ((io_func&IO_INDEX2(3))>>30)
#define IO_FUNC(func) ((func&0xFF)<<0)
#define IO_INDEX0_BIT_SITE (8)
#define IO_INDEX0_BIT_WIDTH (5)
#define IO_INDEX0_VAL_SITE (13)
#define IO_INDEX0_VAL_WIDTH (1)
#define IO_INDEX0_SET_VAL(val) ((val&0x01)<<IO_INDEX0_VAL_SITE)
#define IO_INDEX0_SET_BIT(bit) ((bit&0x1F)<<IO_INDEX0_BIT_SITE)
#define IO_INDEX0_SET(mask, val, bit) (IO_INDEX0(mask) | IO_INDEX0_SET_VAL(val) | IO_INDEX0_SET_BIT(bit))
#define IO_INDEX0_GET_VAL(io_func) ((io_func & IO_INDEX0_SET_VAL(0x01)) >> IO_INDEX0_VAL_SITE)
#define IO_INDEX0_GET_BIT(io_func) ((io_func & IO_INDEX0_SET_BIT(0x1F)) >> IO_INDEX0_BIT_SITE)
#define IO_INDEX1_BIT_SITE (14)
#define IO_INDEX1_BIT_WIDTH (5)
#define IO_INDEX1_VAL_SITE (19)
#define IO_INDEX1_VAL_WIDTH (1)
#define IO_INDEX1_SET_VAL(val) ((val&0x01)<<IO_INDEX1_VAL_SITE)
#define IO_INDEX1_SET_BIT(bit) ((bit&0x1F)<<IO_INDEX1_BIT_SITE)
#define IO_INDEX1_SET(mask, val, bit) (IO_INDEX1(mask) | IO_INDEX1_SET_VAL(val) | IO_INDEX1_SET_BIT(bit))
#define IO_INDEX1_GET_VAL(io_func) ((io_func & IO_INDEX1_SET_VAL(0x01)) >> IO_INDEX1_VAL_SITE)
#define IO_INDEX1_GET_BIT(io_func) ((io_func & IO_INDEX1_SET_BIT(0x1F)) >> IO_INDEX1_BIT_SITE)
#define IO_INDEX2_BIT_SITE (20)
#define IO_INDEX2_BIT_WIDTH (5)
#define IO_INDEX2_VAL_SITE (25)
#define IO_INDEX2_VAL_WIDTH (1)
#define IO_INDEX2_SET_VAL(val) ((val&0x01)<<IO_INDEX2_VAL_SITE)
#define IO_INDEX2_SET_BIT(bit) ((bit&0x1F)<<IO_INDEX2_BIT_SITE)
#define IO_INDEX2_SET(mask, val, bit) (IO_INDEX2(mask) | IO_INDEX2_SET_VAL(val) | IO_INDEX2_SET_BIT(bit))
#define IO_INDEX2_GET_VAL(io_func) ((io_func & IO_INDEX2_SET_VAL(0x01)) >> IO_INDEX2_VAL_SITE)
#define IO_INDEX2_GET_BIT(io_func) ((io_func & IO_INDEX2_SET_BIT(0x1F)) >> IO_INDEX2_BIT_SITE)
#define IO_MASK(set, func) ((set) | (func))
/**
* @A : iofuncmask0[14]
* @B : iofuncmask0[8]
*
* @(A=0) & (B=0) : comp_dout_dig0
* @(A=1) & (B=0) : ospi_cs_io
* @(A=0) & (B=1) : dbgpath_dbgo[8]
*/
enum IOMASK_GPIO_IOMAP_OUT_COMP_DOUT_DIG0 {
GPIO_IOMAP_OUT_COMP_DOUT_DIG0 = IO_MASK(IO_INDEX0_SET(0, 0, 14) |\
IO_INDEX1_SET(0, 0, 8) |\
IO_INDEX2_SET(0, 0, 8) ,
IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG0_VAL)),
GPIO_IOMAP_OUT_OSPI_CS_IO = IO_MASK(IO_INDEX0_SET(0, 1, 14) |\
IO_INDEX1_SET(0, 0, 8) |\
IO_INDEX2_SET(0, 0, 8) ,
IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG0_VAL)),
};
/**
* @A : iofuncmask0[20]
* @B : iofuncmask0[9]
*
* @(A=0) & (B=0) : comp_dout_dig1
* @(A=1) & (B=0) : lcd_data_o[0]
* @(A=0) & (B=1) : dbgpath_dbgo[9]
*/
enum IOMASK_GPIO_IOMAP_OUT_COMP_DOUT_DIG1 {
GPIO_IOMAP_OUT_COMP_DOUT_DIG1 = IO_MASK(IO_INDEX0_SET(0, 0, 20) |\
IO_INDEX1_SET(0, 0, 9) |\
IO_INDEX2_SET(0, 0, 9) ,
IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG1_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_0 = IO_MASK(IO_INDEX0_SET(0, 1, 20) |\
IO_INDEX1_SET(0, 0, 9) |\
IO_INDEX2_SET(0, 0, 9) ,
IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG1_VAL)),
};
/**
* @A : iofuncmask0[16]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : antenna_sel
* @(A=1) & (B=0) : lcd_de_or_erd
* @(A=0) & (B=1) : grant_ble
*/
enum IOMASK_GPIO_IOMAP_OUT_ANTENNA_SEL {
GPIO_IOMAP_OUT_ANTENNA_SEL = IO_MASK(IO_INDEX0_SET(0, 0, 16) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_ANTENNA_SEL_VAL)),
GPIO_IOMAP_OUT_LCD_DE_OR_ERD = IO_MASK(IO_INDEX0_SET(0, 1, 16) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_ANTENNA_SEL_VAL)),
GPIO_IOMAP_OUT_GRANT_BLE = IO_MASK(IO_INDEX0_SET(0, 0, 16) |\
IO_INDEX1_SET(0, 1, 15) |\
IO_INDEX2_SET(0, 1, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_ANTENNA_SEL_VAL)),
};
/**
* @A : iofuncmask0[17]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : pa_en
* @(A=1) & (B=0) : lcd_hsync_or_dc
* @(A=0) & (B=1) : grant_ble_switch_o
*/
enum IOMASK_GPIO_IOMAP_OUT_PA_EN {
GPIO_IOMAP_OUT_PA_EN = IO_MASK(IO_INDEX0_SET(0, 0, 17) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_PA_EN_VAL)),
GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC = IO_MASK(IO_INDEX0_SET(0, 1, 17) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_PA_EN_VAL)),
GPIO_IOMAP_OUT_GRANT_BLE_SWITCH_O = IO_MASK(IO_INDEX0_SET(0, 0, 17) |\
IO_INDEX1_SET(0, 1, 15) |\
IO_INDEX2_SET(0, 1, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_PA_EN_VAL)),
};
/**
* @A : iofuncmask0[18]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : rf_ext_lna_en
* @(A=1) & (B=0) : lcd_vsync_or_cs
* @(A=0) & (B=1) : grant_wifi_switch_o
*/
enum IOMASK_GPIO_IOMAP_OUT_RF_EXT_LNA_EN {
GPIO_IOMAP_OUT_RF_EXT_LNA_EN = IO_MASK(IO_INDEX0_SET(0, 0, 18) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL)),
GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS = IO_MASK(IO_INDEX0_SET(0, 1, 18) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL)),
GPIO_IOMAP_OUT_GRANT_WIFI_SWITCH_O = IO_MASK(IO_INDEX0_SET(0, 0, 18) |\
IO_INDEX1_SET(0, 1, 15) |\
IO_INDEX2_SET(0, 1, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL)),
};
/**
* @A : iofuncmask0[19]
* @B : iofuncmask0[15]
*
* @(A=0) & (B=0) : rf_tx_en_fem
* @(A=1) & (B=0) : lcd_dotclk_or_rwr
* @(A=0) & (B=1) : rf_switch_en1
*/
enum IOMASK_GPIO_IOMAP_OUT_RF_TX_EN_FEM {
GPIO_IOMAP_OUT_RF_TX_EN_FEM = IO_MASK(IO_INDEX0_SET(0, 0, 19) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL)),
GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR = IO_MASK(IO_INDEX0_SET(0, 1, 19) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL)),
GPIO_IOMAP_OUT_RF_SWITCH_EN1 = IO_MASK(IO_INDEX0_SET(0, 0, 19) |\
IO_INDEX1_SET(0, 1, 15) |\
IO_INDEX2_SET(0, 1, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL)),
};
/**
* @A : iofuncmask0[15]
*
* @(A=0): rf_rx_en_fem
* @(A=1): rf_switch_en0
*/
enum IOMASK_GPIO_IOMAP_OUT_RF_RX_EN_FEM {
GPIO_IOMAP_OUT_RF_RX_EN_FEM = IO_MASK(IO_INDEX0_SET(0, 0, 15) |\
IO_INDEX1_SET(0, 0, 15) |\
IO_INDEX2_SET(0, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_RX_EN_FEM_VAL)),
GPIO_IOMAP_OUT_RF_SWITCH_EN0 = IO_MASK(IO_INDEX0_SET(0, 1, 15) |\
IO_INDEX1_SET(0, 1, 15) |\
IO_INDEX2_SET(0, 1, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_RF_RX_EN_FEM_VAL)),
};
/**
* @A : iofuncmask0[21]
* @B : iofuncmask0[0]
* @C : rtc_calib_oe
*
* @(A=0) & (B=0) & (C=0): uart1_rts_re_o
* @(A=1) & (B=0) & (C=0): lcd_data_o[3]
* @(A=0) & (B=1) & (C=0): dbgpath_dbgo[0]
* @(A=0) & (B=0) & (C=1): rtc_calib
*/
enum IOMASK_GPIO_IOMAP_OUT_UART1_RTS_RE_O {
GPIO_IOMAP_OUT_UART1_RTS_RE_O = IO_MASK(IO_INDEX0_SET(0, 0, 21) |\
IO_INDEX1_SET(0, 0, 0) |\
IO_INDEX2_SET(0, 0, 0) ,
IO_FUNC(GPIO_IOMAP_OUT_UART1_RTS_RE_O_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_3 = IO_MASK(IO_INDEX0_SET(0, 1, 21) |\
IO_INDEX1_SET(0, 0, 0) |\
IO_INDEX2_SET(0, 0, 0) ,
IO_FUNC(GPIO_IOMAP_OUT_UART1_RTS_RE_O_VAL)),
};
/**
* @A : iofuncmask0[22]
* @B : iofuncmask0[1]
* @C : rtc_calib_oe
*
* @(A=0) & (B=0) & (C=0): uart1_cts_de_out
* @(A=1) & (B=0) & (C=0): lcd_data_o[4]
* @(A=0) & (B=1) & (C=0): dbgpath_dbgo[1]
* @(A=0) & (B=0) & (C=1): rtc_calib_pul
*/
enum IOMASK_GPIO_IOMAP_OUT_UART1_CTS_DE_OUT {
GPIO_IOMAP_OUT_UART1_CTS_DE_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 22) |\
IO_INDEX1_SET(0, 0, 1) |\
IO_INDEX2_SET(0, 0, 1) ,
IO_FUNC(GPIO_IOMAP_OUT_UART1_CTS_DE_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_4 = IO_MASK(IO_INDEX0_SET(0, 1, 22) |\
IO_INDEX1_SET(0, 0, 1) |\
IO_INDEX2_SET(0, 0, 1) ,
IO_FUNC(GPIO_IOMAP_OUT_UART1_CTS_DE_OUT_VAL)),
};
/**
* @A : iofuncmask0[23]
*
* @(A=0): uart1_out
* @(A=1): lcd_data_o[5]
*/
enum IOMASK_GPIO_IOMAP_OUT_UART1_OUT {
GPIO_IOMAP_OUT_UART1_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 23) |\
IO_INDEX1_SET(0, 0, 23) |\
IO_INDEX2_SET(0, 0, 23) ,
IO_FUNC(GPIO_IOMAP_OUT_UART1_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_5 = IO_MASK(IO_INDEX0_SET(0, 1, 23) |\
IO_INDEX1_SET(0, 1, 23) |\
IO_INDEX2_SET(0, 1, 23) ,
IO_FUNC(GPIO_IOMAP_OUT_UART1_OUT_VAL)),
};
/**
* @A : Iofuncmask0[24]
*
* @(A=0): stmr3_pwm_out
* @(A=1): lcd_data_o[6]
*/
enum IOMASK_GPIO_IOMAP_OUT_STMR3_PWM_OUT {
GPIO_IOMAP_OUT_STMR3_PWM_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 24) |\
IO_INDEX1_SET(0, 0, 24) |\
IO_INDEX2_SET(0, 0, 24) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR3_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_6 = IO_MASK(IO_INDEX0_SET(0, 1, 24) |\
IO_INDEX1_SET(0, 1, 24) |\
IO_INDEX2_SET(0, 1, 24) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR3_PWM_OUT_VAL)),
};
/**
* @A : Iofuncmask0[25]
*
* @(A=0): stmr2_pwm_out
* @(A=1): lcd_data_o[7]
*/
enum IOMASK_GPIO_IOMAP_OUT_STMR2_PWM_OUT {
GPIO_IOMAP_OUT_STMR2_PWM_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 25) |\
IO_INDEX1_SET(0, 0, 25) |\
IO_INDEX2_SET(0, 0, 25) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR2_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_7 = IO_MASK(IO_INDEX0_SET(0, 1, 25) |\
IO_INDEX1_SET(0, 1, 25) |\
IO_INDEX2_SET(0, 1, 25) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR2_PWM_OUT_VAL)),
};
/**
* @A : Iofuncmask0[26]
*
* @(A=0): stmr1_pwm_out
* @(A=1): lcd_data_o[8]
*/
enum IOMASK_GPIO_IOMAP_OUT_STMR1_PWM_OUT {
GPIO_IOMAP_OUT_STMR1_PWM_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 26) |\
IO_INDEX1_SET(0, 0, 26) |\
IO_INDEX2_SET(0, 0, 26) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR1_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_8 = IO_MASK(IO_INDEX0_SET(0, 1, 26) |\
IO_INDEX1_SET(0, 1, 26) |\
IO_INDEX2_SET(0, 1, 26) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR1_PWM_OUT_VAL)),
};
/**
* @A : Iofuncmask0[27]
*
* @(A=0): stmr0_pwm_out
* @(A=1): lcd_data_o[9]
*/
enum IOMASK_GPIO_IOMAP_OUT_STMR0_PWM_OUT {
GPIO_IOMAP_OUT_STMR0_PWM_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 27) |\
IO_INDEX1_SET(0, 0, 27) |\
IO_INDEX2_SET(0, 0, 27) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR0_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_9 = IO_MASK(IO_INDEX0_SET(0, 1, 27) |\
IO_INDEX1_SET(0, 1, 27) |\
IO_INDEX2_SET(0, 1, 27) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR0_PWM_OUT_VAL)),
};
/**
* @A : Iofuncmask0[28]
*
* @(A=0): stmr4_pwm_out
* @(A=1): lcd_data_o[10]
*/
enum IOMASK_GPIO_IOMAP_OUT_STMR4_PWM_OUT {
GPIO_IOMAP_OUT_STMR4_PWM_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 28) |\
IO_INDEX1_SET(0, 0, 28) |\
IO_INDEX2_SET(0, 0, 28) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR4_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_10 = IO_MASK(IO_INDEX0_SET(0, 1, 28) |\
IO_INDEX1_SET(0, 1, 28) |\
IO_INDEX2_SET(0, 1, 28) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR4_PWM_OUT_VAL)),
};
/**
* @A : iofuncmask1[8]
* @B : iofuncmask1[6]
*
* @(A=0) & (B=0) : stmr5_pwm_out
* @(A=1) & (B=0) : lcd_data_o[11]
* @(A=0) & (B=1) : qspi_ospi_mnt_o[6]
*/
enum IOMASK_GPIO_IOMAP_OUT_STMR5_PWM_OUT {
GPIO_IOMAP_OUT_STMR5_PWM_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 8) |\
IO_INDEX1_SET(1, 0, 6) |\
IO_INDEX2_SET(1, 0, 6) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR5_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_11 = IO_MASK(IO_INDEX0_SET(1, 1, 8) |\
IO_INDEX1_SET(1, 0, 6) |\
IO_INDEX2_SET(1, 0, 6) ,
IO_FUNC(GPIO_IOMAP_OUT_STMR5_PWM_OUT_VAL)),
};
/**
* @A : iofuncmask1[10]
* @B : iofuncmask0[5]
*
* @(A=0) & (B=0) : led_tmr1_pwm_out
* @(A=1) & (B=0) : lcd_data_o[13]
* @(A=0) & (B=1) : dbgpath_dbgo[5]
*/
enum IOMASK_GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT {
GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 10) |\
IO_INDEX1_SET(0, 0, 5) |\
IO_INDEX2_SET(0, 0, 5) ,
IO_FUNC(GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_13 = IO_MASK(IO_INDEX0_SET(1, 1, 10) |\
IO_INDEX1_SET(0, 0, 5) |\
IO_INDEX2_SET(0, 0, 5) ,
IO_FUNC(GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT_VAL)),
};
/**
* @A : iofuncmask1[11]
* @B : iofuncmask0[6]
*
* @(A=0) & (B=0) : led_tmr2_pwm_out
* @(A=1) & (B=0) : lcd_data_o[14]
* @(A=0) & (B=1) : dbgpath_dbgo[6]
*/
enum IOMASK_GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT {
GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 11) |\
IO_INDEX1_SET(0, 0, 6) |\
IO_INDEX2_SET(0, 0, 6) ,
IO_FUNC(GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_14 = IO_MASK(IO_INDEX0_SET(1, 1, 11) |\
IO_INDEX1_SET(0, 0, 6) |\
IO_INDEX2_SET(0, 0, 6) ,
IO_FUNC(GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT_VAL)),
};
/**
* @A : iofuncmask1[12]
* @B : iofuncmask0[7]
*
* @(A=0) & (B=0) : led_tmr3_pwm_out
* @(A=1) & (B=0) : lcd_data_o[15]
* @(A=0) & (B=1) : dbgpath_dbgo[7]
*/
enum IOMASK_GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT {
GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 12) |\
IO_INDEX1_SET(0, 0, 7) |\
IO_INDEX2_SET(0, 0, 7) ,
IO_FUNC(GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_15 = IO_MASK(IO_INDEX0_SET(1, 1, 12) |\
IO_INDEX1_SET(0, 0, 7) |\
IO_INDEX2_SET(0, 0, 7) ,
IO_FUNC(GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT_VAL)),
};
/**
* @A : iofuncmask0[11]
*
* @(A=0): qspi_nss1_out
* @(A=1): ospi_cs_io
*/
enum IOMASK_GPIO_IOMAP_OUT_QSPI_NSS1_OUT {
GPIO_IOMAP_OUT_QSPI_NSS1_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 11) |\
IO_INDEX1_SET(0, 0, 11) |\
IO_INDEX2_SET(0, 0, 11) ,
IO_FUNC(GPIO_IOMAP_OUT_QSPI_NSS1_OUT_VAL)),
GPIO_IOMAP_OUT_OSPI_CS_IO_ = IO_MASK(IO_INDEX0_SET(0, 1, 11) |\
IO_INDEX1_SET(0, 1, 11) |\
IO_INDEX2_SET(0, 1, 11) ,
IO_FUNC(GPIO_IOMAP_OUT_QSPI_NSS1_OUT_VAL)),
};
/**
* @A : iofuncmask1[13]
*
* @(A=0): spi2_nss_out
* @(A=1): lcd_data_o[18]
*/
enum IOMASK_GPIO_IOMAP_OUT_SPI2_NSS_OUT {
GPIO_IOMAP_OUT_SPI2_NSS_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 13) |\
IO_INDEX1_SET(1, 0, 13) |\
IO_INDEX2_SET(1, 0, 13) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_NSS_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_18 = IO_MASK(IO_INDEX0_SET(1, 1, 13) |\
IO_INDEX1_SET(1, 1, 13) |\
IO_INDEX2_SET(1, 1, 13) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_NSS_OUT_VAL)),
};
/**
* @A : iofuncmask1[14]
*
* @(A=0): spi2_io1_out
* @(A=1): lcd_data_o[19]
*/
enum IOMASK_GPIO_IOMAP_OUT_SPI2_IO1_OUT {
GPIO_IOMAP_OUT_SPI2_IO1_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 14) |\
IO_INDEX1_SET(1, 0, 14) |\
IO_INDEX2_SET(1, 0, 14) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO1_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_19 = IO_MASK(IO_INDEX0_SET(1, 1, 14) |\
IO_INDEX1_SET(1, 1, 14) |\
IO_INDEX2_SET(1, 1, 14) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO1_OUT_VAL)),
};
/**
* @A : iofuncmask1[15]
*
* @(A=0): spi2_io2_out
* @(A=1): lcd_data_o[20]
*/
enum IOMASK_GPIO_IOMAP_OUT_SPI2_IO2_OUT {
GPIO_IOMAP_OUT_SPI2_IO2_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 15) |\
IO_INDEX1_SET(1, 0, 15) |\
IO_INDEX2_SET(1, 0, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO2_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_20 = IO_MASK(IO_INDEX0_SET(1, 1, 15) |\
IO_INDEX1_SET(1, 1, 15) |\
IO_INDEX2_SET(1, 1, 15) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO2_OUT_VAL)),
};
/**
* @A : iofuncmask1[16]
*
* @(A=0): spi2_io3_out
* @(A=1): lcd_data_o[21]
*/
enum IOMASK_GPIO_IOMAP_OUT_SPI2_IO3_OUT {
GPIO_IOMAP_OUT_SPI2_IO3_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 16) |\
IO_INDEX1_SET(1, 0, 16) |\
IO_INDEX2_SET(1, 0, 16) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO3_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_21 = IO_MASK(IO_INDEX0_SET(1, 1, 16) |\
IO_INDEX1_SET(1, 1, 16) |\
IO_INDEX2_SET(1, 1, 16) ,
IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO3_OUT_VAL)),
};
/**
* @A : iofuncmask0[31]
* @B : iofuncmask1[17]
*
* @(A=0) & (B=0) : iis1_mclk_out
* @(A=1) & (B=0) : uart5_tx
* @(A=0) & (B=1) : lcd_data_o[22]
*/
enum IOMASK_GPIO_IOMAP_OUT_IIS1_MCLK_OUT {
GPIO_IOMAP_OUT_IIS1_MCLK_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 31) |\
IO_INDEX1_SET(1, 0, 17) |\
IO_INDEX2_SET(1, 0, 17) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL)),
GPIO_IOMAP_OUT_UART5_TX = IO_MASK(IO_INDEX0_SET(0, 1, 31) |\
IO_INDEX1_SET(1, 0, 17) |\
IO_INDEX2_SET(1, 0, 17) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_22 = IO_MASK(IO_INDEX0_SET(0, 0, 31) |\
IO_INDEX1_SET(1, 1, 17) |\
IO_INDEX2_SET(1, 1, 17) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL)),
};
/**
* @A : iofuncmask1[18]
*
* @(A=0): iis1_wsclk_out
* @(A=1): lcd_data_o[23]
*/
enum IOMASK_GPIO_IOMAP_OUT_IIS1_WSCLK_OUT {
GPIO_IOMAP_OUT_IIS1_WSCLK_OUT = IO_MASK(IO_INDEX0_SET(1, 0, 18) |\
IO_INDEX1_SET(1, 0, 18) |\
IO_INDEX2_SET(1, 0, 18) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_WSCLK_OUT_VAL)),
GPIO_IOMAP_OUT_LCD_DATA_O_23 = IO_MASK(IO_INDEX0_SET(1, 1, 18) |\
IO_INDEX1_SET(1, 1, 18) |\
IO_INDEX2_SET(1, 1, 18) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_WSCLK_OUT_VAL)),
};
/**
* @A : iofuncmask0[30]
*
* @(A=0): iis1_bclk_out
* @(A=1): spi1_io2_out
*/
enum IOMASK_GPIO_IOMAP_OUT_IIS1_BCLK_OUT {
GPIO_IOMAP_OUT_IIS1_BCLK_OUT = IO_MASK(IO_INDEX0_SET(0, 0, 30) |\
IO_INDEX1_SET(0, 0, 30) |\
IO_INDEX2_SET(0, 0, 30) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_BCLK_OUT_VAL)),
GPIO_IOMAP_OUT_SPI1_IO2_OUT = IO_MASK(IO_INDEX0_SET(0, 1, 30) |\
IO_INDEX1_SET(0, 1, 30) |\
IO_INDEX2_SET(0, 1, 30) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_BCLK_OUT_VAL)),
};
/**
* @A : iofuncmask0[29]
*
* @(A=0): iis1_do
* @(A=1): spi1_io3_out
*/
enum IOMASK_GPIO_IOMAP_OUT_IIS1_DO {
GPIO_IOMAP_OUT_IIS1_DO = IO_MASK(IO_INDEX0_SET(0, 0, 29) |\
IO_INDEX1_SET(0, 0, 29) |\
IO_INDEX2_SET(0, 0, 29) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_DO_VAL)),
GPIO_IOMAP_OUT_SPI1_IO3_OUT = IO_MASK(IO_INDEX0_SET(0, 1, 29) |\
IO_INDEX1_SET(0, 1, 29) |\
IO_INDEX2_SET(0, 1, 29) ,
IO_FUNC(GPIO_IOMAP_OUT_IIS1_DO_VAL)),
};
/**
* @A : iofuncmask0[13]
*
* @(A=0): clk_to_io
* @(A=1): uart4_tx
*/
enum IOMASK_GPIO_IOMAP_OUT_CLK_TO_IO {
GPIO_IOMAP_OUT_CLK_TO_IO = IO_MASK(IO_INDEX0_SET(0, 0, 13) |\
IO_INDEX1_SET(0, 0, 13) |\
IO_INDEX2_SET(0, 0, 13) ,
IO_FUNC(GPIO_IOMAP_OUT_CLK_TO_IO_VAL)),
GPIO_IOMAP_OUT_UART4_TX = IO_MASK(IO_INDEX0_SET(0, 1, 13) |\
IO_INDEX1_SET(0, 1, 13) |\
IO_INDEX2_SET(0, 1, 13) ,
IO_FUNC(GPIO_IOMAP_OUT_CLK_TO_IO_VAL)),
};
#ifdef __cplusplus
}
#endif
#endif
/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/
sdk/include/chip/txw81x/misc.h
+356
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@@ -0,0 +1,356 @@
/**
******************************************************************************
* @file misc.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2021.01.14
* @brief This file contains all the PowerDomain firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
*
*
* Revision History
* V1.0.0 2021.01.14 First Release, move from sysctrl
*
******************************************************************************
*/
#ifndef __MISC_H__
#define __MISC_H__
#include "typesdef.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef VENUS_END
/*******************************************************************/
/* Venus to be continue */
/*******************************************************************/
#endif
/**
* @}
*/
///** @defgroup SYSMONITOR MACRO-DEF & Exported_Functions
// * @{
// */
typedef struct
{
__IO uint32 CHx_LMT_L;
__IO uint32 CHx_LMT_H;
__IO uint32 CHx_ERR_ADR;
// uint32 RESERVEDx;
} SYS_MNT_CH_TypeDef;
typedef struct
{
__IO uint32 CTRL;
__IO uint32 PND;
__IO uint32 CLR;
__IO uint32 RD;
__IO uint32 WR;
__IO uint32 CPU_PC0;
__IO uint32 CPU_PC1;
__IO uint32 CPU_PC2;
__IO uint32 CPU_PC3;
SYS_MNT_CH_TypeDef SYS_MNT_CH;
} SYS_MNT_TypeDef;
#define SYSMNT ((SYS_MNT_TypeDef *) SYS_MNT_BASE)
/** @addtogroup Template_Project
* @{
*/
#define LL_SYSMONITOR_CHN_EN(n) (BIT(n))
#define LL_SYSMONITOR_CHN_CAP_RANGE_INTER(n) (BIT(n+4))
#define LL_SYSMONITOR_CHN_CAP_RANGE_OUTER(n) (0)
#define LL_SYSMONITOR_CAP_PC_EN (1UL << 6)
#define LL_SYSMONITOR_INT_EN (1UL << 7)
#define LL_SYSMONITOR_CH0_SEL(n) (((n) & 0x1F) << 8)
#define LL_SYSMONITOR_CH0_SEL_MSK ((0x1F) << 8)
#define LL_SYSMONITOR_CH0_CAP_READ ((1UL) << 18)
#define LL_SYSMONITOR_CH0_CAP_WRITE ((1UL) << 19)
#define LL_SYSMONITOR_CH0_CAP_MODE(n) ((((n) & 0x3)) << 18)
#define LL_SYSMONITOR_CLEAR_REGISTER() do { SYSMNT->CLR = 1; } while(0)
/** @addtogroup XXX
* @{
*/
typedef enum {
LL_SYSMONITOR_CHN_LMAC_WAVE_TX = (0),
LL_SYSMONITOR_CHN_LMAC_WAVE_RX = (1),
LL_SYSMONITOR_CHN_LMAC_TX = (2),
LL_SYSMONITOR_CHN_LMAC_RX = (3),
LL_SYSMONITOR_CHN_SDIO = (4),
LL_SYSMONITOR_CHN_USB20 = (5),
LL_SYSMONITOR_CHN_USB11 = (6),
LL_SYSMONITOR_CHN_GMAC_RX = (7),
LL_SYSMONITOR_CHN_GMAC_TX = (8),
LL_SYSMONITOR_CHN_CPU_I_CODE_BUS = (9),
LL_SYSMONITOR_CHN_CPU_D_CODE_BUS = (10),
LL_SYSMONITOR_CHN_CPU_SYSBUS_BUS = (11),
} TYPE_ENUM_LL_SYSMONITOR_CH;
/** @addtogroup XXX
* @{
*/
typedef enum {
LL_SYSMONITOR_CAP_RANGE_INTER = (0),
LL_SYSMONITOR_CAP_RANGE_OUTER = (1),
} TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE;
/** @addtogroup XXX
* @{
*/
typedef enum {
LL_SYSMONITOR_CAP_MODE_READ = (1),
LL_SYSMONITOR_CAP_MODE_WRITE = (2),
LL_SYSMONITOR_CAP_MODE_READ_OR_WRITE = (3),
} TYPE_ENUM_LL_SYSMONITOR_CAP_MODE;
typedef struct __ll_sysmonitor_cfg {
/*! System monitor interrupt enable
*/
bool int_en;
/*! System monitor sub channel : [0, 20]
*/
TYPE_ENUM_LL_SYSMONITOR_CH sub_chn;
/*! capture mode
*/
TYPE_ENUM_LL_SYSMONITOR_CAP_MODE cap_mode;
/*! capture range
*/
TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE cap_range;
/*! Chx low limited address
*/
uint32 chx_limit_low;
/*! Chx high limited address
*/
uint32 chx_limit_high;
} TYPE_SYSMONITOR_CFG;
void sys_monitor_config(TYPE_SYSMONITOR_CFG *p_cfg);
void sys_monitor_reset(void);
/**
* @}
*/
/** @defgroup EFUSE MACRO-DEF & Exported_Functions
* @{
*/
typedef struct
{
__IO uint32 EFUSE_CON;
__IO uint32 EFUSE_TIME_CON0;
__IO uint32 EFUSE_TIME_CON1;
__IO uint32 EFUSE_TIME_CON2;
__IO uint32 EFUSE_STATUS;
__IO uint32 EFUSE_ADDR_CNT;
__IO uint32 EFUSE_DATA;
} EFUSE_TypeDef;
#define EFUSE ((EFUSE_TypeDef *) EFUSE_BASE)
/* efuse timing define */
#define LL_EFUSE_POWER_FREQ 100000 /* 10us */
#define LL_EFUSE_PROGRAM_FREQ 100000 /* 10us (9~11uS) */
#define LL_EFUSE_READ_FREQ 10000000 /* 100ns ( > 36ns) */
uint16 sysctrl_efuse_config_and_read(uint32 addr, uint8 *p_buf, uint16 len);
void rf_para_efuse_check_valid(void);
void sysctrl_efuse_mac_addr_calc(uint8 *addr_buf);
void sysctrl_efuse_mac_addr_calc_uuid(uint8 *addr_buf);
uint16 sysctrl_efuse_get_customer_id(void);
uint32 sysctrl_efuse_get_smt_dat(void);
int32 tsensor_meas(uint8 sensor_idx);
/*******************************************************************/
/* RFADC */
/*******************************************************************/
typedef struct {
__IO uint32 RFADCDIGCON;
} RFADCDIG_TypeDef;
#define RFADCDIG ((RFADCDIG_TypeDef *) RFADCDIG_BASE)
#define RFADCDIGCON_ACS_ON_MSK BIT(0)
#define RFADCDIGCON_ACS_RW_MSK BIT(1)
#define RFADCDIGCON_ACS_ADDR_SHIFT 2
#define RFADCDIGCON_ACS_ADDR_MSK (0x1f<<RFADCDIGCON_ACS_ADDR_SHIFT)
#define RFADCDIGCON_ACS_DATA_SHIFT 7
#define RFADCDIGCON_ACS_DATA_MSK (0x3fffff<<RFADCDIGCON_ACS_DATA_SHIFT)
#define ADCOUTSEL 0 // 0: output data after calibration; 1: output data before calibration
/*******************************************************************/
/* RFADC */
/*******************************************************************/
enum lf_clk_src {
FROM_HOSC = 0,
FROM_RC32K = 2,
FROM_PB0 = 3,
};
enum lf_clk_count {
_1024_CYCLE = 0,
_512_CYCLE = 1,
_256_CYCLE = 2,
_128_CYCLE = 3,
_64_CYCLE = 4,
_32_CYCLE = 5,
_16_CYCLE = 6,
_8_CYCLE = 7,
};
enum dac_default_state {
POWER_OFF = 0,
SLEEP = 1,
STAND_BY = 2,
POWER_ON = 3
};
enum rf_bw {
BW_1M = 0,
BW_2M = 1,
BW_4M = 2,
BW_8M = 3
};
enum rf_parameter_type {
RF_EFUSE_ALL_SIM = 0,
ADC_CALIB_VAL = 1,
ADDA_TIM_OFFSET = 2,
TXDCOC_CALIB_VAL = 3,
TXIMB_CALIB_VAL = 4,
RXDCOC_CALIB_VAL = 5,
RXIMB_CALIB_VAL = 6
};
int32 tx_digi_gain_store(uint16 tx_digi_gain);
int32 sysctrl_internal_rf_sel_lo_freq(uint8 lo_freq_idx);
int32 is_xo_cs_calibed(void);
int32 is_xo_cto_calibed(void);
int32 xo_cs_store(uint8 xo_cs_val);
int32 sysctrl_get_xo_drcs(void);
int32 sysctrl_set_xo_drcs(uint16 xo_drcs);
void adc_cfg_reg_wr(uint8 addr, uint32 data);
uint32 adc_cfg_reg_rd(uint8 addr);
int32 is_adc_calibed(void);
void adc_init(void);
int32 adc_calib_res_store(void);
void adc_calib_res_restore(void);
void rfadc_calib_mode_soft_test(void);
int32 sysctrl_err_resp_icode_bus(uint8 enable);
int32 sysctrl_err_resp_dcode_bus(uint8 enable);
int32 sysctrl_err_resp_ahb2dma_bus(uint8 enable);
int32 sysctrl_err_resp_sdiodevice_bus(uint8 enable);
int32 sysctrl_err_resp_disable(void);
int32 sysctrl_get_chip_flash_size(void);
#ifdef PSRAM_HEAP
/** use when DMA source is psram
* 1、usage( this -> DMA kick)
*/
__STATIC_INLINE void sys_dcache_clean_range (uint32_t *addr, int32_t dsize)
{
if (((uint32)addr >= PSRAM_BASE) &&
((uint32)addr < PSRAM_END_ADDR) &&
csi_is_cache_enable()) {
ASSERT(!(((uint32)addr) & (BIT(CACHE_CIR_INV_ADDR_Pos)-1)));
csi_dcache_clean_range(addr, dsize);
}
}
/* usefor TCPIP CHKSUM */
__STATIC_INLINE void sys_dcache_clean_range_unaligned (uint32_t *addr, int32_t dsize)
{
if (((uint32)addr >= PSRAM_BASE) &&
((uint32)addr < PSRAM_END_ADDR) &&
csi_is_cache_enable()) {
csi_dcache_clean_range(addr, dsize);
}
}
/** use when DMA destination is psram
* 1、usage : ( this -> DMA) ;
*/
__STATIC_INLINE void sys_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
{
if (((uint32)addr >= PSRAM_BASE) &&
((uint32)addr < PSRAM_END_ADDR) &&
csi_is_cache_enable()) {
//ASSERT(!(((uint32)addr) & (BIT(CACHE_CIR_INV_ADDR_Pos)-1)));
/* data head */
if ((uint32_t)addr & 0xF) {
csi_dcache_clean_invalid_range(addr, 16);
}
/* data tail */
if (((uint32_t)addr+dsize) & 0xF) {
csi_dcache_clean_invalid_range((addr+dsize), 16);
}
/* data all */
csi_dcache_invalid_range(addr, dsize);
}
}
/** use when DMA destination is psram
* 1、usage : ( DMA done-> this) ;
* 2、Precondition: dma buffer addr & size is 16byte aligned
* 3、DMA buffer size is not checked
*/
__STATIC_INLINE void sys_dcache_invalid_range (uint32_t *addr, int32_t dsize)
{
if (((uint32)addr >= PSRAM_BASE) &&
((uint32)addr < PSRAM_END_ADDR) &&
csi_is_cache_enable()) {
//ASSERT(!(((uint32)addr) & (BIT(CACHE_CIR_INV_ADDR_Pos)-1)));
csi_dcache_invalid_range(addr, dsize);
}
}
#else
#define sys_dcache_clean_range(addr, dsize)
#define sys_dcache_clean_range_unaligned(addr, dsize)
#define sys_dcache_clean_invalid_range(addr, dsize)
#define sys_dcache_invalid_range(addr, dsize)
#endif
int32 sysctrl_is_chipdcn_compid(void);
/* 速率：x Bps */
uint32_t sys_dma2ahb_bw_static(int32 printf_en);
/* miss rate : 万分之x */
uint32_t sys_csi_cache_static(int32 printf_en);
#ifdef __cplusplus
}
#endif
#endif //__MISC_H__
/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/
sdk/include/chip/txw81x/pin_names.h
+647
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// Revision History
// V1.0.0 06/01/2019 First Release, copy from 4001a project
// V1.0.1 07/27/2019 change uart0 to A2/A3
// V1.0.2 02/07/2020 change PIN_SPI_CS to PIN_SPI0_CS
// V1.1.0 03/02/2020 add pa/pa-vmode pin
#ifndef _PIN_NAMES_DEF_H_
#define _PIN_NAMES_DEF_H_
//#include "sys_config.h"
#ifdef __cplusplus
extern "C" {
#endif
/*---------------------------------------*/
/*----------UART PIN DEFINITION----------*/
/*---------------------------------------*/
/* UART0 */
#ifndef PIN_UART0_TX
#define PIN_UART0_TX 255
#endif
#ifndef PIN_UART0_RX
#define PIN_UART0_RX 255
#endif
#ifndef PIN_UART0_DE
#define PIN_UART0_DE 255
#endif
#ifndef PIN_UART0_RE
#define PIN_UART0_RE 255
#endif
/* UART1 */
#ifndef PIN_UART1_TX
#define PIN_UART1_TX 255
#endif
#ifndef PIN_UART1_RX
#define PIN_UART1_RX 255
#endif
/* UART4 */
#ifndef PIN_UART4_TX
#define PIN_UART4_TX 255
#endif
#ifndef PIN_UART4_RX
#define PIN_UART4_RX 255
#endif
#ifndef PIN_UART4_DE
#define PIN_UART4_DE 255
#endif
#ifndef PIN_UART4_RE
#define PIN_UART4_RE 255
#endif
/* UART5 */
#ifndef PIN_UART5_TX
#define PIN_UART5_TX 255
#endif
#ifndef PIN_UART5_RX
#define PIN_UART5_RX 255
#endif
#ifndef PIN_UART5_DE
#define PIN_UART5_DE 255
#endif
#ifndef PIN_UART5_RE
#define PIN_UART5_RE 255
#endif
/*---------------------------------------*/
/*----------IIC PIN DEFINITION-----------*/
/*---------------------------------------*/
/* IIC1 */
#ifndef PIN_IIC1_SCL
#define PIN_IIC1_SCL 255
#endif
#ifndef PIN_IIC1_SDA
#define PIN_IIC1_SDA 255
#endif
/* IIC2 */
#ifndef PIN_IIC2_SCL
#define PIN_IIC2_SCL 255
#endif
#ifndef PIN_IIC2_SDA
#define PIN_IIC2_SDA 255
#endif
/*---------------------------------------*/
/*----------IIS PIN DEFINITION-----------*/
/*---------------------------------------*/
/* IIS0 */
#ifndef PIN_IIS0_MCLK
#define PIN_IIS0_MCLK 255
#endif
#ifndef PIN_IIS0_BCLK
#define PIN_IIS0_BCLK 255
#endif
#ifndef PIN_IIS0_WCLK
#define PIN_IIS0_WCLK 255
#endif
#ifndef PIN_IIS0_DATA
#define PIN_IIS0_DATA 255
#endif
/* IIS1 */
#ifndef PIN_IIS1_MCLK
#define PIN_IIS1_MCLK 255
#endif
#ifndef PIN_IIS1_BCLK
#define PIN_IIS1_BCLK 255
#endif
#ifndef PIN_IIS1_WCLK
#define PIN_IIS1_WCLK 255
#endif
#ifndef PIN_IIS1_DATA
#define PIN_IIS1_DATA 255
#endif
/*---------------------------------------*/
/*----------PDM PIN DEFINITION-----------*/
/*---------------------------------------*/
/* PDM */
#ifndef PIN_PDM_MCLK
#define PIN_PDM_MCLK 255
#endif
#ifndef PIN_PDM_DATA
#define PIN_PDM_DATA 255
#endif
/*---------------------------------------*/
/*----------LED PIN DEFINITION-----------*/
/*---------------------------------------*/
/* LED */
#ifndef PIN_LED_SEG0
#define PIN_LED_SEG0 255
#endif
#ifndef PIN_LED_SEG1
#define PIN_LED_SEG1 255
#endif
#ifndef PIN_LED_SEG2
#define PIN_LED_SEG2 255
#endif
#ifndef PIN_LED_SEG3
#define PIN_LED_SEG3 255
#endif
#ifndef PIN_LED_SEG4
#define PIN_LED_SEG4 255
#endif
#ifndef PIN_LED_SEG5
#define PIN_LED_SEG5 255
#endif
#ifndef PIN_LED_SEG6
#define PIN_LED_SEG6 255
#endif
#ifndef PIN_LED_SEG7
#define PIN_LED_SEG7 255
#endif
#ifndef PIN_LED_SEG8
#define PIN_LED_SEG8 255
#endif
#ifndef PIN_LED_SEG9
#define PIN_LED_SEG9 255
#endif
#ifndef PIN_LED_SEG10
#define PIN_LED_SEG10 255
#endif
#ifndef PIN_LED_SEG11
#define PIN_LED_SEG11 255
#endif
#ifndef PIN_LED_COM0
#define PIN_LED_COM0 255
#endif
#ifndef PIN_LED_COM1
#define PIN_LED_COM1 255
#endif
#ifndef PIN_LED_COM2
#define PIN_LED_COM2 255
#endif
#ifndef PIN_LED_COM3
#define PIN_LED_COM3 255
#endif
#ifndef PIN_LED_COM4
#define PIN_LED_COM4 255
#endif
#ifndef PIN_LED_COM5
#define PIN_LED_COM5 255
#endif
#ifndef PIN_LED_COM6
#define PIN_LED_COM6 255
#endif
#ifndef PIN_LED_COM7
#define PIN_LED_COM7 255
#endif
/*---------------------------------------*/
/*---------GMAC PIN DEFINITION-----------*/
/*---------------------------------------*/
/* GMAC */
#ifndef PIN_GMAC_RMII_REF_CLKIN
#define PIN_GMAC_RMII_REF_CLKIN PB_14
#endif
#ifndef PIN_GMAC_RMII_RXD0
#define PIN_GMAC_RMII_RXD0 PB_12
#endif
#ifndef PIN_GMAC_RMII_RXD1
#define PIN_GMAC_RMII_RXD1 PB_13
#endif
#ifndef PIN_GMAC_RMII_TXD0
#define PIN_GMAC_RMII_TXD0 PB_15
#endif
#ifndef PIN_GMAC_RMII_TXD1
#define PIN_GMAC_RMII_TXD1 PC_0
#endif
#ifndef PIN_GMAC_RMII_CRS_DV
#define PIN_GMAC_RMII_CRS_DV PC_2
#endif
#ifndef PIN_GMAC_RMII_TX_EN
#define PIN_GMAC_RMII_TX_EN PC_1
#endif
#ifndef PIN_GMAC_RMII_MDIO
#define PIN_GMAC_RMII_MDIO PC_4
#endif
#ifndef PIN_GMAC_RMII_MDC
#define PIN_GMAC_RMII_MDC PC_5
#endif
/*---------------------------------------*/
/*---------SDIO PIN DEFINITION-----------*/
/*---------------------------------------*/
/* SDIO */
#ifndef PIN_SDCLK
#define PIN_SDCLK 255
#endif
#ifndef PIN_SDCMD
#define PIN_SDCMD 255
#endif
#ifndef PIN_SDDAT0
#define PIN_SDDAT0 255
#endif
#ifndef PIN_SDDAT1
#define PIN_SDDAT1 255
#endif
#ifndef PIN_SDDAT2
#define PIN_SDDAT2 255
#endif
#ifndef PIN_SDDAT3
#define PIN_SDDAT3 255
#endif
/*---------------------------------------*/
/*---------QSPI PIN DEFINITION-----------*/
/*---------------------------------------*/
/* QSPI */
#ifndef PIN_QSPI_CS
#define PIN_QSPI_CS PB_4
#endif
#ifndef PIN_QSPI_CLK
#define PIN_QSPI_CLK PB_1
#endif
#ifndef PIN_QSPI_IO0
#define PIN_QSPI_IO0 PB_0
#endif
#ifndef PIN_QSPI_IO1
#define PIN_QSPI_IO1 PB_5
#endif
#ifndef PIN_QSPI_IO2
#define PIN_QSPI_IO2 PB_3
#endif
#ifndef PIN_QSPI_IO3
#define PIN_QSPI_IO3 PB_2
#endif
#ifndef PIN_QSPI_CS1
#define PIN_QSPI_CS1 PB_6
#endif
/*---------------------------------------*/
/*---------SPI PIN DEFINITION------------*/
/*---------------------------------------*/
/* SPI0 */
#ifndef PIN_SPI0_CS
#define PIN_SPI0_CS 255
#endif
#ifndef PIN_SPI0_CLK
#define PIN_SPI0_CLK 255
#endif
#ifndef PIN_SPI0_IO0
#define PIN_SPI0_IO0 255
#endif
#ifndef PIN_SPI0_IO1
#define PIN_SPI0_IO1 255
#endif
#ifndef PIN_SPI0_IO2
#define PIN_SPI0_IO2 255
#endif
#ifndef PIN_SPI0_IO3
#define PIN_SPI0_IO3 255
#endif
/* SPI1 */
#ifndef PIN_SPI1_CS
#define PIN_SPI1_CS 255
#endif
#ifndef PIN_SPI1_CLK
#define PIN_SPI1_CLK 255
#endif
#ifndef PIN_SPI1_IO0
#define PIN_SPI1_IO0 255
#endif
#ifndef PIN_SPI1_IO1
#define PIN_SPI1_IO1 255
#endif
#ifndef PIN_SPI1_IO2
#define PIN_SPI1_IO2 255
#endif
#ifndef PIN_SPI1_IO3
#define PIN_SPI1_IO3 255
#endif
/* SPI5 */
#ifndef PIN_SPI5_CLK
#define PIN_SPI5_CLK 255
#endif
#ifndef PIN_SPI5_IO0
#define PIN_SPI5_IO0 255
#endif
#ifndef PIN_SPI5_IO1
#define PIN_SPI5_IO1 255
#endif
/* SPI6 */
#ifndef PIN_SPI6_CLK
#define PIN_SPI6_CLK 255
#endif
#ifndef PIN_SPI6_IO0
#define PIN_SPI6_IO0 255
#endif
#ifndef PIN_SPI6_IO1
#define PIN_SPI6_IO1 255
#endif
/*---------------------------------------*/
/*---------ADC PIN DEFINITION------------*/
/*---------------------------------------*/
/* ADC */
#ifndef PIN_ADC
#define PIN_ADC 255
#endif
/*---------------------------------------*/
/*---------DVP PIN DEFINITION------------*/
/*---------------------------------------*/
/* DVP */
#ifndef PIN_DVP_HSYNC
#define PIN_DVP_HSYNC PB_7
#endif
#ifndef PIN_DVP_VSYNC
#define PIN_DVP_VSYNC PB_6
#endif
#ifndef PIN_DVP_PCLK
#define PIN_DVP_PCLK PB_12
#endif
#ifndef PIN_DVP_MCLK
#define PIN_DVP_MCLK PB_9
#endif
#ifndef PIN_DVP_DATA0
#define PIN_DVP_DATA0 PB_14
#endif
#ifndef PIN_DVP_DATA1
#define PIN_DVP_DATA1 PC_0
#endif
#ifndef PIN_DVP_DATA2
#define PIN_DVP_DATA2 PC_1
#endif
#ifndef PIN_DVP_DATA3
#define PIN_DVP_DATA3 PB_15
#endif
#ifndef PIN_DVP_DATA4
#define PIN_DVP_DATA4 PB_13
#endif
#ifndef PIN_DVP_DATA5
#define PIN_DVP_DATA5 PB_11
#endif
#ifndef PIN_DVP_DATA6
#define PIN_DVP_DATA6 PB_10
#endif
#ifndef PIN_DVP_DATA7
#define PIN_DVP_DATA7 PB_8
#endif
#ifndef PIN_DVP_RESET
#define PIN_DVP_RESET 255
#endif
#ifndef PIN_DVP_PDN
#define PIN_DVP_PDN 255
#endif
/*---------------------------------------*/
/*---------SDH PIN DEFINITION------------*/
/*---------------------------------------*/
/* SDH */
#ifndef PIN_SDH_CLK
#define PIN_SDH_CLK 255
#endif
#ifndef PIN_SDH_CMD
#define PIN_SDH_CMD 255
#endif
#ifndef PIN_SDH_DAT0
#define PIN_SDH_DAT0 255
#endif
#ifndef PIN_SDH_DAT1
#define PIN_SDH_DAT1 255
#endif
#ifndef PIN_SDH_DAT2
#define PIN_SDH_DAT2 255
#endif
#ifndef PIN_SDH_DAT3
#define PIN_SDH_DAT3 255
#endif
/*---------------------------------------*/
/*---------TIMER PIN DEFINITION----------*/
/*---------------------------------------*/
/* NORMAL TIMER0 */
#ifndef PIN_PWM_CHANNEL_0
#define PIN_PWM_CHANNEL_0 255
#endif
#ifndef PIN_CAPTURE_CHANNEL_0
#define PIN_CAPTURE_CHANNEL_0 255
#endif
/* NORMAL TIMER1 */
#ifndef PIN_PWM_CHANNEL_1
#define PIN_PWM_CHANNEL_1 255
#endif
#ifndef PIN_CAPTURE_CHANNEL_1
#define PIN_CAPTURE_CHANNEL_1 255
#endif
/* LED_TIMER0 */
#ifndef PIN_PWM_CHANNEL_2
#define PIN_PWM_CHANNEL_2 255
#endif
/* SUPTMR0 */
#ifndef PIN_PWM_CHANNEL_3
#define PIN_PWM_CHANNEL_3 255
#endif
#ifndef PIN_PWM_CHANNEL_4
#define PIN_PWM_CHANNEL_4 255
#endif
#ifndef LCD_TE
#define LCD_TE 255
#endif
enum pin_name {
PA_0 = 0,
PA_1,
PA_2,
PA_3,
PA_4,
PA_5,
PA_6,
PA_7,
PA_8,
PA_9,
PA_10,
PA_11,
PA_12,
PA_13,
PA_14,
PA_15,
PB_0,
PB_1,
PB_2,
PB_3,
PB_4,
PB_5,
PB_6,
PB_7,
PB_8,
PB_9,
PB_10,
PB_11,
PB_12,
PB_13,
PB_14,
PB_15,
PC_0,
PC_1,
PC_2,
PC_3,
PC_4,
PC_5,
PC_6,
PC_7,
PC_8,
PC_9,
PC_10,
PC_11,
PC_12,
PC_13,
PC_14,
PC_15,
PE_0,
PE_1,
PE_2,
PE_3,
PE_4,
PE_5,
PE_6,
PE_7,
PE_8,
PE_9,
PE_10,
PE_11,
PE_12,
PE_13,
PE_14,
PE_15,
};
#ifdef __cplusplus
}
#endif
#endif
sdk/include/chip/txw81x/pmu.h
+553
View File
@@ -0,0 +1,553 @@
/**
******************************************************************************
* @file pmu.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2021.01.14
* @brief This file contains all the PowerDomain firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
*
*
* Revision History
* V1.0.0 2021.01.14 First Release, move from sysctrl
*
******************************************************************************
*/
#ifndef __PMU_H__
#define __PMU_H__
#include "typesdef.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CORE_LVD_CON (0x00>>0)
#define CORE_LVD_CON1 (0x04>>0)
#define CORE_LVD_CON2 (0x08>>0)
#define CORE_PMUCON0 (0x10>>0)
#define CORE_PMUCON1 (0x14>>0)
#define CORE_PMUCON2 (0x18>>0)
#define CORE_PMUCON3 (0x1c>>0)
#define CORE_PMUCON4 (0x20>>0)
#define CORE_PMUCON5 (0x24>>0)
#define CORE_RFCON0 (0x28>>0)
#define CORE_RFCON1 (0x2c>>0)
#define CORE_PMUCON6 (0x30>>0)
#define CORE_PMUCON7 (0x34>>0)
#define CORE_PMUCON8 (0x38>>0)
#define CORE_PMUCON9 (0x3c>>0)
#define CORE_PMUCON10 (0x40>>0)
#define CORE_PMUCON11 (0x44>>0)
#define CORE_PMUCON12 (0x48>>0)
#define CORE_PMUCON13 (0x4c>>0)
#define CORE_PNDCLR (0x50>>0)
//-------------RTC part1 start---------------
#define CORE_RTCWPR (0x54>>0) //54
#define CORE_RTCCTR (0x58>>0) //58
#define CORE_RTCPDR (0x5c>>0) //5c
#define CORE_RTCISR (0x60>>0) //60
#define CORE_RTCSSR (0x64>>0) //64
#define CORE_RTCTMR (0x68>>0) //68
#define CORE_RTCDAR (0x6c>>0) //6c
#define CORE_RTCALR0R (0x70>>0) //70
#define CORE_RTCWUTR (0x74>>0) //74
#define CORE_RTCTSSSR (0x78>>0) //78
#define CORE_RTCTSTMR (0x7c>>0) //7c
//-------------RTC part1 end---------------
#define CORE_TMRCON (0x80>>0)
#define CORE_TMRPR (0x84>>0)
#define CORE_TMRRPT (0x88>>0)
#define CORE_TMRTRIM (0x8c>>0)
#define CORE_TMRPR2 (0x90>>0)
//-------------RTC part2 start---------------
//#define CORE_TMRRTCC (0x94>>0)
#define CORE_RTCTSDAR (0x94>>0) //94
#define CORE_RTCCALR (0x98>>0) //98
#define CORE_RTCSSSR (0x9c>>0) //9c
//-------------RTC part2 start---------------
#define CORE_WKCON (0xa0>>0)
#define CORE_WKCON1 (0xa4>>0)
#define CORE_WKCON2 (0xa8>>0)
#define CORE_SECCON (0xb0>>0)
#define CORE_SECDAT (0xb4>>0)
#define CORE_SECADR (0xb8>>0)
#define CORE_SECKEY (0xbc>>0)
#define CORE_CMPCON (0xc0>>0)
#define CORE_CMPCON1 (0xc4>>0)
#if 0 //vernus
#define CORE_TMR0CON (0xd0>>0)
#define CORE_TMR1CON (0xd4>>0)
#define CORE_TMR2CON (0xd8>>0)
#define CORE_TMR3CON (0xdc>>0)
#else //vernus200
#define CORE_PMUCON14 (0xc8>>0)
#define CORE_PMUCON15 (0xcc>>0)
#define CORE_TMR_CON (0xd0>>0)
#define CORE_TMR0CON (0xd4>>0)
#define CORE_TMR1CON (0xd8>>0)
#define CORE_TMR2CON (0xdc>>0)
#define CORE_TMR3CON (0xe0>>0)
#define CORE_WDTCON (0xe4>>0)
#define CORE_WDTKEY (0xe8>>0)
#endif
typedef struct
{
__IO uint32 LVD_CON;
__IO uint32 LVD_CON1;
__IO uint32 LVD_CON2;
uint32 RESERVED0;
__IO uint32 PMUCON0;
__IO uint32 PMUCON1;
__IO uint32 PMUCON2;
__IO uint32 PMUCON3;
__IO uint32 PMUCON4;
__IO uint32 PMUCON5;
__IO uint32 RFCON0;
__IO uint32 RFCON1;
__IO uint32 PMUCON6;
__IO uint32 PMUCON7;
__IO uint32 PMUCON8;
__IO uint32 PMUCON9;
__IO uint32 PMUCON10; //40
__IO uint32 PMUCON11;
__IO uint32 PMUCON12;
__IO uint32 PMUCON13;
__IO uint32 PNDCLR; //50
//-------------RTC part1 start---------------
__IO uint32 RTCWPR; //54
__IO uint32 RTCCTR; //58
__IO uint32 RTCPDR; //5c
__IO uint32 RTCISR; //60
__IO uint32 RTCSSR; //64
__IO uint32 RTCTMR; //68
__IO uint32 RTCDAR; //6c
__IO uint32 RTCALR0R; //70
__IO uint32 RTCWUTR; //74
__IO uint32 RTCTSSSR; //78
__IO uint32 RTCTSTMR; //7c
//uint32 RESERVED1[((0x80 - 0x50) / 4) - 1];
//-------------RTC part1 end---------------
__IO uint32 TMRCON; //80
__IO uint32 TMRPR;
__IO uint32 TMRRPT;
__IO uint32 TMRTRIM;
__IO uint32 TMRPR2; //90
//-------------RTC part2 start---------------
//__IO uint32 TMRRTCC; //remove
__IO uint32 RTCTSDAR; //94
__IO uint32 RTCCALR; //98
__IO uint32 RTCSSSR; //9c
//uint32 RESERVED2[((0xa0 - 0x94) / 4) - 1];
//-------------RTC part2 end---------------
__IO uint32 WKCON; //a0
__IO uint32 WKCON1;
__IO uint32 WKCON2;
uint32 RESERVED3[((0xb0 - 0xa8) / 4) - 1];
__IO uint32 SECCON; //b0
__IO uint32 SECDAT;
__IO uint32 SECADDR;
__IO uint32 SECKEY;
__IO uint32 CMPCON; //c0
__IO uint32 CMPCON1; //c4
__IO uint32 PMUCON14; //c8
__IO uint32 PMUCON15; //cc
__IO uint32 TMR_CON; //d0
__IO uint32 TMR0CON0; //d4
__IO uint32 TMR1CON0; //d8
__IO uint32 TMR2CON0; //dc
__IO uint32 TMR3CON0; //e0
__IO uint32 WDTCON; //e0
__IO uint32 WDTKEY; //e0
} PMU_TypeDef;
#define PMU ((PMU_TypeDef *) PMU_BASE)
#define PMU_REG_SET_BITS(reg, bits) do { pmu_reg_write((uint32)&reg, (reg)|(bits)); } while(0)
#define PMU_REG_CLR_BITS(reg, bits) do { pmu_reg_write((uint32)&reg, (reg) & ~(bits)); } while(0)
#define PMU_REG_SET_VALUE(reg, bit_mask, val, bit_pos) do { pmu_reg_write((uint32)&reg, ((reg) & ~(bit_mask)) | (((val) << (bit_pos)) & (bit_mask)) ); } while(0)
#define PMU_REG_BIT_FUN(fun_name, reg, bits)\
__STATIC_INLINE void fun_name##_en(void) { PMU_REG_SET_BITS(reg, bits); }\
__STATIC_INLINE void fun_name##_dis(void) { PMU_REG_CLR_BITS(reg, bits); }
/* lvdcon */
#define pmu_vcam_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(31))
#define pmu_vcam_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(31))
#define PMU_VCAM_OC_PENDING (PMU->LVD_CON & BIT(30))
#define PMU_V15_OC_PENDING (PMU->LVD_CON & BIT(29))
#define PMU_VDD_OC_PENDING (PMU->LVD_CON & BIT(28))
#define PMU_VDD_LV_PENDING (PMU->LVD_CON & BIT(27))
#define PMU_VCC_LV_PENDING (PMU->LVD_CON & BIT(26))
#define PMU_VCC1_LV_PENDING (PMU->LVD_CON & BIT(25))
#define PMU_VCC15_LV_PENDING (PMU->LVD_CON & BIT(24))
#define pmu_vcc1_lv_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(23))
#define pmu_vcc1_lv_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(23))
#define pmu_vcc15_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(22))
#define pmu_vcc15_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(22))
#define pmu_lvd_oe_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(21))
#define pmu_lvd_oe_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(21))
#define pmu_vdd_oc_int_en() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(20))
#define pmu_vdd_oc_int_dis() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(20))
#define pmu_vdd_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(19))
#define pmu_vdd_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(19))
#define pmu_vcc_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(18))
#define pmu_vcc_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(18))
#define pmu_vcc15_lv_reset_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(17))
#define pmu_vcc15_lv_reset_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(17))
#define PMU_VDD18_OC_PENDING (PMU->LVD_CON1 & BIT(31))
#define PMU_VDD12_OC_PENDING (PMU->LVD_CON1 & BIT(30))
enum vcc15_oc_level {
VCC15_OC_200MA = 0,
VCC15_OC_90MA = 0x3,
VCC15_OC_70MA,
VCC15_OC_60MA,
VCC15_OC_50MA,
};
#define pmu_vcc15_oc_level_set(vcc15_oc_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x0001c000, vcc15_oc_level, 14)
enum vdd_oc_level {
VDD_OC_50MA,
VDD_OC_100MA,
VDD_OC_150MA,
VDD_OC_200MA,
};
#define pmu_vdd_oc_level_set(vdd_oc_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00003000, vdd_oc_level, 12)
enum vcc15_lv_level {
VCC15_LV_0V86_T_0V90,
VCC15_LV_1V00_T_1V05,
VCC15_LV_1V14_T_1V19,
VCC15_LV_1V29_T_1V35,
};
#define pmu_vcc15_lv_level_set(vcc15_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000c00, vcc15_lv_level, 10)
enum vdd_lv_level {
VDD_LV_0V64_T_0V68,
VDD_LV_0V74_T_0V78,
VDD_LV_0V84_T_0V88,
VDD_LV_0V84_T_0V98,
};
#define pmu_vdd_lv_level_set(vdd_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000300, vdd_lv_level, 8)
enum avcc_lv_level {
AVCC_LV_1V90_T_1V99,
AVCC_LV_2V06_T_2V16,
AVCC_LV_2V21_T_2V31,
AVCC_LV_2V33_T_2V44,
AVCC_LV_2V46_T_2V58,
AVCC_LV_2V62_T_2V74,
AVCC_LV_2V75_T_2V87,
AVCC_LV_2V90_T_3V04,
};
#define pmu_avcc_lv_level_set(avcc_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x000000e0, avcc_lv_level, 5)
enum vcc1_lv_level {
VCC1_LV_2V54_T_2V66,
VCC1_LV_1V46_T_1V53,
};
#define pmu_vcc1_lv_level_set(vcc1_lv_level) PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000010, vcc1_lv_level, 4)
#define pmu_vdd_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(3))
#define pmu_vdd_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(3))
#define pmu_avcc_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(2))
#define pmu_avcc_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(2))
#define pmu_vcc1_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(1))
#define pmu_vcc1_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(1))
#define pmu_vcc15_lv_detect_en() PMU_REG_SET_BITS(PMU->LVD_CON, BIT(0))
#define pmu_vcc15_lv_detect_dis() PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(0))
/* lvdcon1 */
#define pmu_vcc_lv_detect_sync_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(30))
#define pmu_vcc_lv_detect_sync_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(30))
#define pmu_vdd_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(29))
#define pmu_vdd_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(29))
#define pmu_vcc_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(28))
#define pmu_vcc_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(28))
#define pmu_vdd_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
#define pmu_vdd_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
#define pmu_vdd_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
#define pmu_vdd_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
#define pmu_vcc_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
#define pmu_vcc_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
#define pmu_vcc_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
#define pmu_vcc_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
/* lvdcon2 */
#define pmu_vcc1_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(29))
#define pmu_vcc1_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(29))
#define pmu_vcc15_lv_detect_filter_en() PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(28))
#define pmu_vcc15_lv_detect_filter_dis() PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(28))
#define pmu_vcc1_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
#define pmu_vcc1_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
#define pmu_vcc1_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
#define pmu_vcc1_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
#define pmu_vcc15_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
#define pmu_vcc15_oc_lv_ldetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
#define pmu_vcc15_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
#define pmu_vcc15_oc_lv_hdetect_filter_set(level) PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
/* CORE_PMUCON0 */
#define pmu_port_wk_auto_dis_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(29))
#define pmu_port_wk_auto_dis_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(29))
#define pmu_mclr_soft_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(28))
#define pmu_mclr_soft_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(28))
#define pmu_led_io_mux_en() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(27))
#define pmu_led_io_mux_dis() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(27))
enum pd_tmr1_clk_sel {
PD_TMR1_CLK_RC128K,
PD_TMR1_CLK_XOSC,
PD_TMR1_CLK_RC10M,
PD_TMR1_CLK_LX32K,
};
#define pmu_pd_tmr1_clk_sel(pd_tmr1_clk_sel) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x06000000, pd_tmr1_clk_sel, 25)
#define pmu_pd_mem2_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(24))
#define pmu_pd_mem2_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(24))
#define pmu_fls_pg_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(23))
#define pmu_fls_pg_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(23))
#define pmu_pd_mem32k_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(22))
#define pmu_pd_mem32k_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(22))
#define pmu_pd_ulp_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(21))
#define pmu_pd_ulp_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(21))
#define pmu_pd_rf_latch_en() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(19))
#define pmu_pd_rf_latch_dis() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(19))
#define pmu_pd_osc_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(18))
#define pmu_pd_osc_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(18))
#define pmu_pd_osc_hw_trim_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(17))
#define pmu_pd_osc_hw_trim_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(17))
enum pd_tmr_clk_sel {
PD_TMR_CLK_RC128K,
PD_TMR_CLK_XOSC,
PD_TMR_CLK_RC10M,
PD_TMR_CLK_LX32K,
};
#define pmu_pd_tmr_clk_sel(pd_tmr_clk_sel) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00018000, pd_tmr_clk_sel, 15)
#define pmu_io_clk_en() PMU_REG_SET_BITS(PMU->PMUCON0, BIT(14))
#define pmu_io_clk_dis() PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(14))
enum lpvdd_vol_level {
LPVDD_VOL_0V74,
LPVDD_VOL_0V81,
LPVDD_VOL_0V88,
LPVDD_VOL_0V95,
LPVDD_VOL_1V02,
LPVDD_VOL_1V09,
LPVDD_VOL_1V16,
LPVDD_VOL_1V23,
};
#define pmu_lpvdd_vol_set(lpvdd_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00000700, lpvdd_vol_level, 8)
/* CORE_PMUCON1 */
/* CORE_PMUCON2 */
/* CORE_PMUCON3 */
/* CORE_PMUCON4 */
/* CORE_PMUCON5 */
enum vdd15_vol_level {
VDD15_VOL_1V2,
VDD15_VOL_1V3,
VDD15_VOL_1V4,
VDD15_VOL_1V5,
VDD15_VOL_1V6,
VDD15_VOL_1V7,
VDD15_VOL_1V8,
VDD15_VOL_1V9,
VDD15_VOL_2V0,
VDD15_VOL_2V1,
VDD15_VOL_2V2,
VDD15_VOL_2V3,
VDD15_VOL_2V4,
VDD15_VOL_2V5,
};
#define pmu_vdd15_vol_set(vdd15_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON5, 0xF, vdd15_vol_level, 0)
#define pmu_hirc_10mhz_en() PMU_REG_SET_BITS(PMU->PMUCON5, BIT(24))
#define pmu_hirc_10mhz_dis() PMU_REG_CLR_BITS(PMU->PMUCON5, BIT(24))
/* CORE_PMUCON7 */
#define pmu_boot_direct_run_en() PMU_REG_SET_BITS(PMU->PMUCON7, BIT(0))
#define pmu_boot_direct_run_dis() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(0))
#define pmu_get_boot_direct_run_pending() ((PMU->PMUCON7 & BIT(0)))
#define pmu_get_boot_direct_run_pending2() ((PMU->PMUCON7 & BIT(23)))
#define pmu_set_direct_run_pengding2() PMU_REG_SET_BITS(PMU->PMUCON7, BIT(23))
#define pmu_clr_direct_run_pengding2() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(23))
#define pmu_set_direct_run_addr(addr) PMU_REG_SET_VALUE(PMU->PMUCON7, 0xFF000000, ((addr >> 12) & 0xFF), 24)
#define pmu_get_boot_code_pos() ((PMU->PMUCON7 & BIT(3)) ? 1 : 0)
#define pmu_get_cp_fail_pending() ((PMU->PMUCON7 & BIT(2)) ? 1 : 0)
#define pmu_clr_cp_fail_pending() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(2))
#define pmu_get_deadcode_pending() ((PMU->PMUCON7 & BIT(1)) ? 1 : 0)
#define pmu_clr_deadcode_pending() PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(1))
#define pmu_set_deadcode_pending() PMU_REG_SET_BITS(PMU->PMUCON7, BIT(1))
#define GET_DIRECT_RUN_DISABLE_SIGN() ((PMU->PMUCON7 & BIT(4)) ? 1 : 0)
#define SET_DIRECT_RUN_DISABLE_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(4));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(4));\
} while(0)
#define GET_SKIP_MASTER_BOOT_SIGN() ((PMU->PMUCON7 & BIT(5)) ? 1 : 0)
#define SET_SKIP_MASTER_BOOT_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(5));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(5));\
} while(0)
#define GET_SKIP_TEST_MODE_SIGN() ((PMU->PMUCON7 & BIT(6)))
#define SET_SKIP_TEST_MODE_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(6));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(6));\
} while(0)
#define GET_SKIP_PSRAM_SIGN() ((PMU->PMUCON7 & BIT(7)))
#define SET_SKIP_PSRAM_SIGN(n)\
do {\
if (n) PMU_REG_SET_BITS(PMU->PMUCON7, BIT(7));\
else PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(7));\
} while(0)
/* CORE_PMUCON8 */
#define pmu_jtag_io_en() PMU_REG_SET_BITS(PMU->PMUCON8, BIT(0))
#define pmu_jtag_io_dis() PMU_REG_CLR_BITS(PMU->PMUCON8, BIT(0))
/* CORE_PMUCON11 */
#define VCCFLS_PG_DISABLE()\
do {\
pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 & (~ BIT(23))); \
pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 | (BIT(17))); \
} while(0)
#define VCCFLS_PG_ENABLE()\
do {\
pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 & (~ BIT(17)));\
pmu_reg_write((uint32)&PMU->PMUCON0, PMU->PMUCON0 | BIT(23)); \
} while(0)
#define pmu_vcam_lc_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(29))
#define pmu_vcam_lc_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(29))
#define pmu_vcam_pg_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(16))
#define pmu_vcam_pg_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(16))
#define pmu_vcam_oc_detect_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(15))
#define pmu_vcam_oc_detect_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(15))
#define pmu_vcam_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(14))
#define pmu_vcam_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(14))
#define pmu_vcam_discharge_en() PMU_REG_SET_BITS(PMU->PMUCON11, BIT(13))
#define pmu_vcam_discharge_dis() PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(13))
enum vcam_vol_level {
VCAM_VOL_2V50,
VCAM_VOL_2V55,
VCAM_VOL_2V60,
VCAM_VOL_2V65,
VCAM_VOL_2V70,
VCAM_VOL_2V75,
VCAM_VOL_2V80,
VCAM_VOL_2V85,
VCAM_VOL_2V90,
VCAM_VOL_2V95,
VCAM_VOL_3V00,
VCAM_VOL_3V05,
VCAM_VOL_3V10,
VCAM_VOL_3V15,
VCAM_VOL_3V20,
VCAM_VOL_3V25,
};
#define pmu_set_vcam_vol(vcam_vol_level) PMU_REG_SET_VALUE(PMU->PMUCON11, 0x01e00000, vcam_vol_level, 21)
/* CORE_RFCON0 */
#define pmu_xo_cs_set(xo_cs_vdd) PMU_REG_SET_VALUE(PMU->RFCON0, 0x03f80000, xo_cs_vdd, 19)
#define xo_set_cs_sec(xo_cs_vdd) pmu_xo_cs_set(xo_cs_vdd)
#define pmu_xosc_en() PMU_REG_SET_BITS(PMU->RFCON0, BIT(0))
#define pmu_xosc_dis() PMU_REG_CLR_BITS(PMU->RFCON0, BIT(0))
struct system_reset_info {
union {
uint32 system_reset_pending;
struct system_reset_pending_bits {
uint32 srp_mclr : 1,
srp_soft : 1,
srp_wdt : 1,
srp_lvd : 1,
srp_lvd_vcam_cur_ov : 1,
srp_lvd_vcc15_cur_ov : 1,
srp_lvd_vdd_cur_ov : 1,
srp_lvd_vdd_vol_low : 1,
srp_lvd_vcc_vol_low : 1,
srp_lvd_vcc1_vol_low : 1,
srp_lvd_vcc15_vol_low : 1,
srp_deep_sleep : 1,
srp_lvd_vdd18_cur_ov : 1,
srp_lvd_vdd12_cur_ov : 1,
srp_lp_wdt : 1,
Reserved : 16,
srp_detected : 1;
} system_reset_pending_bits_s;
};
} __attribute__((packed));
extern struct system_reset_info sri;
void pmu_reg_write(uint32 reg_addr, uint32 data) ;
void pmu_dcdc_open(void);
void pmu_tsensor_chan_sel_sec(uint8 chan_idx);
void pmu_pd_set_anatop_en_sec(void);
int jtag_map_set(uint8 val);
void tsensor_open(void);
void tsensor_close(void);
void lvd_irq_handler(void *data);
void sys_reset_detect(void);
void sys_reset_pending_clr(void);
void sys_reset_show(void);
void pmu_vdd_core_set(uint32 vddcore);
#ifdef __cplusplus
}
#endif
#endif //__PMU_H__
/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/
sdk/include/chip/txw81x/sysctrl.h
+860
View File
@@ -0,0 +1,860 @@
/**
******************************************************************************
* @file sysctrl.h
* @author HUGE-IC Application Team
* @version V1.0.0
* @date 2021.01.14
* @brief This file contains all the PowerDomain firmware functions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
*
*
* Revision History
* V1.0.0 2021.01.14 First Release
*
******************************************************************************
*/
// Define to prevent recursive inclusion //////////////////////////////
#ifndef __SYSCTRL_H__
#define __SYSCTRL_H__
#include "typesdef.h"
#include "pmu.h"
#include "misc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @defgroup SYSCTRL_Exported_Constants
* @{
*/
#define CLK_RC128K 128000
#define CLK_HXOSC 40000000
#define CLK_SYSPLL 360000000
#define CLK_USBPLL 480000000
#define CLK_RC10M 10000000
#define CLK_LXOSC32K 32000
#define EFUSE_PACK_OFFSET 119
#define EFUSE_BIOS_ID 113
#define EFUSE_5_10M_DIS_OFFSET 118
#define EFUSE_5_10M_DIS_SIZE 1 //bit 2
//芯片封装定义
#define PACK_811_100 0x01
#define PACK_812_310 0x02
#define PACK_813_320 0x03
#define PACK_816_G00 0x06 //QFN48
#define PACK_816_G00_FIX 0xF6 //QFN48 ， 改启动模式补救PCBA
#define PACK_KL908 0x07 //QFN48 PACK_816_G00 基础上增加VCC18 LDO封装
#define PACK_KL908F 0x16 //QFN48
#define PACK_816_810 0x08 //QFN48
#define PACK_817_810 0x0A
#define PACK_817_H24 0x0B
#define PACK_817_824 0x0C
#define PACK_817_812 0x0D
#define PACK_817_824F 0x0F
#define PACK_818_C04L 0x10
#define PACK_818_C08L 0x11
#define PACK_818_C016L 0x12
#define PACK_818_C04F 0x13
#define PACK_818_C04LB 0x14
#define PACK_818_C08LP 0x15
#define PACK_817_824_GD 0x1C
struct __clock_cfg {
uint8 clk_source_sel;
uint8 clk_valid;
uint16 reserved;
uint32 exosc_clk_hz; /* read from efuse */
uint32 hirc_clk_hz; /* read from efuse */
uint32 sys_clk;
uint32 syspll_clk;
uint32 max_flash_clk;
uint32 flash_clk_mod;
uint32 max_psram_clk;
};
typedef struct
{
__IO uint32 SYS_KEY;
__IO uint32 SYS_CON0;
__IO uint32 SYS_CON1;
__IO uint32 SYS_CON2;
__IO uint32 SYS_CON3;
__IO uint32 SYS_CON4;
__IO uint32 SYS_CON5;
__IO uint32 SYS_CON6;
__IO uint32 SYS_CON7;
__IO uint32 SYS_CON8;
__IO uint32 SYS_CON9;
__IO uint32 SYS_CON10;
__IO uint32 SYS_CON11;
__IO uint32 SYS_CON12;
__IO uint32 SYS_CON13;
__IO uint32 SYS_CON14;
__IO uint32 SYS_CON15;
__IO uint32 CLK_CON0;
__IO uint32 CLK_CON1;
__IO uint32 CLK_CON2;
__IO uint32 CLK_CON3;
__IO uint32 CLK_CON4;
__IO uint32 CLK_CON5;
__IO uint32 CHIP_ID;
__IO uint32 CLK_CON6;
__IO uint32 CLK_CON7;
__IO uint32 SRAM0_PD_CON;
__IO uint32 AIP_CON0;
__IO uint32 AIP_CON1;
__IO uint32 IO_MAP;
__IO uint32 EFUSE_CON;
__IO uint32 SYS_ERR0;
__IO uint32 SYS_ERR1;
__IO uint32 HOSC_MNT;
__IO uint32 WK_CTRL;
__IO uint32 LP_CTRL;
__IO uint32 MBIST_CTRL;
__IO uint32 MPE[6];
__IO uint32 MPE_PND[6];
__IO uint32 MODE_REG;
__IO uint32 MBIST_MISR;
__IO uint32 MBIST_MISR1;
__IO uint32 MBIST_MISR2;
__IO uint32 MBIST_MISR3;
__IO uint32 MBIST_MISR4;
__IO uint32 MBIST_MISR5;
__IO uint32 MBIST_MISR6;
__IO uint32 MBIST_MISR7;
__IO uint32 USB20_PHY_CFG0;
__IO uint32 USB20_PHY_CFG1;
__IO uint32 USB20_PHY_CFG2;
__IO uint32 USB20_PHY_CFG3;
__IO uint32 USB20_PHY_DBG0;
__IO uint32 USB20_PHY_DBG1;
uint32 RESERVED0[16];
__IO uint32 IOFUNCINCON0;
__IO uint32 IOFUNCINCON1;
__IO uint32 IOFUNCINCON2;
__IO uint32 IOFUNCINCON3;
__IO uint32 IOFUNCINCON4;
__IO uint32 IOFUNCINCON5;
__IO uint32 IOFUNCINCON6;
__IO uint32 IOFUNCINCON7;
__IO uint32 IOFUNCINCON8;
__IO uint32 IOFUNCINCON9;
__IO uint32 IOFUNCINCON10;
__IO uint32 IOFUNCINCON11;
__IO uint32 IOFUNCINCON12;
__IO uint32 IOFUNCINCON13;
__IO uint32 IOFUNCINCON14;
__IO uint32 IOFUNCINCON15;
__IO uint32 IOFUNCMASK0;
__IO uint32 QSPI_MAP_CTL;
__IO uint32 QSPI_ENCDEC_CON0;
__IO uint32 QSPI_ENCDEC_CON1;
__IO uint32 TRNG;
__IO uint32 DCRC_TRIM;
__IO uint32 CPU1_CON0;
__IO uint32 CPU1_CON1;
__IO uint32 IOFUNCMASK1;
__IO uint32 PE16CON;
__IO uint32 OSPI_MAP_CTL0;
__IO uint32 OSPI_MAP_CTL1;
__IO uint32 IOFUNCMASK2;
} SYSCTRL_TypeDef;
#define SYSCTRL ((SYSCTRL_TypeDef *) HG_SYSCTRL_BASE)
#if SYS_KEY_OPT_EN
#define sysctrl_unlock() do { SYSCTRL->SYS_KEY = 0x3fac87e4; } while(0)
#define sysctrl_lock() do { SYSCTRL->SYS_KEY = ~ 0x3fac87e4; } while(0)
#define SYSCTRL_REG_OPT_INIT() do { sysctrl_lock(); SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; } while(0)
#define SYSCTRL_REG_OPT(expr) do { uint32 flag=disable_irq(); sysctrl_unlock(); expr; sysctrl_lock(); enable_irq(flag); } while(0)
#define EFUSE_REG_OPT(expr) do { uint32 flag=disable_irq(); SYSCTRL->SYS_KEY = 0x4c5de9b3; expr; __NOP();__NOP();__NOP(); SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; sysctrl_lock(); enable_irq(flag); } while(0)
#else
#define sysctrl_unlock()
#define sysctrl_lock()
#define SYSCTRL_REG_OPT_INIT() do { SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; SYSCTRL->SYS_KEY = 0x3fac87e4; } while(0)
#define SYSCTRL_REG_OPT(expr) do { expr; } while(0)
#define EFUSE_REG_OPT(expr) do { uint32 flag=disable_irq(); SYSCTRL->SYS_KEY = 0x4c5de9b3; expr; __NOP();__NOP();__NOP(); SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; enable_irq(flag); } while(0)
#endif
#define SYSCTRL_REG_BITS_S0S1(reg, bits) do { SYSCTRL_REG_OPT( reg &= ~(bits); __NOP();__NOP();__NOP(); (reg) |= (bits); ); } while(0)
#define SYSCTRL_REG_BITS_S1S0(reg, bits) do { SYSCTRL_REG_OPT( reg |= (bits); __NOP();__NOP();__NOP(); (reg) &= ~(bits); ); } while(0)
#define SYSCTRL_REG_SET_BITS(reg, bits) do { SYSCTRL_REG_OPT( reg |= (bits); ); } while(0)
#define SYSCTRL_REG_CLR_BITS(reg, bits) do { SYSCTRL_REG_OPT( reg &= ~(bits); ); } while(0)
#define SYSCTRL_REG_SET_VALUE(reg, bit_mask, val, bit_pos) do { SYSCTRL_REG_OPT( reg = ((reg) & ~(bit_mask)) | (((val) << (bit_pos)) & (bit_mask)); ); } while(0)
#define SYSCTRL_REG_BIT_FUN(fun_name, reg, bits)\
__STATIC_INLINE void fun_name##_en(void) { SYSCTRL_REG_SET_BITS(reg, bits); }\
__STATIC_INLINE void fun_name##_dis(void) { SYSCTRL_REG_CLR_BITS(reg, bits); }
enum iis_clk_src {
IIS_CLK_NONE,
IIS_CLK_SYSPLL,
IIS_CLK_USBPLL,
IIS_CLK_XOSC,
};
/* SYS_CON0 */
#define sysctrl_iis1_clk_sel(iis_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, BIT(31)|BIT(30), iis_clk_src, 30)
#define sysctrl_rssi_ck_sel_rssi_done() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(29))
#define sysctrl_rssi_ck_sel_rssi_en() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(29))
#define sysctrl_rssi_sel_rssi_done() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(28))
#define sysctrl_rssi_sel_rssi_en() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(28))
#define sysctrl_dbg_seg9_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, 0xFF00000, n, 20)
#define sysctrl_dbg_seg8_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, 0xFF000, n, 12)
#define sysctrl_iis0_clk_sel(iis_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, BIT(11)|BIT(10), iis_clk_src, 10)
#define sysctrl_mac_pa_en() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(9))
#define sysctrl_mac_pa_dis() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(9))
#define sysctrl_qspi_dlychain_cfg(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, 0x1F0, n, 4)
#define sysctrl_qspi_clkin_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(3))
#define sysctrl_qspi_clkin_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(3))
#define sysctrl_mjpeg_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON0, BIT(2))
#define sysctrl_iis1_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON0, BIT(1))
#define sysctrl_wdt_at_lp_gate_en() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(0))
#define sysctrl_wdt_at_lp_gate_dis() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(0))
/* SYS_CON1 */
#define sysctrl_qspi_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(31))
#define sysctrl_sha_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(30))
#define sysctrl_usb20sie_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(29))
#define sysctrl_dvp_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(28))
#define sysctrl_dma2ahb_sched_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(27))
#define sysctrl_dbg_dma_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(26))
#define sysctrl_rf_dig_calib_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(25))
#define sysctrl_saradc_sys_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(24))
#define sysctrl_modem_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(22))
#define sysctrl_mac_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(21))
#define sysctrl_sdhc_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(20))
#define sysctrl_sdio_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(19))
#define sysctrl_usb20_phy_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(18))
#define sysctrl_pdm_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(17))
#define sysctrl_gmac_sys_rst() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(16))
#define sysctrl_sysaes_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(15))
#define sysctrl_crc_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(14))
#define sysctrl_iis0_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(13))
#define sysctrl_timer_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(12))
#define sysctrl_uart1_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(11))
#define sysctrl_uart0_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(10))
#define sysctrl_tk_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(8))
#define sysctrl_spi2_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(7))
#define sysctrl_spi1_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(6))
#define sysctrl_spi0_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(5))
#define sysctrl_wdt_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, (BIT(4)|BIT(3)))
#define sysctrl_m2m_dma_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(2))
#define sysctrl_memory_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(1))
#define sysctrl_gpio_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(0))
/* SYS_CON2 */
#define sysctrl_pdm_mclk_div(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON2, 0x7F00000, n, 20) /* N > 1 */
enum pdm_clk_src {
PDM_CLK_NONE,
PDM_CLK_SYSPLL,
PDM_CLK_USBPLL,
PDM_CLK_XOSC,
};
#define sysctrl_pdm_clk_sel(pdm_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON2, BIT(19)|BIT(18), pdm_clk_src, 18)
#define sysctrl_xosc_loss_nmi_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(17))
#define sysctrl_xosc_loss_nmi_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(17))
#define sysctrl_xosc_loss_swrc_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(16))
#define sysctrl_xosc_loss_swrc_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(16))
#define sysctrl_sdio_cmd_wk_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(10))
#define sysctrl_sdio_cmd_wk_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(10))
#define sysctrl_cpu_clk_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(9))
#define sysctrl_cpu_clk_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(9))
#define sysctrl_gmac_dma_disable() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(7))
#define sysctrl_gmac_dma_enable() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(7))
#define sysctrl_syserr_int_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(6))
#define sysctrl_syserr_int_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(6))
#define sysctrl_apb1_wr_optimize_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(5)) /* sfr write optimze from 3 to 2 cycle */
#define sysctrl_apb1_wr_optimize_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(5))
#define sysctrl_apb0_wr_optimize_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(4))
#define sysctrl_apb0_wr_optimize_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(4))
#define sysctrl_nmi_port_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(3)) /* PA4 */
#define sysctrl_nmi_port_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(3))
#define sysctrl_iis_duplex_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(0))
#define sysctrl_iis_duplex_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(0))
/* SYS_CON3 */
#define sysctrl_gmac_dbc_pll_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(31), n, 31)
#define sysctrl_dvp_dbc_pll_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(30), n, 30)
#define sysctrl_iis1_mclk_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(29), n, 29)
#define sysctrl_iis0_mclk_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(28), n, 28)
#define sysctrl_iis01_mclk_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(27), n, 27)
enum gpio_dbc_clk_src {
GPIO_DEBUNCE_CLK_RC128K,
GPIO_DEBUNCE_CLK_XOSC,
GPIO_DEBUNCE_CLK_FCLK,
GPIO_DEBUNCE_CLK_RC32K,
};
#define sysctrl_gpioc_dbc_clk_sel(gpio_dbc_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(25)|BIT(24), gpio_dbc_clk_src, 24)
#define sysctrl_gpiob_dbc_clk_sel(gpio_dbc_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(23)|BIT(22), gpio_dbc_clk_src, 22)
#define sysctrl_gpioa_dbc_clk_sel(gpio_dbc_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(21)|BIT(20), gpio_dbc_clk_src, 20)
// #define sysctrl_trng_clk_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(19), n, 19)
#define sysctrl_err_rsp_sdio_bus_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(18))
#define sysctrl_err_rsp_sdio_bus_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(18))
// #define sysctrl_tk_clk_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(17))
// #define sysctrl_tk_clk_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(17))
#define sysctrl_err_rsp_dbus_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(16))
#define sysctrl_err_rsp_dbus_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(16))
#define sysctrl_err_rsp_ibus_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(15))
#define sysctrl_err_rsp_ibus_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(15))
#define sysctrl_audio_mem_pd_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(14))
#define sysctrl_audio_mem_pd_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(14))
#define sysctrl_pll1_clk_sel_120M() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(12))
#define sysctrl_pll1_clk_sel_div3() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(12))
#define sysctrl_pll_src_upll_div4() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(12))
// #define sysctrl_pll_src_spll_div2() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(11))
// #define sysctrl_pll_src_spll_div3() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(11))
#define sysctrl_bb_clk_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(5))
#define sysctrl_bb_clk_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(5))
#define sysctrl_usb_wk_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(4))
#define sysctrl_usb_wk_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(4))
/* SYS_CON6 */
#define sysctrl_dbg_seg3_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0xFF000000, n, 24)
#define sysctrl_dbg_seg2_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0x00FF0000, n, 16)
#define sysctrl_dbg_seg1_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0x0000FF00, n, 8)
#define sysctrl_dbg_seg0_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0x000000FF, n, 0)
/* SYS_CON7 */
#define sysctrl_dbg_seg7_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0xFF000000, n, 24)
#define sysctrl_dbg_seg6_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0x00FF0000, n, 16)
#define sysctrl_dbg_seg5_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0x0000FF00, n, 8)
#define sysctrl_dbg_seg4_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0x000000FF, n, 0)
/* SYS_CON12 */
#define sysctrl_usb_trim_en(n) SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON12, BIT(14))
#define sysctrl_usb_trim_dis(n) SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON12, BIT(14))
/* CLK_CON0 */
/* CLK_CON1 */
#define sysctrl_rf_dac_clk_n_posedge() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(31))
#define sysctrl_rf_dac_clk_n_negedge() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(31))
#define sysctrl_rf_adc_clk_n_posedge() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(30))
#define sysctrl_rf_adc_clk_n_negedge() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(30))
#define sysctrl_rf_adc_sample_clk_n_posedge() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(29))
#define sysctrl_rf_adc_sample_clk_n_negedge() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(29))
enum dvp_pll_src {
DVP_PLL_SRC_XOSC,
DVP_PLL_SRC_SPLL,
DVP_PLL_SRC_UPLL,
};
#define sysctrl_dvp_pll_sel(dvp_pll_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, BIT(28)|BIT(27), dvp_pll_src, 27)
#define sysctrl_qspi_pll_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, BIT(26), n, 26)
#define sysctrl_qspi_clk_sel_spll() do { SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 &= ~(BIT(3));\
SYSCTRL->CLK_CON0 &= ~(BIT(26)); );\
} while(0)
#define sysctrl_qspi_clk_sel_upll() do { SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 &= ~(BIT(3));\
SYSCTRL->CLK_CON1 |= (BIT(26)); );\
} while(0)
#define sysctrl_qspi_clk_sel_hxosc() do { SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 |= (BIT(3));\
SYSCTRL->CLK_CON1 &= ~(BIT(26)); );\
} while(0)
#define sysctrl_qspi_clk_sel_rc10m() do { SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 |= (BIT(3));\
SYSCTRL->CLK_CON1 |= (BIT(26)); );\
} while(0)
enum qspi_clk_src {
QSPI_CLK_NONE,
QSPI_CLK_USBPLL,
QSPI_CLK_XOSC,
QSPI_CLK_RC10M,
};
#define sysctrl_qspi_clk_src_sel(qspi_clk_src)\
do {\
if (qspi_clk_src & BIT(1)) SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON0, BIT(3));\
else SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON0, BIT(3));\
if (qspi_clk_src & BIT(0)) SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(26));\
else SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(26));\
} while (0)
#define sysctrl_qspi_clk_src_get() (SYSCTRL->CLK_CON0 & BIT(3)) ? ((SYSCTRL->CLK_CON1 & BIT(26)) ? 0x3 : 0x2) : ((SYSCTRL->CLK_CON1 & BIT(26)) ? 0x1 : 0x0);
enum ospi_clk_src {
OSPI_CLK_NONE,
OSPI_CLK_USBPLL,
OSPI_CLK_XOSC,
OSPI_CLK_RC10M,
};
#define sysctrl_ospi_clk_src_sel(ospi_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON4, BIT(22)|BIT(21), ospi_clk_src, 21)
#define sysctrl_ospi_clk_src_get() ((SYSCTRL->CLK_CON4 & (BIT(22)|BIT(21))) >> 21)
#define sysctrl_ospi_clk_en() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON4, BIT(23));
#define sysctrl_ospi_clk_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON4, BIT(23));
#define sysctrl_ospi_set_clk_div(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON4, 0x1f000000, ((n)-1), 24)
#define sysctrl_ospi_get_clk_div() ((SYSCTRL->CLK_CON4 & 0x1f000000) >> 24)
#define sysctrl_ospi_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->CLK_CON4, BIT(20))
#define sysctrl_audac_reset() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON4, BIT(17))
#define sysctrl_audac_en() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON4, BIT(17));
#define sysctrl_auadc_reset() SYSCTRL_REG_BITS_S0S1(SYSCTRL->CLK_CON4, BIT(16))
enum rfadc_pll_sel {
RF_ADC_PLL_80MHZ,
RF_ADC_PLL_40MHZ = 2,
RF_ADC_PLL_20MHZ = 3,
};
#define sysctrl_adda_cnt_pr(rfadc_pll_sel) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, BIT(25)|BIT(24), rfadc_pll_sel, 24)
#define sysctrl_apb1_clk_div(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x00FF0000, n, 16)
#define sysctrl_apb0_clk_div(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x0000FF00, n, 8)
#define sysctrl_mac_clk_sel(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x000000C0, n, 6)
#define sysctrl_sys_clk_div(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x0000003F, n, 0)
/* CKL_CON2 */
#define sysctrl_dvp_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(31))
#define sysctrl_dvp_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(31))
#define sysctrl_qspi_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(30))
#define sysctrl_qspi_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(30))
#define sysctrl_tmr0_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(29))
#define sysctrl_tmr0_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(29))
#define sysctrl_test_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(28))
#define sysctrl_test_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(28))
#define sysctrl_stmr_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(27))
#define sysctrl_stmr_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(27))
#define sysctrl_tmr3_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(26))
#define sysctrl_tmr3_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(26))
#define sysctrl_rfdac_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(25))
#define sysctrl_rfdac_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(25))
#define sysctrl_rfadda_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(24))
#define sysctrl_rfadda_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(24))
#define sysctrl_rf_pclk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(23))
#define sysctrl_rf_pclk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(23))
#define sysctrl_modem_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(22))
#define sysctrl_modem_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(22))
#define sysctrl_mac_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(21))
#define sysctrl_mac_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(21))
#define sysctrl_sdhc_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(20))
#define sysctrl_sdhc_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(20))
#define sysctrl_sddev_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(19))
#define sysctrl_sddev_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(19))
#define sysctrl_usb20_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(18))
#define sysctrl_usb20_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(18))
#define sysctrl_pdm_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(17))
#define sysctrl_pdm_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(17))
#define sysctrl_simtmr_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(16))
#define sysctrl_simtmr_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(16))
#define sysctrl_sysaes_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(15))
#define sysctrl_sysaes_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(15))
#define sysctrl_crc_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(14))
#define sysctrl_crc_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(14))
#define sysctrl_iis0_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(13))
#define sysctrl_iis0_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(13))
#define sysctrl_tmr1_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(12))
#define sysctrl_tmr1_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(12))
#define sysctrl_uart1_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(11))
#define sysctrl_uart1_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(11))
#define sysctrl_uart0_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(10))
#define sysctrl_uart0_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(10))
#define sysctrl_tmr2_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(8))
#define sysctrl_tmr2_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(8))
#define sysctrl_spi2_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(7))
#define sysctrl_spi2_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(7))
#define sysctrl_spi1_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(6))
#define sysctrl_spi1_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(6))
#define sysctrl_spi0_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(5))
#define sysctrl_spi0_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(5))
#define sysctrl_wdt_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(3))
#define sysctrl_wdt_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(3))
#define sysctrl_ahb1_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(2))
#define sysctrl_ahb1_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(2))
#define sysctrl_ahb0_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(1))
#define sysctrl_ahb0_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(1))
#define sysctrl_adkey_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(0))
#define sysctrl_adkey_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(0))
/* CLK_CON3 */
#define sysctrl_dvp_mclk_div(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON3, 0xFC000000, n, 26)
#define sysctrl_cache_en() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(25))
#define sysctrl_cache_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(25))
#define sysctrl_lmac_fifo_en() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(24))
#define sysctrl_lmac_fifo_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(24))
#define sysctrl_lvd_dbc_clk_en() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(23))
#define sysctrl_lvd_dbc_clk_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(23))
enum lvd_dbc_clk_src {
LVD_DEBUNCE_CLK_RC128K,
LVD_DEBUNCE_CLK_XOSC,
LVD_DEBUNCE_CLK_FCLK,
LVD_DEBUNCE_CLK_RC32K,
};
#define sysctrl_lvd_dbg_clk_sel(lvd_dbc_clk_src) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON3, BIT(22)|BIT(21), lvd_dbc_clk_src, 21)
#define sysctrl_sysmonitor_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(20))
#define sysctrl_sysmonitor_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(20))
#define sysctrl_m2mdma_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(19))
#define sysctrl_m2mdma_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(19))
#define sysctrl_iis1_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(18))
#define sysctrl_iis1_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(18))
#define sysctrl_gmac_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(17))
#define sysctrl_gmac_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(17))
#define sysctrl_rom_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(16))
#define sysctrl_rom_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(16))
#define sysctrl_apb1_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(15))
#define sysctrl_apb1_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(15))
#define sysctrl_mjpeg_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(14))
#define sysctrl_mjpeg_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(14))
#define sysctrl_sdio_fifo_open() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(14))
#define sysctrl_sdio_fifo_close() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(14))
#define sysctrl_qspi_pll_div(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON3, BIT(13)|BIT(12)|BIT(11), n, 11)
#define sysctrl_qspi_get_clk_div() ((SYSCTRL->CLK_CON3 & 0x00003800) >> 11)
#define sysctrl_sram10_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(10))
#define sysctrl_sram10_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(10))
#define sysctrl_sram9_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(9))
#define sysctrl_sram9_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(9))
#define sysctrl_sram8_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(8))
#define sysctrl_sram8_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(8))
#define sysctrl_sram7_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(7))
#define sysctrl_sram7_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(7))
#define sysctrl_sram6_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(6))
#define sysctrl_sram6_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(6))
#define sysctrl_sram5_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(5))
#define sysctrl_sram5_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(5))
#define sysctrl_sram4_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(4))
#define sysctrl_sram4_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(4))
#define sysctrl_sram3_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(3))
#define sysctrl_sram3_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(3))
#define sysctrl_sram2_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(2))
#define sysctrl_sram2_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(2))
#define sysctrl_sram1_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(1))
#define sysctrl_sram1_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(1))
#define sysctrl_sram0_clk_open() SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(0))
#define sysctrl_sram0_clk_close() SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(0))
/* CHIP_ID */
#define sysctrl_get_chip_dcn() ((uint16)(SYSCTRL->CHIP_ID >> 16))
/* SRAM0_PD_CON */
#define sysctrl_sram0_pd_exit_cnt(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SRAM0_PD_CON, 0x001FF800, n, 11)
#define sysctrl_sram0_pd_enter_cnt(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->SRAM0_PD_CON, 0x000007Fe, n, 1)
#define sysctrl_sram0_hw_pd_en() SYSCTRL_REG_SET_BITS(SYSCTRL->SRAM0_PD_CON, BIT(0))
#define sysctrl_sram0_hw_pd_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->SRAM0_PD_CON, BIT(0))
/* IO_MAP */
/* MBIST_CTRL */
#define sysctrl_get_softreset_pending() ((SYSCTRL->MBIST_CTRL & BIT(31)))
#define sysctrl_clr_softreset_pending() ((SYSCTRL->MBIST_CTRL = 0x80000000))
/* EFUSE_CON */
#define sysctrl_efuse_pwron_init() SYSCTRL_REG_SET_BITS(SYSCTRL->EFUSE_CON, BIT(1)|BIT(0))
/* SYS_ERR0 */
/* SYS_ERR1 */
/* HOSC_MNT */
#define sysctrl_hosc_mnt_high_limit(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->HOSC_MNT, 0xFFFF0000, n, 16)
#define sysctrl_hosc_mnt_en() SYSCTRL_REG_SET_BITS(SYSCTRL->HOSC_MNT, BIT(15))
#define sysctrl_hosc_mnt_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->HOSC_MNT, BIT(15))
#define sysctrl_hosc_lost_pend_clr() SYSCTRL_REG_SET_BITS(SYSCTRL->HOSC_MNT, BIT(14))
#define sysctrl_hosc_mnt_low_limit(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->HOSC_MNT, 0x00003FFF, n, 0)
/* WK_CTRL */
/* LP_CTRL */
/* MPE0~5 */
void sysctrl_memory_protect_config(uint32 start_addr, uint32 size, uint8 enable);
#define sysctrl_get_mem_protect_pending() ((SYSCTRL->MPE_PND[0] | SYSCTRL->MPE_PND[1] | SYSCTRL->MPE_PND[2]))
/* MODE_REG */
#define sysctrl_get_buck_cmpfb_sta() ((SYSCTRL->MODE_REG & BIT(31)))
#define sysctrl_get_buck_dtmod_index_sta() ((SYSCTRL->MODE_REG & BIT(30)))
#define sysctrl_get_buck_ipeaktrimout_sta() ((SYSCTRL->MODE_REG & BIT(29)))
#define sysctrl_get_buck_irptrimout_sta() ((SYSCTRL->MODE_REG & BIT(28)))
#define sysctrl_get_ft_mode() ((SYSCTRL->MODE_REG & BIT(1)))
#define sysctrl_get_cp_mode() ((SYSCTRL->MODE_REG & BIT(0)))
/* QSPI_MAP_CTL */
#define sysctrl_set_qspi_iomap(iomap) SYSCTRL_REG_OPT(SYSCTRL->QSPI_MAP_CTL = iomap;);
#define sysctrl_get_qspi_iomap() ((SYSCTRL->QSPI_MAP_CTL))
/* QSPI_ENCDEC_CON0 */
#define sysctrl_get_xip_scramble_sta() (SYSCTRL->QSPI_ENCDEC_CON0 & (BIT(31)))
#define sysctrl_xip_scramble_disable() SYSCTRL_REG_OPT( SYSCTRL->QSPI_ENCDEC_CON0 &= ~(BIT(31)); );
#define sysctrl_xip_scramble_enable() SYSCTRL_REG_OPT( SYSCTRL->QSPI_ENCDEC_CON0 |= (BIT(31)); );
#define sysctrl_xip_scramble_toggle() SYSCTRL_REG_OPT( SYSCTRL->QSPI_ENCDEC_CON0 ^= (BIT(31)); );
/* TRNG */
#define sysctrl_get_trng() ((SYSCTRL->TRNG))
/* DCRC_TRIM */
#define sysctrl_set_dc_trim_init_val(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x00fc0000, n, 18)
#define sysctrl_set_dc_trim_range(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x0003c000, n, 14)
#define sysctrl_set_dc_trim_step(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x00003e00, n, 9)
#define sysctrl_set_dc_trim_1us_prd(n) SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x000001fe, n, 1)
#define sysctrl_dc_trim_en() SYSCTRL_REG_SET_BITS(SYSCTRL->DCRC_TRIM, BIT(0))
#define sysctrl_dc_trim_dis() SYSCTRL_REG_CLR_BITS(SYSCTRL->DCRC_TRIM, BIT(0))
typedef struct
{
__IO uint32 CTRL_CON; //0x00
__IO uint32 BURST_CON0; //0x04
__IO uint32 BURST_CON1; //0x08
__IO uint32 BASE_CON0; //0x0c
__IO uint32 BASE_CON1; //0x10
__IO uint32 BASE_CON2; //0x14
__IO uint32 BASE_CON3; //0x18
__IO uint32 BASE_CON4; //0x1c
__IO uint32 BASE_CON5; //0x20
__IO uint32 BASE_CON6; //0x24
__IO uint32 BASE_CON7; //0x28
__IO uint32 FIFO_EN; //0x2c
__IO uint32 BW_STA_CYCLE; //0x30
__IO uint32 BW_STA_CNT; //0x34
__IO uint32 FLASH_RD_EN; //0x38 : 0x20028008
} SCHED_TypeDef;
#define SCHED ((SCHED_TypeDef *) HG_SCHED_BASE)
/* DMA2AHB */
enum sysctrl_dma2ahb_burst_obj {
DMA2AHB_BURST_OBJ_QSPI,
DMA2AHB_BURST_OBJ_OSPI,
};
/* unit: byte, total memery is pingpong, need x2 */
enum sysctrl_dma2ahb_burst_size {
DMA2AHB_BURST_SIZE_0,
DMA2AHB_BURST_SIZE_16,
DMA2AHB_BURST_SIZE_32,
DMA2AHB_BURST_SIZE_64,
};
enum sysctrl_dma2ahb_burst_chanel {
DMA2AHB_BURST_CH_LCD_ROTATE_RD ,
DMA2AHB_BURST_CH_VPP_IPF_RD , /* flash & psram */
DMA2AHB_BURST_CH_OSD0_RD ,
DMA2AHB_BURST_CH_LMAC_RX_WR ,
DMA2AHB_BURST_CH_LMAC_TX_RD ,
DMA2AHB_BURST_CH_LMAC_WAVE_RD ,
DMA2AHB_BURST_CH_LMAC_WAVE_WR ,
DMA2AHB_BURST_CH_GMAC_TX_RD ,
DMA2AHB_BURST_CH_SCALE3_Y_WR ,
DMA2AHB_BURST_CH_SCALE3_U_WR ,
DMA2AHB_BURST_CH_SCALE3_V_WR ,
DMA2AHB_BURST_CH_MJPEG1_SCALE2_YUV_WR ,
DMA2AHB_BURST_CH_UNUSED,
DMA2AHB_BURST_CH_MJPEG1_RD , /* flash & psram */
DMA2AHB_BURST_CH_MJPEG0_VPP_WR ,
DMA2AHB_BURST_CH_OSD_ENC_RD ,
DMA2AHB_BURST_CH_OSD_ENC_WR ,
DMA2AHB_BURST_CH_LMAC_HDR_RD,
DMA2AHB_BURST_CH_SYSAES_WR ,
DMA2AHB_BURST_CH_SYSAES_RD , /* flash & psram */
DMA2AHB_BURST_CH_SHA_RD , /* flash & psram */
DMA2AHB_BURST_CH_CRC_RD , /* flash & psram */
DMA2AHB_BURST_CH_M2M0_RD ,
/* flash & psram */
DMA2AHB_BURST_CH_M2M0_WR ,
DMA2AHB_BURST_CH_M2M1_RD , /* flash & psram */
DMA2AHB_BURST_CH_M2M1_WR ,
DMA2AHB_BURST_CH_AUDIO_RD ,
DMA2AHB_BURST_CH_CODEC_RD ,
DMA2AHB_BURST_CH_CODEC_WR ,
DMA2AHB_BURST_CH_SDH_RD ,
DMA2AHB_BURST_CH_SDH_WR ,
};
/* CTRLCON */
int32 ll_sysctrl_dma2ahb_burst_set(enum sysctrl_dma2ahb_burst_chanel ch, enum sysctrl_dma2ahb_burst_size size) ;
__STATIC_INLINE void ll_sysctrl_dma2ahb_select(enum sysctrl_dma2ahb_burst_obj obj) {
SCHED->CTRL_CON = (SCHED->CTRL_CON & ~(0x1UL << 0)) | ((obj & 0x1) << 0);
}
__STATIC_INLINE void ll_sysctrl_dma2ahb_osd_enc_rd_lmac_wave_rd_priority_switch(uint8 enable) {
if (enable) {
SCHED->CTRL_CON |= (BIT(4));
} else {
SCHED->CTRL_CON &= ~(BIT(4));
}
}
__STATIC_INLINE void ll_sysctrl_dma2ahb_pri_switch(uint32 pri) {
SCHED->CTRL_CON &= ~(0xfff<<8);
SCHED->CTRL_CON |= (pri<<8);
}
__STATIC_INLINE void ll_sysctrl_dma2ahb_m2m1_wr_lmac_wave_wr_priority_switch(uint8 enable) {
if (enable) {
SCHED->CTRL_CON |= (BIT(5));
} else {
SCHED->CTRL_CON &= ~(BIT(5));
}
}
__STATIC_INLINE void ll_sysctrl_dma2ahb_m2m1_rd_gmac_tx_rd_priority_switch(uint8 enable) {
if (enable) {
SCHED->CTRL_CON |= (BIT(6));
} else {
SCHED->CTRL_CON &= ~(BIT(6));
}
}
__STATIC_INLINE int32 ll_sysctrl_dma2ahb_is_busy(enum sysctrl_dma2ahb_burst_chanel ch) {
return (SCHED->FIFO_EN & BIT(ch));
}
__STATIC_INLINE int32 ll_sysctrl_dma2ahb_busy_sta(void) {
return SCHED->FIFO_EN;
}
#define sysctrl_dma2ahb_bw_io_freq_set(hz) do {SCHED->BW_STA_CYCLE = hz;} while (0)
#define sysctrl_dma2ahb_bw_calc_en() do {SCHED->CTRL_CON |= BIT(1);} while (0)
#define sysctrl_dma2ahb_bw_calc_dis() do {SCHED->CTRL_CON &= ~ BIT(1);} while (0)
#define sysctrl_get_dma2ahb_bw_byteps() (SCHED->BW_STA_CNT)
#define sysctrl_dma2ahb_bw_is_calc_en() (SCHED->CTRL_CON & BIT(1))
/**
* @}
*/
int32 sys_get_apbclk(void);
int32 sys_get_sysclk(void);
int32 sys_set_sysclk(uint32 system_clk);
void mcu_reset(void);
void mcu_watchdog_timeout(uint8 tmo_sec);
void mcu_watchdog_timeout_level(uint8 level);
void mcu_watchdog_irq_request(void *hdl);
void mcu_watchdog_feed(void);
#ifdef CONFIG_SLEEP
void lp_watchdog_timeout(uint8 tmo_sec);
void lp_watchdog_feed(void);
#endif
void system_enter_sleep(void);
void system_exit_sleep(void);
void sysctrl_cmu_init(void);
bool sysctrl_cmu_upll_init(void);
bool sysctrl_cmu_sysclk_set(uint32 clk, bool is_upll);
#define sysctrl_gmac_clk_sel_clk_from_io()
/**
* @brief system_clock_set
* @param clk_hz : clk wish to be set
* @retval OK or ERR
* @note
*/
int32 system_clock_set(uint32 clk_hz);
/**
* @brief system_clock_get
* @retval system clk_hz
* @note this function will get the clock form sotfware temp storage
*/
uint32 system_clock_get(void);
/**
* @brief system_clock_get_refresh
* @retval system clk_hz
* @note this function will get the clock form hardware
*/
uint32 system_clock_get_refresh(void);
/**
* @brief peripheral_clock_set
* @param peripheral : HG_Peripheral_Type
* @param clk_hz : Peripheral clk_hz
* @retval ok or err
* @note peripheral on same bus apb0/1 clk must be same
*/
int32 peripheral_clock_set(HG_Peripheral_Type peripheral, uint32 clk_hz);
/**
* @brief peripheral_clock_get
* @param peripheral : HG_Peripheral_Type
* @retval clk_hz
*/
uint32 peripheral_clock_get(HG_Peripheral_Type peripheral);
uint16 sysctrl_get_chip_id(void);
uint32 sysctrl_efuse_get_chip_uuid(uint8* pbuf, uint32 len);
uint32 sysctrl_efuse_get_aes_key_but_return_crc16(void);
uint32 sysctrl_efuse_validity_get(void);
void sysctrl_efuse_validity_handle(void);
void sysctrl_efuse_info_show(void);
uint32 sysctrl_efuse_vddi_get(void);
uint32 sysctrl_efuse_tsensor_get(void);
uint32 sysctrl_efuse_vddi_gears_get(void);
uint32 sysctrl_efuse_adda_vref_get(void);
uint32 sysctrl_efuse_aubias_sel_vref100_vdd(void);
uint32 sysctrl_efuse_aubias_sel_vcmau_vdd(void);
uint32 sysctrl_efuse_aubias_sel_vcc27au_vdd(void);
uint32 sysctrl_efuse_audio_en(void);
void sysctrl_rst_lmac_phy(void);
int32 sysctrl_err_resp_disable(void);
uint8 sysctrl_efuse_get_bios_id(void);
uint8 sysctrl_efuse_get_module_type(void);
void system_clocks_show(void);
void sysctrl_gpio_funcmap_default(void);
void system_goto_boot(void);
void system_reboot_test_mode(void);
void system_reboot_normal_mode(void);
int32 system_is_wifi_test_mode(void);
void system_qspi_pretect_all(void);
uint8 get_chip_pack(void);
uint8 get_bios_id(void);
#define sysctrl_dma_bridge_reset()
#ifdef __cplusplus
}
#endif
#endif //__SYSCTRL_H__
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2019 HUGE-IC *****END OF FILE****/
sdk/include/chip/txw81x/test_atcmd.h
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#ifndef _TXW81X_TEST_ATCMD_H_
#define _TXW81X_TEST_ATCMD_H_
#ifdef __cplusplus
extern "C" {
#endif
int32 atcmd_reg_rd_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_reg_wt_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_test_start_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_test_addr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_temp_en_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_type_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_rf_pwr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_pha_amp_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_step_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_cont_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_start_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_trig_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_frm_type_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_mcs_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_lo_freq_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_edca_cw_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_edca_aifs_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_edca_txop_hdl(const char *cmd, char *argv[], uint32 argc);
int32 at_cmd_cfg_rx_agc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_lmac_print_period_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_bss_bw_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 at_cmd_cca_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_rx_cnt_clr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_rx_cnt_get_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_tx_delay_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_wave_dump_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_write_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_write_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_write_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_dbg_level_hdl(const char *cmd, char *argv[], uint32 argc);
int32 sys_atcmd_reset(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_max_txcnt_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_pcf_en_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_pcf_chn_hdl(const char *cmd, char *argv[], uint32 argc);
#ifdef CONFIG_SLEEP
int32 atcmd_sleep_dbg_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_sleep_alg_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_sleep_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_dtim_hdl(const char *cmd, char *argv[], uint32 argc);
#endif
int32 atcmd_set_tx_timeout_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_cca_cert_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_set_srrc_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_start_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_tx_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_rx_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_rx_cnt_clr_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_rx_cnt_get_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_tx_delay_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_chan_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_rx_timeout_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_ble_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_write_ble_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_io_test_hdl(const char *cmd, char *argv[], uint32 argc);
int32 atcmd_io_test_res_get_hdl(const char *cmd, char *argv[], uint32 argc);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/chip/txw81x/ticker.h
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#ifndef _TICKER_H_
#define _TICKER_H_
#ifdef __cplusplus
extern "C" {
#endif
//#define TIMER0_BASE (APB1_BASE + 0x5000)
#define TIMER0 ((struct hgtimer_v2_hw *) TIMER0_BASE)
#define HW_TIMER_PSC 7//HGTIMER_V2_TIMER_PSC_128
/**
* @brief Time(us) to timer tick
* @param n : Time in us
* @retval Time(us) to timer tick
*/
#define HW_TIMER_T2C(n) (((n)*(system_clock_get()/1000000)) >> (HW_TIMER_PSC))
/**
* @brief timer tick to Time(us)
* @param n : timer tick
* @retval timer tick to Time(us)
*/
#define HW_TIMER_C2T(n) ((n)*(1 << HW_TIMER_PSC)/(system_clock_get()/1000000))
/**
* @brief The tick timer is initialized.
* @param None
* @retval None
* @note Use the lowest priority interrupt.
*/
//void hw_timer_init(void);
/**
* @brief get the tick of the timer.
* @param None
* @retval None
*/
//uint32 hw_timer_get_tick(uint8 start);
/**
* @brief tick timer interrupt handler.
* @param None
* @retval None
*/
//void hw_timer_irq_handler(void);
#ifdef __cplusplus
}
#endif
#endif
sdk/include/chip/txw81x/txw81x.h
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#ifndef _TXW81X_DEF_H_
#define _TXW81X_DEF_H_
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "typesdef.h"
/* ------------------------- Interrupt Number Definition ------------------------ */
enum IRQn
{
/****** Peripheral Interrupt Numbers *********************************************************/
USB20DMA_IRQn = 0,
USB20MC_IRQn = 1,
UART0_IRQn = 2,
UART1_IRQn = 3,
LCD_IRQn = 4,
QSPI_IRQn = 5,
SPI0_IRQn = 6,
SPI1_IRQn = 7,
SPI2_IRQn = 8,
OSPI_IRQn = 9,
TIM0_IRQn = 10,
TIM1_IRQn = 11,
TIM2_IRQn = 12,
TIM3_IRQn = 13,
SCALE1_IRQn = 14,
AUDIO_SUBSYS0_IRQn = 15, //ALAW & HS & VAD
AUDIO_SUBSYS1_IRQn = 16, //ADC
AUDIO_SUBSYS2_IRQn = 17, //DAC
SDIO_IRQn = 18,
SDIO_RST_IRQn = 19,
SDHOST_IRQn = 20,
LMAC_IRQn = 21,
GMAC_IRQn = 22,
M2M0_IRQn = 23,
M2M1_IRQn = 24,
CORET_IRQn = 25, //CPU TIMER
SPACC_PKA_IRQn = 26, //SHA/SYS_AES
CRC_IRQn = 27,
ADKEY01_IRQn = 28,
PD_TMR_IRQn = 29,
WKPND_IRQn = 30,
PDWKPND_IRQn = 31,
LVD_IRQn = 32,
WDT_IRQn = 33,
SYS_ERR_IRQn = 34,
IIS0_IRQn = 35,
IIS1_IRQn = 36,
GPIOABCE_IRQn = 37,
//GPIODE_IRQn = 38,
DVP_IRQn = 39,
MJPEG01_IRQn = 40,
//CSI2_IRQn = 41,
VPP_IRQn = 42,
PRC_IRQn = 43,
STMR012345_IRQn = 44,
PDM_IRQn = 45,
LED_TMR_IRQn = 46,
SCALE2_IRQn = 47,
GFSK_IRQn = 48,
CMPOUT01_IRQn = 49,
UART45_IRQn = 50,
SCALE3_IRQn = 51,
//SPI5_IRQn = 52,
//SPI6_IRQn = 53,
//LED_IRQn = 54,
//SUPTMR3_IRQn = 55,
//SUPTMR4_IRQn = 56,
//SUPTMR5_IRQn = 57,
USB20PHY_RTC_IRQn = 58,
//TK_IRQn = 59,
//CPU0_SPINLOCK_IRQn = 60,
//CPU0_SEND_MAIL_IRQn = 61,
//CPU0_RECV_MAIL_IRQn = 62,
//AUDIO_SUBSYS_IRQn = 63,
SHA_VIRTUAL_IRQn = 64,
AES_VIRTUAL_IRQn = 65,
UART4_IRQn = 66,
UART5_IRQn = 67,
GPIOA_IRQn = 68,
GPIOB_IRQn = 69,
GPIOC_IRQn = 70,
GPIOE_IRQn = 71,
AUVAD_IRQn = 72,
AUHS_IRQn = 73,
AUALAW_IRQn = 74,
IRQ_NUM,
};
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the CK803 Processor and Core Peripherals ------- */
#define __CK803_REV 0x0000U /* Core revision r0p0 */
#define __MPU_PRESENT 0 /* MGU present or not */
#define __VIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include "csi_core.h" /* Processor and core peripherals */
#include "stdint.h"
////////
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define SRAM_END_ADDR ((uint32_t)0x20044000) /*!< SRAM end address in the alias region */
#define PSRAM_BASE ((uint32_t)0x38000000) /*!< SRAM base address in the alias region */
#define PSRAM_END_ADDR (PSRAM_BASE + 16*1024*1024) /*!< SRAM end address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
/*!< Peripheral memory map */
#define APB0_BASE PERIPH_BASE
#define APB1_BASE (PERIPH_BASE + 0x10000)
#define AHB_BASE (PERIPH_BASE + 0x20000)
#define QSPI_BASE (APB0_BASE + 0x0000)
#define HG_OSPI_BASE (APB0_BASE + 0x1000)
#define HG_SCHED_BASE (APB0_BASE + 0x2000)
#define HG_UART0_BASE (APB0_BASE + 0x4000)
#define HG_UART1_BASE (APB0_BASE + 0x4100)
#define HG_UART2_BASE (APB0_BASE + 0x4200)
#define HG_UART3_BASE (APB0_BASE + 0x4300)
#define HG_UART4_BASE (APB0_BASE + 0x4b70)
#define HG_UART5_BASE (APB0_BASE + 0x4b90)
#define SPI0_BASE (APB0_BASE + 0x4400)
#define SPI1_BASE (APB0_BASE + 0x4500)
#define SPI2_BASE (APB0_BASE + 0x4600)
#define SPI3_BASE (APB0_BASE + 0x4700)
#define SPI4_BASE (APB0_BASE + 0x4800)
#define SPI5_BASE (APB0_BASE + 0x4b20)
#define SPI6_BASE (APB0_BASE + 0x4b38)
#define HG_LED_BASE (APB0_BASE + 0x4b50)
#define IIC1_BASE (APB0_BASE + 0x4500)
#define IIC2_BASE (APB0_BASE + 0x4600)
#define IIC3_BASE (APB0_BASE + 0x4700)
#define IIC4_BASE (APB0_BASE + 0x4800)
#define HG_IIS0_BASE (APB0_BASE + 0x80C0)
#define HG_IIS1_BASE (APB0_BASE + 0x80E0)
#define HG_PDM_BASE (APB0_BASE + 0x8110)
#define PRC_BASE (APB0_BASE + 0x5000)
#define OF_BASE (APB0_BASE + 0x5020)
#define DVP_BASE (APB0_BASE + 0x5040)
#define VPP_BASE (APB0_BASE + 0x5080)
#define JPG0_BASE (APB0_BASE + 0x5100)
#define JPG1_BASE (APB0_BASE + 0x5200)
#define MJPEG0_TAB_BASE (APB0_BASE + 0x5180)
#define MJPEG1_TAB_BASE (APB0_BASE + 0x5280)
#define CSI2_HOST_BASE (APB0_BASE + 0x5700)
#define TK_BASE (APB0_BASE + 0x6000)
#define SCALE0_BASE (APB0_BASE + 0x7000)
#define SCALE1_BASE (APB0_BASE + 0x7100)
#define LCDC_BASE (APB0_BASE + 0x7000)
#define SCALE2_BASE (APB0_BASE + 0x71A0)
#define SCALE3_BASE (APB0_BASE + 0x7200)
#define AUDIO_BASE (APB0_BASE + 0x8000)
#define COMP_BASE (APB0_BASE + 0x9000)
#define EFUSE_BASE (APB0_BASE + 0xa000)
#define HG_SYSAES_BASE (APB1_BASE + 0x2000)
//#define RFADCDIG_BASE (APB1_BASE + 0x4000)
#define HG_SHA_BASE (APB1_BASE + 0x4000)
#define WDT_BASE (APB1_BASE + 0x5000)
#define TIMER_ALL_BASE (APB1_BASE + 0x5128)
#define TIMER0_BASE (APB1_BASE + 0x5100)
#define TIMER1_BASE (APB1_BASE + 0x5200)
#define TIMER2_BASE (APB1_BASE + 0x5300)
#define TIMER3_BASE (APB1_BASE + 0x5400)
#define TIMER4_BASE (APB1_BASE + 0x5500)
//#define TIMER5_BASE (APB1_BASE + 0x5600)
//#define TIMER6_BASE (APB1_BASE + 0x5700)
//#define TIMER7_BASE (APB1_BASE + 0x5800)
#define SUPTMR_BASE (APB1_BASE + 0x5600)
#define SIMPLE_TIMER0_BASE (APB1_BASE + 0x5B00)
#define SIMPLE_TIMER1_BASE (APB1_BASE + 0x5B10)
#define SIMPLE_TIMER2_BASE (APB1_BASE + 0x5B20)
#define SIMPLE_TIMER3_BASE (APB1_BASE + 0x5B30)
#define SIMPLE_TIMER4_BASE (APB1_BASE + 0x5B40)
#define SIMPLE_TIMER5_BASE (APB1_BASE + 0x5B50)
//#define HG_RTC_BASE (APB1_BASE + 0x8050)
#define HG_CRC32_BASE (APB1_BASE + 0x7000)
#define PMU_BASE (APB1_BASE + 0x8000)
#define LVD_BASE (APB1_BASE + 0x8000)
#define RFDIG_BASE (APB1_BASE + 0x9000)
#define ADKEY_BASE (APB1_BASE + 0xa000)
#define ADKEY1_BASE (APB1_BASE + 0xa00c)
#define ZH_RFSPI_BASE (APB1_BASE + 0xb000)
#define RFDIGCAL_BASE (APB1_BASE + 0xd000)
#define HG_SYSCTRL_BASE (AHB_BASE + 0x0000)
#define HG_GPIOA_BASE (AHB_BASE + 0x0a00)
#define HG_GPIOB_BASE (AHB_BASE + 0x0b00)
#define HG_GPIOC_BASE (AHB_BASE + 0x0c00)
#define HG_GPIOD_BASE (AHB_BASE + 0x0d00)
#define HG_GPIOE_BASE (AHB_BASE + 0x0e00)
#define HG_GPIOF_BASE (AHB_BASE + 0x0f00)
#define HG_GPIOG_BASE (AHB_BASE + 0x1000)
#define HG_GPIOH_BASE (AHB_BASE + 0x1100)
#define M2M_DMA_BASE (AHB_BASE + 0x1200)
#define M2M_DMA0_BASE (AHB_BASE + 0x1200)
#define M2M_DMA1_BASE (AHB_BASE + 0x121C)
#define SYS_MNT_BASE (AHB_BASE + 0x1300)
#define SDHOST_BASE (AHB_BASE + 0x1400)
#define LED_TIMER0_BASE (PMU_BASE + 0x000d0)
#define LED_TIMER1_BASE (PMU_BASE + 0x000d4)
#define LED_TIMER2_BASE (PMU_BASE + 0x000d8)
#define LED_TIMER3_BASE (PMU_BASE + 0x000dc)
#define HG_SUPTMR_COMM_BASE (SUPTMR_BASE )
#define HG_SUPTMR0_BASE (APB1_BASE + 0x5B00)
#define HG_SUPTMR1_BASE (APB1_BASE + 0x5B10)
#define HG_SUPTMR2_BASE (APB1_BASE + 0x5B20)
#define HG_SUPTMR3_BASE (APB1_BASE + 0x5B30)
#define HG_SUPTMR4_BASE (APB1_BASE + 0x5B40)
#define HG_SUPTMR5_BASE (APB1_BASE + 0x5B50)
#define HG_SDIO20_SLAVE_BASE (AHB_BASE + 0x20000)
#define MODEM_BASE (AHB_BASE + 0x40000)
#define LMAC_BASE (AHB_BASE + 0x42000)
#define HG_GMAC_BASE (AHB_BASE + 0x51000)
#define HG_USB20_DEVICE_BASE (AHB_BASE + 0xd0000)
typedef enum {
HG_AHB_PT_ALL,
HG_AHB_PT_GPIOA_DEBUNCE,
HG_AHB_PT_GPIOB_DEBUNCE,
HG_AHB_PT_GPIOC_DEBUNCE,
HG_AHB_PT_M2M_DMA,
HG_AHB_PT_SYS_MNT,
HG_AHB_PT_SDMMC,
HG_AHB_PT_SDIO,
HG_AHB_PT_MODEM,
HG_AHB_PT_LMAC,
HG_AHB_PT_GMAC,
HG_AHB_PT_USB20,
HG_APB0_PT_ALL,
HG_APB0_PT_QSPI,
HG_APB0_PT_OSPI,
HG_APB0_PT_UART0,
HG_APB0_PT_UART1,
HG_APB0_PT_UART4,
HG_APB0_PT_UART5,
HG_APB0_PT_SPI0,
HG_APB0_PT_SPI1,
HG_APB0_PT_SPI2,
HG_APB0_PT_SPI3,
HG_APB0_PT_SPI5,
HG_APB0_PT_SPI6,
HG_APB0_PT_LED,
HG_APB0_PT_IIC0,
HG_APB0_PT_IIC1,
HG_APB0_PT_IIC2,
HG_APB0_PT_IIC3,
HG_APB0_PT_IIS0,
HG_APB0_PT_IIS1,
HG_APB0_PT_PDM,
HG_APB0_PT_JPEG,
HG_APB0_PT_DVP,
HG_APB0_PT_CMP,
HG_APB0_PT_EFUSE,
HG_APB1_PT_ALL,
HG_APB1_PT_AES,
HG_APB1_PT_WDT,
HG_APB1_PT_TMR0,
HG_APB1_PT_TMR1,
HG_APB1_PT_TMR2,
HG_APB1_PT_TMR3,
HG_APB1_PT_STMR,
HG_APB1_PT_SUPTMR,
HG_APB1_PT_CRC,
HG_APB1_PT_PMU,
HG_APB1_PT_LVD,
HG_APB1_PT_ADKEY,
} HG_Peripheral_Type;
/**
* @}
*/
enum phy_rf_mode {
INT_PHY_EXT_RF_MODE = 1, //for ext-rf case
PHY_RF_NORMAL_MODE = 2, //tx4001 ic normal case
INT_RF_EXT_PHY_MODE = 3, //for transceiver case
};
#define EFUSE_OFFSET 3
#define OSC_CLK 32000000UL
#define M2M_DMA
#define IS_DCACHE_ADDR(addr) ((uint32)(addr) >= 0x38000000 && (uint32)(addr) < 0x38f00000) //psram
#define IS_PSRAM_ADDR(addr) ((uint32)(addr) >= 0x38000000 && (uint32)(addr) < 0x38f00000) //psram
#ifdef __cplusplus
}
#endif
#endif