pure sdk for main

sdk/include/app_version.h

@@ -0,0 +1 @@
+#define APP_VERSION 0

sdk/include/basic_include.h

@@ -0,0 +1,34 @@
+#ifndef _HUGEIC_BASIC_INCLUDE_H_
+#define _HUGEIC_BASIC_INCLUDE_H_
+
+#include "typesdef.h"
+#include "list.h"
+#include "dev.h"
+#include "devid.h"
+#include "errno.h"
+
+#include "osal/atomic.h"
+#include "osal/ffs.h"
+#include "osal/irq.h"
+#include "osal/msgqueue.h"
+#include "osal/mutex.h"
+#include "osal/semaphore.h"
+#include "osal/sleep.h"
+#include "osal/string.h"
+#include "osal/task.h"
+#include "osal/timer.h"
+#include "osal/time.h"
+#include "osal/work.h"
+#include "osal/event.h"
+
+#include "hal/gpio.h"
+#include "hal/dma.h"
+#include "hal/crc.h"
+#include "hal/uart.h"
+
+#include "lib/common/common.h"
+#include "lib/common/sysevt.h"
+#include "lib/heap/sysheap.h"
+#include "lib/syscfg/syscfg.h"
+
+#endif

sdk/include/chip/soc.h

@@ -0,0 +1,9 @@
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include "tx_platform.h"
+
+#define CONFIG_KERNEL_RHINO 1
+#define SYSTEM_CLOCK DEFAULT_SYS_CLK
+
+#endif

sdk/include/chip/tx_platform.h

@@ -0,0 +1,62 @@
+#ifndef _HUGE_IC_PLATFORM_H_
+#define _HUGE_IC_PLATFORM_H_
+
+#define PRO_TYPE_LMAC 1
+#define PRO_TYPE_UMAC 2
+#define PRO_TYPE_WNB  3
+#define PRO_TYPE_UAV  4
+#define PRO_TYPE_FMAC 5
+#define PRO_TYPE_IOT  6
+#define PRO_TYPE_FPV  7
+#define PRO_TYPE_MCU  8
+
+#define PRO_TYPE_QA   66
+#define PRO_TYPE_QC   88
+
+
+#ifdef TXW4002ACK803
+#include "txw4002ack803/txw4002ack803.h"
+#include "txw4002ack803/io_function.h"
+#include "txw4002ack803/pin_names.h"
+#include "txw4002ack803/sysctrl.h"
+#include "txw4002ack803/test_atcmd.h"
+#endif
+
+#ifdef TXW80X
+#include "txw80x/txw80x.h"
+#include "txw80x/pin_names.h"
+#include "txw80x/io_function.h"
+#include "txw80x/adc_voltage_type.h"
+#include "txw80x/sysctrl.h"
+#include "txw80x/pmu.h"
+#include "txw80x/misc.h"
+#include "txw80x/boot_lib.h"
+#include "txw80x/test_atcmd.h"
+#endif
+
+
+#ifdef TXW81X
+#include "txw81x/txw81x.h"
+#include "txw81x/pin_names.h"
+#include "txw81x/io_mask.h"
+#include "txw81x/io_function.h"
+#include "txw81x/adc_voltage_type.h"
+#include "txw81x/sysctrl.h"
+#include "txw81x/pmu.h"
+#include "txw81x/misc.h"
+#include "txw81x/boot_lib.h"
+#include "txw81x/test_atcmd.h"
+#endif
+
+#ifdef TXW8000
+#include "txw8000/txw8000.h"
+#include "txw8000/pin_names.h"
+#include "txw8000/io_function.h"
+#include "txw8000/adc_voltage_type.h"
+#include "txw8000/sysctrl.h"
+#include "txw8000/pmu.h"
+#include "txw8000/misc.h"
+#include "txw8000/test_atcmd.h"
+#endif
+
+#endif

sdk/include/chip/txw81x/adc_voltage_type.h

@@ -0,0 +1,72 @@
+/**
+  ******************************************************************************
+  * @file       sdk\include\chip\txw80x\adc_voltage_type.h
+  * @author     HUGE-IC Application Team
+  * @version    V1.0.0
+  * @date       2022-03-18
+  * @brief      This file contains all the adc_voltage_type.
+  * @copyright  Copyright (c) 2016-2022 HUGE-IC
+  ******************************************************************************
+  * @attention
+  * Only used for txw80x.
+  * 
+  *
+  *
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __ADC_VOLTAGE_TYPE_H
+#define __ADC_VOLTAGE_TYPE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Docxygenid_ADC_voltage_type_enum
+  * @{
+  */
+
+/**
+  * @brief Enumeration constant for ADC voltage type.
+  * @note
+  *       Enum number start from 0x101.
+  */
+enum adc_voltage_type {
+    /*! RF temperature
+     */
+    ADC_CHANNEL_RF_TEMPERATURE = 0x101,
+    /*! Vtune电压
+     */
+    ADC_CHANNEL_VTUNE          = 0x102,
+    /*!
+     * VCO VDD电压
+     */
+    ADC_CHANNEL_VCO_VDD        = 0x103,
+    /*!
+     * VDD DIV电压
+     */
+    ADC_CHANNEL_VDD_DIV        = 0x104,
+    /*!
+     * VDDI电压
+     */
+    ADC_CHANNEL_VDDI           = 0x105,
+    /*!
+     * VDDI电压
+     */
+    ADC_CHANNEL_VDD_PFD        = 0x106,
+
+};
+
+
+/** @} Docxygenid_ADC_voltage_type_enum_enum*/
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/
+

sdk/include/chip/txw81x/boot_lib.h

@@ -0,0 +1,19 @@
+#ifndef __BOOT_LIB_H
+#define __BOOT_LIB_H
+#include "typesdef.h"
+uint32 get_boot_loader_addr();
+void save_boot_loader_addr();
+uint32 get_boot_total_size();
+uint32 get_boot_version();
+void increase_boot_version();
+void set_boot_msg(uint8 *msg);
+uint32 get_boot_svn_version();
+
+
+
+
+
+
+
+
+#endif

sdk/include/chip/txw81x/io_function.h

@@ -0,0 +1,711 @@
+/**
+  ******************************************************************************
+  * @file       sdk\include\chip\txw81x\io_function.h
+  * @author     HUGE-IC Application Team
+  * @version    V1.0.0
+  * @date       2022-01-11
+  * @brief      This file contains all the GPIO functions.
+  * @copyright  Copyright (c) 2016-2024 HUGE-IC
+  ******************************************************************************
+  * @attention
+  * Only used for txw81x.
+  * 
+  *
+  *
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __IO_FUNCTION_H
+#define __IO_FUNCTION_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "typesdef.h"
+
+/** @addtogroup Docxygenid_GPIO_enum
+  * @{
+  */
+
+/**
+  * @brief Enumeration constant for GPIO command.
+  * @note
+  *       Enum number start from 0x101.
+  */
+enum gpio_cmd {
+    /*! GPIO cmd afio set
+     */
+    GPIO_CMD_AFIO_SET = 0x101,
+
+    /*! GPIO cmd iomap output
+     */
+    GPIO_CMD_IOMAP_OUT_FUNC,
+
+    /*! GPIO cmd iomap input
+     */
+    GPIO_CMD_IOMAP_IN_FUNC,
+
+    /*! GPIO cmd iomap inout
+     */
+    GPIO_CMD_IOMAP_INOUT_FUNC,
+
+    /*! GPIO pin driver strength config
+     */
+    GPIO_CMD_DRIVER_STRENGTH,
+
+};
+
+
+/**
+  * @brief Enumeration constant for GPIO afio set.
+  */
+enum gpio_afio_set{
+    /*! gpio cmd afio 0
+     */
+    GPIO_AF_0  = 0,
+    
+    /*! gpio cmd afio 1
+     */
+    GPIO_AF_1 ,
+
+    /*! gpio cmd afio 2
+     */
+    GPIO_AF_2 ,
+
+    /*! gpio cmd afio 3
+     */
+    GPIO_AF_3 ,
+};
+
+/**
+  * @breif : Enumeration constant for GPIO pull level.
+  */
+enum gpio_pull_level {
+    /*! gpio pull level : NONE
+     */
+    GPIO_PULL_LEVEL_NONE = 0,
+    
+    /*! gpio pull level : 4.7K
+     */
+    GPIO_PULL_LEVEL_4_7K ,
+    
+    /*! gpio pull level : 100k
+     */
+    GPIO_PULL_LEVEL_100K ,
+};
+
+/**
+  * @breif : Enumeration constant for GPIO driver strength
+  */
+enum pin_driver_strength {
+    /*! Compatible version: V4
+     */
+    GPIO_DS_4MA ,
+    
+    /*! Compatible version: V4
+     */
+    GPIO_DS_12MA,
+    
+    /*! Compatible version: V4
+     */
+    GPIO_DS_20MA,
+    
+    /*! Compatible version: V4
+     */
+    GPIO_DS_28MA,
+} ;
+
+/** @defgroup Enumeration constant for GPIO IO map output function selection
+  * @{
+  */
+enum gpio_iomap_out_func{
+    GPIO_IOMAP_OUTPUT,
+
+    /**
+     * @A : iofuncmask0[14]
+     * @B : iofuncmask0[8]
+     * 
+     * @(A=0) & (B=0) : comp_dout_dig0
+     * @(A=1) & (B=0) : ospi_cs_io
+     * @(A=0) & (B=1) : dbgpath_dbgo[8]
+     */
+    GPIO_IOMAP_OUT_COMP_DOUT_DIG0_VAL,
+
+    /**
+     * @A : iofuncmask0[20]
+     * @B : iofuncmask0[9]
+     * 
+     * @(A=0) & (B=0) : comp_dout_dig1
+     * @(A=1) & (B=0) : lcd_data_o[0]
+     * @(A=0) & (B=1) : dbgpath_dbgo[9]
+     */                               
+    GPIO_IOMAP_OUT_COMP_DOUT_DIG1_VAL,
+
+    /**
+     * @A : iofuncmask0[16]
+     * @B : iofuncmask0[15]
+     * 
+     * @(A=0) & (B=0) : antenna_sel
+     * @(A=1) & (B=0) : lcd_de_or_erd
+     * @(A=0) & (B=1) : grant_ble
+     */      
+    GPIO_IOMAP_OUT_ANTENNA_SEL_VAL,
+
+    /**
+     * @A : iofuncmask0[17]
+     * @B : iofuncmask0[15]
+     * 
+     * @(A=0) & (B=0) : pa_en
+     * @(A=1) & (B=0) : lcd_hsync_or_dc
+     * @(A=0) & (B=1) : grant_ble_switch_o
+     */  
+    GPIO_IOMAP_OUT_PA_EN_VAL,
+
+    /**
+     * @A : iofuncmask0[18]
+     * @B : iofuncmask0[15]
+     * 
+     * @(A=0) & (B=0) : rf_ext_lna_en
+     * @(A=1) & (B=0) : lcd_vsync_or_cs
+     * @(A=0) & (B=1) : grant_wifi_switch_o
+     */ 
+    GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL,
+
+    /**
+     * @A : iofuncmask0[19]
+     * @B : iofuncmask0[15]
+     * 
+     * @(A=0) & (B=0) : rf_tx_en_fem
+     * @(A=1) & (B=0) : lcd_dotclk_or_rwr
+     * @(A=0) & (B=1) : rf_switch_en1
+     */ 
+    GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL,
+
+    /**
+     * @A : iofuncmask0[15]
+     * 
+     * @(A=0): rf_rx_en_fem
+     * @(A=1): rf_switch_en0
+     */ 
+    GPIO_IOMAP_OUT_RF_RX_EN_FEM_VAL,
+
+    /**
+     * @NONE
+     * 
+     */ 
+    GPIO_IOMAP_OUT_LCD_DATA_O_1,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_LCD_DATA_O_2,
+
+    /**
+     * @A : iofuncmask0[21]
+     * @B : iofuncmask0[0]
+     * @C : rtc_calib_oe
+     * 
+     * @(A=0) & (B=0) & (C=0): uart1_rts_re_o
+     * @(A=1) & (B=0) & (C=0): lcd_data_o[3]
+     * @(A=0) & (B=1) & (C=0): dbgpath_dbgo[0]
+     * @(A=0) & (B=0) & (C=1): rtc_calib
+     */ 
+    GPIO_IOMAP_OUT_UART1_RTS_RE_O_VAL,
+
+    /**
+     * @A : iofuncmask0[22]
+     * @B : iofuncmask0[1]
+     * @C : rtc_calib_oe
+     * 
+     * @(A=0) & (B=0) & (C=0): uart1_cts_de_out
+     * @(A=1) & (B=0) & (C=0): lcd_data_o[4]
+     * @(A=0) & (B=1) & (C=0): dbgpath_dbgo[1]
+     * @(A=0) & (B=0) & (C=1): rtc_calib_pul
+     */ 
+    GPIO_IOMAP_OUT_UART1_CTS_DE_OUT_VAL,
+
+    /**
+     * @A : iofuncmask0[23]
+     * 
+     * @(A=0): uart1_out
+     * @(A=1): lcd_data_o[5]
+     */
+    GPIO_IOMAP_OUT_UART1_OUT_VAL,
+
+    /**
+     * @A : iofuncmask0[2]
+     * 
+     * @(A=0): uart0_rts_re_o
+     * @(A=1): dbgpath_dbgo[2]
+     */
+    GPIO_IOMAP_OUT_UART0_RTS_RE_O,
+
+    /**
+     * @A : iofuncmask0[3]
+     * 
+     * @(A=0): uart0_cts_de_out
+     * @(A=1): dbgpath_dbgo[3]
+     */
+    GPIO_IOMAP_OUT_UART0_CTS_DE_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_UART0_TX,
+
+    /**
+     * @A : Iofuncmask0[24]
+     * 
+     * @(A=0): stmr3_pwm_out
+     * @(A=1): lcd_data_o[6]
+     */
+    GPIO_IOMAP_OUT_STMR3_PWM_OUT_VAL,
+
+    /**
+     * @A : Iofuncmask0[25]
+     * 
+     * @(A=0): stmr2_pwm_out
+     * @(A=1): lcd_data_o[7]
+     */
+    GPIO_IOMAP_OUT_STMR2_PWM_OUT_VAL,
+
+    /**
+     * @A : Iofuncmask0[26]
+     * 
+     * @(A=0): stmr1_pwm_out
+     * @(A=1): lcd_data_o[8]
+     */
+    GPIO_IOMAP_OUT_STMR1_PWM_OUT_VAL,
+
+    /**
+     * @A : Iofuncmask0[27]
+     * 
+     * @(A=0): stmr0_pwm_out
+     * @(A=1): lcd_data_o[9]
+     */
+    GPIO_IOMAP_OUT_STMR0_PWM_OUT_VAL,
+
+    /**
+     * @A : Iofuncmask0[28]
+     * 
+     * @(A=0): stmr4_pwm_out
+     * @(A=1): lcd_data_o[10]
+     */
+    GPIO_IOMAP_OUT_STMR4_PWM_OUT_VAL,
+
+    /**
+     * @A : iofuncmask1[8]
+     * @B : iofuncmask1[6]
+     * 
+     * @(A=0) & (B=0) : stmr5_pwm_out
+     * @(A=1) & (B=0) : lcd_data_o[11]
+     * @(A=0) & (B=1) : qspi_ospi_mnt_o[6]
+     */ 
+    GPIO_IOMAP_OUT_STMR5_PWM_OUT_VAL,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SDHOST_SCLK_O,
+
+    /**
+     * @A : mjpeg_dma_dbg[3]
+     * 
+     * @(A=0): tmr3_pwm_out
+     * @(A=1): mjpeg_dma_dbg[0]
+     */
+    GPIO_IOMAP_OUT_TMR3_PWM_OUT,
+
+    /**
+     * @A : usb20_phy_cfg3[22]
+     * @B : mjpeg_dma_dbg[3]
+     * 
+     * @(A=0) & (B=0) : tmr2_pwm_out
+     * @(A=1) & (B=0) : comp_dis_dbg
+     * @(A=0) & (B=1) : mjpeg_dma_dbg[1]
+     */ 
+    GPIO_IOMAP_OUT_TMR2_PWM_OUT,
+
+    /**
+     * @A : usb20_phy_cfg3[22]
+     * @B : mjpeg_dma_dbg[3]
+     * 
+     * @(A=0) & (B=0) : tmr1_pwm_out
+     * @(A=1) & (B=0) : comp_clk_dbg
+     * @(A=0) & (B=1) : mjpeg_dma_dbg[2]
+     */ 
+    GPIO_IOMAP_OUT_TMR1_PWM_OUT,
+
+    /**
+     * @A : mjpeg_dma_dbg[3]
+     * 
+     * @(A=0): tmr0_pwm_out
+     * @(A=1): lcd_data_o[12]
+     */
+    GPIO_IOMAP_OUT_TMR0_PWM_OUT,
+
+    /**
+     * @A : iofuncmask0[4]
+     * 
+     * @(A=0): led_tmr0_pwm_out
+     * @(A=1): dbgpath_dbgo[4]
+     */
+    GPIO_IOMAP_OUT_LED_TMR0_PWM_OUT,
+
+    /**
+     * @A : iofuncmask1[10]
+     * @B : iofuncmask0[5]
+     * 
+     * @(A=0) & (B=0) : led_tmr1_pwm_out
+     * @(A=1) & (B=0) : lcd_data_o[13]
+     * @(A=0) & (B=1) : dbgpath_dbgo[5]
+     */ 
+    GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT_VAL,
+
+    /**
+     * @A : iofuncmask1[11]
+     * @B : iofuncmask0[6]
+     * 
+     * @(A=0) & (B=0) : led_tmr2_pwm_out
+     * @(A=1) & (B=0) : lcd_data_o[14]
+     * @(A=0) & (B=1) : dbgpath_dbgo[6]
+     */ 
+    GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT_VAL,
+
+    /**
+     * @A : iofuncmask1[12]
+     * @B : iofuncmask0[7]
+     * 
+     * @(A=0) & (B=0) : led_tmr3_pwm_out
+     * @(A=1) & (B=0) : lcd_data_o[15]
+     * @(A=0) & (B=1) : dbgpath_dbgo[7]
+     */   
+    GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT_VAL,
+
+    /**
+     * @NONE
+     * 
+     */    
+    GPIO_IOMAP_OUT_PDM_MCLK,
+
+    /**
+     * @A : iofuncmask0[11]
+     * 
+     * @(A=0): qspi_nss1_out
+     * @(A=1): ospi_cs_io
+     */   
+    GPIO_IOMAP_OUT_QSPI_NSS1_OUT_VAL,
+
+    /**
+     * @A : iofuncmask1[0]
+     * 
+     * @(A=0): spi0_nss_out
+     * @(A=1): qspi_ospi_mnt_o[0]
+     */ 
+    GPIO_IOMAP_OUT_SPI0_NSS_OUT,
+
+    /**
+     * @A : iofuncmask1[1]
+     * 
+     * @(A=0): spi0_sck_out
+     * @(A=1): qspi_ospi_mnt_o[1]
+     */ 
+    GPIO_IOMAP_OUT_SPI0_SCK_OUT,
+
+    /**
+     * @A : iofuncmask1[2]
+     * 
+     * @(A=0): spi0_io0_out
+     * @(A=1): qspi_ospi_mnt_o[2]
+     */    
+    GPIO_IOMAP_OUT_SPI0_IO0_OUT,
+
+    /**
+     * @A : iofuncmask1[3]
+     * 
+     * @(A=0): spi0_io1_out
+     * @(A=1): qspi_ospi_mnt_o[3]
+     */    
+    GPIO_IOMAP_OUT_SPI0_IO1_OUT,
+
+    /**
+     * @A : iofuncmask1[4]
+     * 
+     * @(A=0): spi0_io2_out
+     * @(A=1): qspi_ospi_mnt_o[4]
+     */ 
+    GPIO_IOMAP_OUT_SPI0_IO2_OUT,
+
+    /**
+     * @A : iofuncmask1[5]
+     * 
+     * @(A=0): spi0_io3_out
+     * @(A=1): qspi_ospi_mnt_o[5]
+     */ 
+    GPIO_IOMAP_OUT_SPI0_IO3_OUT,
+
+    /**
+     * @NONE
+     * 
+     */      
+    GPIO_IOMAP_OUT_SPI1_NSS_OUT,
+
+    /**
+     * @NONE
+     * 
+     */  
+    GPIO_IOMAP_OUT_SPI1_SCK_OUT,
+
+    /**
+     * @NONE
+     * 
+     */  
+    GPIO_IOMAP_OUT_SPI1_IO0_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SPI1_IO1_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_LCD_DATA_O_16,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_LCD_DATA_O_17,
+
+    /**
+     * @A : iofuncmask1[13]
+     * 
+     * @(A=0): spi2_nss_out
+     * @(A=1): lcd_data_o[18]
+     */ 
+    GPIO_IOMAP_OUT_SPI2_NSS_OUT_VAL,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SPI2_SCK_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SPI2_IO0_OUT,
+
+    /**
+     * @A : iofuncmask1[14]
+     * 
+     * @(A=0): spi2_io1_out
+     * @(A=1): lcd_data_o[19]
+     */ 
+    GPIO_IOMAP_OUT_SPI2_IO1_OUT_VAL,
+
+    /**
+     * @A : iofuncmask1[15]
+     * 
+     * @(A=0): spi2_io2_out
+     * @(A=1): lcd_data_o[20]
+     */ 
+    GPIO_IOMAP_OUT_SPI2_IO2_OUT_VAL,
+
+    /**
+     * @A : iofuncmask1[16]
+     * 
+     * @(A=0): spi2_io3_out
+     * @(A=1): lcd_data_o[21]
+     */ 
+    GPIO_IOMAP_OUT_SPI2_IO3_OUT_VAL,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SDHOST_CMD_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SDHOST_DAT0_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SDHOST_DAT1_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SDHOST_DAT2_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_SDHOST_DAT3_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_IIS0_MCLK_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_IIS0_WSCLK_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_IIS0_BCLK_OUT,
+
+    /**
+     * @NONE
+     * 
+     */
+    GPIO_IOMAP_OUT_IIS0_DO,
+
+    /**
+     * @A : iofuncmask0[31]
+     * @B : iofuncmask1[17]
+     * 
+     * @(A=0) & (B=0) : iis1_mclk_out
+     * @(A=1) & (B=0) : uart5_tx
+     * @(A=0) & (B=1) : lcd_data_o[22]
+     */   
+    GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL,
+
+    /**
+     * @A : iofuncmask1[18]
+     * 
+     * @(A=0): iis1_wsclk_out
+     * @(A=1): lcd_data_o[23]
+     */ 
+    GPIO_IOMAP_OUT_IIS1_WSCLK_OUT_VAL,
+
+    /**
+     * @A : iofuncmask0[30]
+     * 
+     * @(A=0): iis1_bclk_out
+     * @(A=1): spi1_io2_out
+     */
+    GPIO_IOMAP_OUT_IIS1_BCLK_OUT_VAL,
+
+    /**
+     * @A : iofuncmask0[29]
+     * 
+     * @(A=0): iis1_do
+     * @(A=1): spi1_io3_out
+     */
+    GPIO_IOMAP_OUT_IIS1_DO_VAL,
+
+    /**
+     * @A : iofuncmask0[13]
+     * 
+     * @(A=0): clk_to_io
+     * @(A=1): uart4_tx
+     */
+    GPIO_IOMAP_OUT_CLK_TO_IO_VAL,
+};
+
+
+/** @defgroup Enumeration constant for GPIO IO map input function selection
+  * @{
+  */
+enum gpio_iomap_in_func{
+    GPIO_IOMAP_INPUT                                        = 0xF000,
+    GPIO_IOMAP_IN_TMR0_CAP_IN                               = 0x0,
+    GPIO_IOMAP_IN_TMR0_SYNC_IN__EXT_RFSWITCH_EN0_IN         ,
+    GPIO_IOMAP_IN_TMR1_CAP_IN                               ,
+    GPIO_IOMAP_IN_TMR2_CAP_IN                               ,
+    GPIO_IOMAP_IN_TMR3_CAP_IN                               ,
+    GPIO_IOMAP_IN_PDM_DATA_IN                               ,
+    GPIO_IOMAP_IN_PTA_REQ_IN                                ,
+    GPIO_IOMAP_IN_PTA_PRI_IN                                ,
+    GPIO_IOMAP_IN_FREQ_IND_IN                               ,
+    GPIO_IOMAP_IN_STMR0_CAP_IN__LCD_D3_IN_MASK1_22          ,
+    GPIO_IOMAP_IN_STMR1_CAP_IN__LCD_D4_IN_MASK1_23          ,
+    GPIO_IOMAP_IN_STMR2_CAP_IN__LCD_D5_IN_MASK1_24          ,
+    GPIO_IOMAP_IN_STMR3_CAP_IN__LCD_D6_IN_MASK1_25          ,
+    GPIO_IOMAP_IN_PORT_WKUP_IN0                             ,
+    GPIO_IOMAP_IN_PORT_WKUP_IN1__LCD_D7_IN_MASK1_26         ,
+    GPIO_IOMAP_IN_PORT_WKUP_IN2__LCD_D8_IN_MASK1_27         ,
+    GPIO_IOMAP_IN_PORT_WKUP_IN3__LCD_TE_MASK0_10            ,
+    GPIO_IOMAP_IN_UART0_IN                                  ,
+    GPIO_IOMAP_IN_UART0_CTS_DE_IN                           ,
+    GPIO_IOMAP_IN_UART1_IN__LCD_D9_IN_MASK1_28              ,
+    GPIO_IOMAP_IN_UART1_CTS_DE_IN__LCD_D10_IN_MASK1_29      ,
+    GPIO_IOMAP_IN_FB_IN__EXT_PA_EN__SYS_NMI                 ,
+    GPIO_IOMAP_IN_UART4_IN                                  ,
+    GPIO_IOMAP_IN_LCD_D0_IN_MASK1_19                        ,
+    GPIO_IOMAP_IN_SPI0_NSS_IN                               ,
+    GPIO_IOMAP_IN_SPI0_SCK_IN                               ,
+    GPIO_IOMAP_IN_SPI0_IO0_IN                               ,
+    GPIO_IOMAP_IN_SPI0_IO1_IN                               ,
+    GPIO_IOMAP_IN_SPI0_IO2_IN                               ,
+    GPIO_IOMAP_IN_SPI0_IO3_IN                               ,
+    GPIO_IOMAP_IN_SPI1_NSS_IN__LCD_D11_IN_MASK1_30          ,
+    GPIO_IOMAP_IN_SPI1_SCK_IN                               ,
+    GPIO_IOMAP_IN_SPI1_IO0_IN                               ,
+    GPIO_IOMAP_IN_SPI1_IO1_IN__LCD_D12_IN_MASK1_31          ,
+    GPIO_IOMAP_IN_LCD_D1_IN_MASK1_20                        ,
+    GPIO_IOMAP_IN_LCD_D2_IN_MASK1_21                        ,
+    GPIO_IOMAP_IN_SPI2_NSS_IN__LCD_D13_IN_MASK2_0           ,
+    GPIO_IOMAP_IN_SPI2_SCK_IN                               ,
+    GPIO_IOMAP_IN_SPI2_IO0_IN                               ,
+    GPIO_IOMAP_IN_SPI2_IO1_IN__LCD_D14_IN_MASK2_1           ,
+    GPIO_IOMAP_IN_SPI2_IO2_IN__LCD_D15_IN_MASK2_2           ,
+    GPIO_IOMAP_IN_SPI2_IO3_IN__LCD_D16_IN_MASK2_3           ,
+    GPIO_IOMAP_IN_STMR4_CAP_IN__LCD_D17_IN_MASK2_4          ,
+    GPIO_IOMAP_IN_STMR5_CAP_IN__LCD_D18_IN_MASK2_5          ,
+    GPIO_IOMAP_IN_SDHOST_CMD_IN                             ,
+    GPIO_IOMAP_IN_SDHOST_DAT0_IN                            ,
+    GPIO_IOMAP_IN_SDHOST_DAT1_IN                            ,
+    GPIO_IOMAP_IN_SDHOST_DAT2_IN                            ,
+    GPIO_IOMAP_IN_SDHOST_DAT3_IN                            ,
+    GPIO_IOMAP_IN_IIS0_MCLK_IN__LCD_D19_IN_MASK2_6          ,
+    GPIO_IOMAP_IN_IIS0_WSCLK_IN__LCD_D20_IN_MASK2_7         ,
+    GPIO_IOMAP_IN_IIS0_BCLK_IN__LCD_D21_IN_MASK2_8          ,
+    GPIO_IOMAP_IN_IIS0_DAT_IN                               ,
+    GPIO_IOMAP_IN_IIS1_MCLK_IN__UART5_IN__LCD_D22_IN_MASK2_9,
+    GPIO_IOMAP_IN_IIS1_WSCLK_IN__LCD_D23_IN_MASK2_10        ,
+    GPIO_IOMAP_IN_SPI1_IO2_IN__IIS1_BCLK_IN                 ,
+    GPIO_IOMAP_IN_SPI1_IO3_IN__IIS1_DAT_IN                  ,
+}; 
+
+
+/** @} Docxygenid_IO_function_enum*/
+
+int32 gpio_driver_strength(uint32 pin, enum pin_driver_strength strength);
+int32 gpio_set_altnt_func(uint32 pin, enum gpio_afio_set afio); 
+int32 gpio_iomap_output(uint32 pin, enum gpio_iomap_out_func func_sel);
+int32 gpio_iomap_input(uint32 pin, enum gpio_iomap_in_func func_sel);
+int32 gpio_iomap_inout(uint32 pin, enum gpio_iomap_in_func in_func_sel, enum gpio_iomap_out_func out_func_sel);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/
+

sdk/include/chip/txw81x/io_mask.h

@@ -0,0 +1,623 @@
+/**
+  ******************************************************************************
+  * @file       sdk\include\chip\txw80x\io_mask.h
+  * @author     HUGE-IC Application Team
+  * @version    V1.0.0
+  * @date       2024-01-04
+  * @brief      This file contains all the GPIO functions.
+  * @copyright  Copyright (c) 2016-2022 HUGE-IC
+  ******************************************************************************
+  * @attention
+  * Only used for txw81x.
+  * 
+  *
+  *
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __IO_MASK_H
+#define __IO_MASK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "typesdef.h"
+#include "io_function.h"
+
+
+#define IO_INDEX0(index)                  ((index&0x3)<<26)
+#define IO_INDEX0_GET(io_func)            ((io_func&IO_INDEX0(3))>>26)
+#define IO_INDEX1(index)                  ((index&0x3)<<28)
+#define IO_INDEX1_GET(io_func)            ((io_func&IO_INDEX1(3))>>28)
+#define IO_INDEX2(index)                  ((index&0x3)<<30)
+#define IO_INDEX2_GET(io_func)            ((io_func&IO_INDEX2(3))>>30)
+
+#define IO_FUNC(func)                     ((func&0xFF)<<0)
+
+#define IO_INDEX0_BIT_SITE                (8)
+#define IO_INDEX0_BIT_WIDTH               (5)
+#define IO_INDEX0_VAL_SITE                (13)
+#define IO_INDEX0_VAL_WIDTH               (1)
+#define IO_INDEX0_SET_VAL(val)            ((val&0x01)<<IO_INDEX0_VAL_SITE)
+#define IO_INDEX0_SET_BIT(bit)            ((bit&0x1F)<<IO_INDEX0_BIT_SITE)
+#define IO_INDEX0_SET(mask, val, bit)     (IO_INDEX0(mask) | IO_INDEX0_SET_VAL(val) | IO_INDEX0_SET_BIT(bit))
+#define IO_INDEX0_GET_VAL(io_func)        ((io_func & IO_INDEX0_SET_VAL(0x01)) >> IO_INDEX0_VAL_SITE)
+#define IO_INDEX0_GET_BIT(io_func)        ((io_func & IO_INDEX0_SET_BIT(0x1F)) >> IO_INDEX0_BIT_SITE)
+
+
+#define IO_INDEX1_BIT_SITE                (14)
+#define IO_INDEX1_BIT_WIDTH               (5)
+#define IO_INDEX1_VAL_SITE                (19)
+#define IO_INDEX1_VAL_WIDTH               (1)
+#define IO_INDEX1_SET_VAL(val)            ((val&0x01)<<IO_INDEX1_VAL_SITE)
+#define IO_INDEX1_SET_BIT(bit)            ((bit&0x1F)<<IO_INDEX1_BIT_SITE)
+#define IO_INDEX1_SET(mask, val, bit)     (IO_INDEX1(mask) | IO_INDEX1_SET_VAL(val) | IO_INDEX1_SET_BIT(bit))
+#define IO_INDEX1_GET_VAL(io_func)        ((io_func & IO_INDEX1_SET_VAL(0x01)) >> IO_INDEX1_VAL_SITE)
+#define IO_INDEX1_GET_BIT(io_func)        ((io_func & IO_INDEX1_SET_BIT(0x1F)) >> IO_INDEX1_BIT_SITE)
+
+
+#define IO_INDEX2_BIT_SITE                (20)
+#define IO_INDEX2_BIT_WIDTH               (5)
+#define IO_INDEX2_VAL_SITE                (25)
+#define IO_INDEX2_VAL_WIDTH               (1)
+#define IO_INDEX2_SET_VAL(val)            ((val&0x01)<<IO_INDEX2_VAL_SITE)
+#define IO_INDEX2_SET_BIT(bit)            ((bit&0x1F)<<IO_INDEX2_BIT_SITE)
+#define IO_INDEX2_SET(mask, val, bit)     (IO_INDEX2(mask) | IO_INDEX2_SET_VAL(val) | IO_INDEX2_SET_BIT(bit))
+#define IO_INDEX2_GET_VAL(io_func)        ((io_func & IO_INDEX2_SET_VAL(0x01)) >> IO_INDEX2_VAL_SITE)
+#define IO_INDEX2_GET_BIT(io_func)        ((io_func & IO_INDEX2_SET_BIT(0x1F)) >> IO_INDEX2_BIT_SITE)
+
+
+#define IO_MASK(set, func)                ((set) | (func))
+
+/**
+ * @A : iofuncmask0[14]
+ * @B : iofuncmask0[8]
+ * 
+ * @(A=0) & (B=0) : comp_dout_dig0
+ * @(A=1) & (B=0) : ospi_cs_io
+ * @(A=0) & (B=1) : dbgpath_dbgo[8]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_COMP_DOUT_DIG0 {
+    GPIO_IOMAP_OUT_COMP_DOUT_DIG0         = IO_MASK(IO_INDEX0_SET(0, 0, 14) |\
+                                                    IO_INDEX1_SET(0, 0,  8) |\
+                                                    IO_INDEX2_SET(0, 0,  8) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG0_VAL)),
+    GPIO_IOMAP_OUT_OSPI_CS_IO             = IO_MASK(IO_INDEX0_SET(0, 1, 14) |\
+                                                    IO_INDEX1_SET(0, 0,  8) |\
+                                                    IO_INDEX2_SET(0, 0,  8) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG0_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[20]
+ * @B : iofuncmask0[9]
+ * 
+ * @(A=0) & (B=0) : comp_dout_dig1
+ * @(A=1) & (B=0) : lcd_data_o[0]
+ * @(A=0) & (B=1) : dbgpath_dbgo[9]
+ */  
+enum IOMASK_GPIO_IOMAP_OUT_COMP_DOUT_DIG1 {
+    GPIO_IOMAP_OUT_COMP_DOUT_DIG1         = IO_MASK(IO_INDEX0_SET(0, 0, 20) |\
+                                                    IO_INDEX1_SET(0, 0,  9) |\
+                                                    IO_INDEX2_SET(0, 0,  9) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG1_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_0           = IO_MASK(IO_INDEX0_SET(0, 1, 20) |\
+                                                    IO_INDEX1_SET(0, 0,  9) |\
+                                                    IO_INDEX2_SET(0, 0,  9) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_COMP_DOUT_DIG1_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[16]
+ * @B : iofuncmask0[15]
+ * 
+ * @(A=0) & (B=0) : antenna_sel
+ * @(A=1) & (B=0) : lcd_de_or_erd
+ * @(A=0) & (B=1) : grant_ble
+ */   
+enum IOMASK_GPIO_IOMAP_OUT_ANTENNA_SEL {
+    GPIO_IOMAP_OUT_ANTENNA_SEL            = IO_MASK(IO_INDEX0_SET(0, 0, 16) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_ANTENNA_SEL_VAL)),
+    GPIO_IOMAP_OUT_LCD_DE_OR_ERD          = IO_MASK(IO_INDEX0_SET(0, 1, 16) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_ANTENNA_SEL_VAL)),
+    GPIO_IOMAP_OUT_GRANT_BLE              = IO_MASK(IO_INDEX0_SET(0, 0, 16) |\
+                                                    IO_INDEX1_SET(0, 1, 15) |\
+                                                    IO_INDEX2_SET(0, 1, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_ANTENNA_SEL_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[17]
+ * @B : iofuncmask0[15]
+ * 
+ * @(A=0) & (B=0) : pa_en
+ * @(A=1) & (B=0) : lcd_hsync_or_dc
+ * @(A=0) & (B=1) : grant_ble_switch_o
+ */  
+enum IOMASK_GPIO_IOMAP_OUT_PA_EN {
+    GPIO_IOMAP_OUT_PA_EN                  = IO_MASK(IO_INDEX0_SET(0, 0, 17) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_PA_EN_VAL)),
+    GPIO_IOMAP_OUT_LCD_HSYNC_OR_DC        = IO_MASK(IO_INDEX0_SET(0, 1, 17) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_PA_EN_VAL)),
+    GPIO_IOMAP_OUT_GRANT_BLE_SWITCH_O     = IO_MASK(IO_INDEX0_SET(0, 0, 17) |\
+                                                    IO_INDEX1_SET(0, 1, 15) |\
+                                                    IO_INDEX2_SET(0, 1, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_PA_EN_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[18]
+ * @B : iofuncmask0[15]
+ * 
+ * @(A=0) & (B=0) : rf_ext_lna_en
+ * @(A=1) & (B=0) : lcd_vsync_or_cs
+ * @(A=0) & (B=1) : grant_wifi_switch_o
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_RF_EXT_LNA_EN {
+    GPIO_IOMAP_OUT_RF_EXT_LNA_EN          = IO_MASK(IO_INDEX0_SET(0, 0, 18) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL)),
+    GPIO_IOMAP_OUT_LCD_VSYNC_OR_CS        = IO_MASK(IO_INDEX0_SET(0, 1, 18) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL)),
+    GPIO_IOMAP_OUT_GRANT_WIFI_SWITCH_O    = IO_MASK(IO_INDEX0_SET(0, 0, 18) |\
+                                                    IO_INDEX1_SET(0, 1, 15) |\
+                                                    IO_INDEX2_SET(0, 1, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_EXT_LNA_EN_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[19]
+ * @B : iofuncmask0[15]
+ * 
+ * @(A=0) & (B=0) : rf_tx_en_fem
+ * @(A=1) & (B=0) : lcd_dotclk_or_rwr
+ * @(A=0) & (B=1) : rf_switch_en1
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_RF_TX_EN_FEM {
+    GPIO_IOMAP_OUT_RF_TX_EN_FEM           = IO_MASK(IO_INDEX0_SET(0, 0, 19) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL)),
+    GPIO_IOMAP_OUT_LCD_DOTCLK_OR_RWR      = IO_MASK(IO_INDEX0_SET(0, 1, 19) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL)),
+    GPIO_IOMAP_OUT_RF_SWITCH_EN1          = IO_MASK(IO_INDEX0_SET(0, 0, 19) |\
+                                                    IO_INDEX1_SET(0, 1, 15) |\
+                                                    IO_INDEX2_SET(0, 1, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_TX_EN_FEM_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[15]
+ * 
+ * @(A=0): rf_rx_en_fem
+ * @(A=1): rf_switch_en0
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_RF_RX_EN_FEM {
+    GPIO_IOMAP_OUT_RF_RX_EN_FEM           = IO_MASK(IO_INDEX0_SET(0, 0, 15) |\
+                                                    IO_INDEX1_SET(0, 0, 15) |\
+                                                    IO_INDEX2_SET(0, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_RX_EN_FEM_VAL)),
+    GPIO_IOMAP_OUT_RF_SWITCH_EN0          = IO_MASK(IO_INDEX0_SET(0, 1, 15) |\
+                                                    IO_INDEX1_SET(0, 1, 15) |\
+                                                    IO_INDEX2_SET(0, 1, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_RF_RX_EN_FEM_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[21]
+ * @B : iofuncmask0[0]
+ * @C : rtc_calib_oe
+ * 
+ * @(A=0) & (B=0) & (C=0): uart1_rts_re_o
+ * @(A=1) & (B=0) & (C=0): lcd_data_o[3]
+ * @(A=0) & (B=1) & (C=0): dbgpath_dbgo[0]
+ * @(A=0) & (B=0) & (C=1): rtc_calib
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_UART1_RTS_RE_O {
+    GPIO_IOMAP_OUT_UART1_RTS_RE_O         = IO_MASK(IO_INDEX0_SET(0, 0, 21) |\
+                                                    IO_INDEX1_SET(0, 0,  0) |\
+                                                    IO_INDEX2_SET(0, 0,  0) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_UART1_RTS_RE_O_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_3           = IO_MASK(IO_INDEX0_SET(0, 1, 21) |\
+                                                    IO_INDEX1_SET(0, 0,  0) |\
+                                                    IO_INDEX2_SET(0, 0,  0) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_UART1_RTS_RE_O_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[22]
+ * @B : iofuncmask0[1]
+ * @C : rtc_calib_oe
+ * 
+ * @(A=0) & (B=0) & (C=0): uart1_cts_de_out
+ * @(A=1) & (B=0) & (C=0): lcd_data_o[4]
+ * @(A=0) & (B=1) & (C=0): dbgpath_dbgo[1]
+ * @(A=0) & (B=0) & (C=1): rtc_calib_pul
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_UART1_CTS_DE_OUT {
+    GPIO_IOMAP_OUT_UART1_CTS_DE_OUT       = IO_MASK(IO_INDEX0_SET(0, 0, 22) |\
+                                                    IO_INDEX1_SET(0, 0,  1) |\
+                                                    IO_INDEX2_SET(0, 0,  1) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_UART1_CTS_DE_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_4           = IO_MASK(IO_INDEX0_SET(0, 1, 22) |\
+                                                    IO_INDEX1_SET(0, 0,  1) |\
+                                                    IO_INDEX2_SET(0, 0,  1) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_UART1_CTS_DE_OUT_VAL)),
+};
+
+/**
+ * @A : iofuncmask0[23]
+ * 
+ * @(A=0): uart1_out
+ * @(A=1): lcd_data_o[5]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_UART1_OUT {
+    GPIO_IOMAP_OUT_UART1_OUT              = IO_MASK(IO_INDEX0_SET(0, 0, 23) |\
+                                                    IO_INDEX1_SET(0, 0, 23) |\
+                                                    IO_INDEX2_SET(0, 0, 23) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_UART1_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_5           = IO_MASK(IO_INDEX0_SET(0, 1, 23) |\
+                                                    IO_INDEX1_SET(0, 1, 23) |\
+                                                    IO_INDEX2_SET(0, 1, 23) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_UART1_OUT_VAL)),
+};
+
+/**
+ * @A : Iofuncmask0[24]
+ * 
+ * @(A=0): stmr3_pwm_out
+ * @(A=1): lcd_data_o[6]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_STMR3_PWM_OUT {
+    GPIO_IOMAP_OUT_STMR3_PWM_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 24) |\
+                                                    IO_INDEX1_SET(0, 0, 24) |\
+                                                    IO_INDEX2_SET(0, 0, 24) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR3_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_6           = IO_MASK(IO_INDEX0_SET(0, 1, 24) |\
+                                                    IO_INDEX1_SET(0, 1, 24) |\
+                                                    IO_INDEX2_SET(0, 1, 24) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR3_PWM_OUT_VAL)),
+};
+
+/**
+ * @A : Iofuncmask0[25]
+ * 
+ * @(A=0): stmr2_pwm_out
+ * @(A=1): lcd_data_o[7]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_STMR2_PWM_OUT {
+    GPIO_IOMAP_OUT_STMR2_PWM_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 25) |\
+                                                    IO_INDEX1_SET(0, 0, 25) |\
+                                                    IO_INDEX2_SET(0, 0, 25) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR2_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_7           = IO_MASK(IO_INDEX0_SET(0, 1, 25) |\
+                                                    IO_INDEX1_SET(0, 1, 25) |\
+                                                    IO_INDEX2_SET(0, 1, 25) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR2_PWM_OUT_VAL)),
+};
+
+/**
+ * @A : Iofuncmask0[26]
+ * 
+ * @(A=0): stmr1_pwm_out
+ * @(A=1): lcd_data_o[8]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_STMR1_PWM_OUT {
+    GPIO_IOMAP_OUT_STMR1_PWM_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 26) |\
+                                                    IO_INDEX1_SET(0, 0, 26) |\
+                                                    IO_INDEX2_SET(0, 0, 26) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR1_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_8           = IO_MASK(IO_INDEX0_SET(0, 1, 26) |\
+                                                    IO_INDEX1_SET(0, 1, 26) |\
+                                                    IO_INDEX2_SET(0, 1, 26) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR1_PWM_OUT_VAL)),
+};
+
+/**
+ * @A : Iofuncmask0[27]
+ * 
+ * @(A=0): stmr0_pwm_out
+ * @(A=1): lcd_data_o[9]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_STMR0_PWM_OUT {
+    GPIO_IOMAP_OUT_STMR0_PWM_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 27) |\
+                                                    IO_INDEX1_SET(0, 0, 27) |\
+                                                    IO_INDEX2_SET(0, 0, 27) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR0_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_9           = IO_MASK(IO_INDEX0_SET(0, 1, 27) |\
+                                                    IO_INDEX1_SET(0, 1, 27) |\
+                                                    IO_INDEX2_SET(0, 1, 27) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR0_PWM_OUT_VAL)),
+};
+
+/**
+ * @A : Iofuncmask0[28]
+ * 
+ * @(A=0): stmr4_pwm_out
+ * @(A=1): lcd_data_o[10]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_STMR4_PWM_OUT {
+    GPIO_IOMAP_OUT_STMR4_PWM_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 28) |\
+                                                    IO_INDEX1_SET(0, 0, 28) |\
+                                                    IO_INDEX2_SET(0, 0, 28) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR4_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_10          = IO_MASK(IO_INDEX0_SET(0, 1, 28) |\
+                                                    IO_INDEX1_SET(0, 1, 28) |\
+                                                    IO_INDEX2_SET(0, 1, 28) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR4_PWM_OUT_VAL)),
+};
+
+/**
+ * @A : iofuncmask1[8]
+ * @B : iofuncmask1[6]
+ * 
+ * @(A=0) & (B=0) : stmr5_pwm_out
+ * @(A=1) & (B=0) : lcd_data_o[11]
+ * @(A=0) & (B=1) : qspi_ospi_mnt_o[6]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_STMR5_PWM_OUT {
+    GPIO_IOMAP_OUT_STMR5_PWM_OUT          = IO_MASK(IO_INDEX0_SET(1, 0,  8) |\
+                                                    IO_INDEX1_SET(1, 0,  6) |\
+                                                    IO_INDEX2_SET(1, 0,  6) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR5_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_11          = IO_MASK(IO_INDEX0_SET(1, 1,  8) |\
+                                                    IO_INDEX1_SET(1, 0,  6) |\
+                                                    IO_INDEX2_SET(1, 0,  6) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_STMR5_PWM_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask1[10]
+ * @B : iofuncmask0[5]
+ * 
+ * @(A=0) & (B=0) : led_tmr1_pwm_out
+ * @(A=1) & (B=0) : lcd_data_o[13]
+ * @(A=0) & (B=1) : dbgpath_dbgo[5]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT {
+    GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT       = IO_MASK(IO_INDEX0_SET(1, 0, 10) |\
+                                                    IO_INDEX1_SET(0, 0,  5) |\
+                                                    IO_INDEX2_SET(0, 0,  5) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_13          = IO_MASK(IO_INDEX0_SET(1, 1, 10) |\
+                                                    IO_INDEX1_SET(0, 0,  5) |\
+                                                    IO_INDEX2_SET(0, 0,  5) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_LED_TMR1_PWM_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask1[11]
+ * @B : iofuncmask0[6]
+ * 
+ * @(A=0) & (B=0) : led_tmr2_pwm_out
+ * @(A=1) & (B=0) : lcd_data_o[14]
+ * @(A=0) & (B=1) : dbgpath_dbgo[6]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT {
+    GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT       = IO_MASK(IO_INDEX0_SET(1, 0, 11) |\
+                                                    IO_INDEX1_SET(0, 0,  6) |\
+                                                    IO_INDEX2_SET(0, 0,  6) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_14          = IO_MASK(IO_INDEX0_SET(1, 1, 11) |\
+                                                    IO_INDEX1_SET(0, 0,  6) |\
+                                                    IO_INDEX2_SET(0, 0,  6) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_LED_TMR2_PWM_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask1[12]
+ * @B : iofuncmask0[7]
+ * 
+ * @(A=0) & (B=0) : led_tmr3_pwm_out
+ * @(A=1) & (B=0) : lcd_data_o[15]
+ * @(A=0) & (B=1) : dbgpath_dbgo[7]
+ */
+enum IOMASK_GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT {
+    GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT       = IO_MASK(IO_INDEX0_SET(1, 0, 12) |\
+                                                    IO_INDEX1_SET(0, 0,  7) |\
+                                                    IO_INDEX2_SET(0, 0,  7) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_15          = IO_MASK(IO_INDEX0_SET(1, 1, 12) |\
+                                                    IO_INDEX1_SET(0, 0,  7) |\
+                                                    IO_INDEX2_SET(0, 0,  7) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_LED_TMR3_PWM_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask0[11]
+ * 
+ * @(A=0): qspi_nss1_out
+ * @(A=1): ospi_cs_io
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_QSPI_NSS1_OUT {
+    GPIO_IOMAP_OUT_QSPI_NSS1_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 11) |\
+                                                    IO_INDEX1_SET(0, 0, 11) |\
+                                                    IO_INDEX2_SET(0, 0, 11) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_QSPI_NSS1_OUT_VAL)),
+    GPIO_IOMAP_OUT_OSPI_CS_IO_            = IO_MASK(IO_INDEX0_SET(0, 1, 11) |\
+                                                    IO_INDEX1_SET(0, 1, 11) |\
+                                                    IO_INDEX2_SET(0, 1, 11) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_QSPI_NSS1_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask1[13]
+ * 
+ * @(A=0): spi2_nss_out
+ * @(A=1): lcd_data_o[18]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_SPI2_NSS_OUT {
+    GPIO_IOMAP_OUT_SPI2_NSS_OUT           = IO_MASK(IO_INDEX0_SET(1, 0, 13) |\
+                                                    IO_INDEX1_SET(1, 0, 13) |\
+                                                    IO_INDEX2_SET(1, 0, 13) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_NSS_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_18          = IO_MASK(IO_INDEX0_SET(1, 1, 13) |\
+                                                    IO_INDEX1_SET(1, 1, 13) |\
+                                                    IO_INDEX2_SET(1, 1, 13) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_NSS_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask1[14]
+ * 
+ * @(A=0): spi2_io1_out
+ * @(A=1): lcd_data_o[19]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_SPI2_IO1_OUT {
+    GPIO_IOMAP_OUT_SPI2_IO1_OUT           = IO_MASK(IO_INDEX0_SET(1, 0, 14) |\
+                                                    IO_INDEX1_SET(1, 0, 14) |\
+                                                    IO_INDEX2_SET(1, 0, 14) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO1_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_19          = IO_MASK(IO_INDEX0_SET(1, 1, 14) |\
+                                                    IO_INDEX1_SET(1, 1, 14) |\
+                                                    IO_INDEX2_SET(1, 1, 14) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO1_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask1[15]
+ * 
+ * @(A=0): spi2_io2_out
+ * @(A=1): lcd_data_o[20]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_SPI2_IO2_OUT {
+    GPIO_IOMAP_OUT_SPI2_IO2_OUT           = IO_MASK(IO_INDEX0_SET(1, 0, 15) |\
+                                                    IO_INDEX1_SET(1, 0, 15) |\
+                                                    IO_INDEX2_SET(1, 0, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO2_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_20          = IO_MASK(IO_INDEX0_SET(1, 1, 15) |\
+                                                    IO_INDEX1_SET(1, 1, 15) |\
+                                                    IO_INDEX2_SET(1, 1, 15) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO2_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask1[16]
+ * 
+ * @(A=0): spi2_io3_out
+ * @(A=1): lcd_data_o[21]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_SPI2_IO3_OUT {
+    GPIO_IOMAP_OUT_SPI2_IO3_OUT           = IO_MASK(IO_INDEX0_SET(1, 0, 16) |\
+                                                    IO_INDEX1_SET(1, 0, 16) |\
+                                                    IO_INDEX2_SET(1, 0, 16) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO3_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_21          = IO_MASK(IO_INDEX0_SET(1, 1, 16) |\
+                                                    IO_INDEX1_SET(1, 1, 16) |\
+                                                    IO_INDEX2_SET(1, 1, 16) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_SPI2_IO3_OUT_VAL)),                                         
+};
+
+/**
+ * @A : iofuncmask0[31]
+ * @B : iofuncmask1[17]
+ * 
+ * @(A=0) & (B=0) : iis1_mclk_out
+ * @(A=1) & (B=0) : uart5_tx
+ * @(A=0) & (B=1) : lcd_data_o[22]
+ */   
+enum IOMASK_GPIO_IOMAP_OUT_IIS1_MCLK_OUT {
+    GPIO_IOMAP_OUT_IIS1_MCLK_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 31) |\
+                                                    IO_INDEX1_SET(1, 0, 17) |\
+                                                    IO_INDEX2_SET(1, 0, 17) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL)),
+    GPIO_IOMAP_OUT_UART5_TX               = IO_MASK(IO_INDEX0_SET(0, 1, 31) |\
+                                                    IO_INDEX1_SET(1, 0, 17) |\
+                                                    IO_INDEX2_SET(1, 0, 17) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_22          = IO_MASK(IO_INDEX0_SET(0, 0, 31) |\
+                                                    IO_INDEX1_SET(1, 1, 17) |\
+                                                    IO_INDEX2_SET(1, 1, 17) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_MCLK_OUT_VAL)),                                                                                             
+};
+
+/**
+ * @A : iofuncmask1[18]
+ * 
+ * @(A=0): iis1_wsclk_out
+ * @(A=1): lcd_data_o[23]
+ */ 
+enum IOMASK_GPIO_IOMAP_OUT_IIS1_WSCLK_OUT {
+    GPIO_IOMAP_OUT_IIS1_WSCLK_OUT         = IO_MASK(IO_INDEX0_SET(1, 0, 18) |\
+                                                    IO_INDEX1_SET(1, 0, 18) |\
+                                                    IO_INDEX2_SET(1, 0, 18) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_WSCLK_OUT_VAL)),
+    GPIO_IOMAP_OUT_LCD_DATA_O_23          = IO_MASK(IO_INDEX0_SET(1, 1, 18) |\
+                                                    IO_INDEX1_SET(1, 1, 18) |\
+                                                    IO_INDEX2_SET(1, 1, 18) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_WSCLK_OUT_VAL)),                                                                                             
+};
+
+/**
+ * @A : iofuncmask0[30]
+ * 
+ * @(A=0): iis1_bclk_out
+ * @(A=1): spi1_io2_out
+ */
+enum IOMASK_GPIO_IOMAP_OUT_IIS1_BCLK_OUT {
+    GPIO_IOMAP_OUT_IIS1_BCLK_OUT          = IO_MASK(IO_INDEX0_SET(0, 0, 30) |\
+                                                    IO_INDEX1_SET(0, 0, 30) |\
+                                                    IO_INDEX2_SET(0, 0, 30) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_BCLK_OUT_VAL)),
+    GPIO_IOMAP_OUT_SPI1_IO2_OUT           = IO_MASK(IO_INDEX0_SET(0, 1, 30) |\
+                                                    IO_INDEX1_SET(0, 1, 30) |\
+                                                    IO_INDEX2_SET(0, 1, 30) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_BCLK_OUT_VAL)),                                                                                             
+};
+
+/**
+ * @A : iofuncmask0[29]
+ * 
+ * @(A=0): iis1_do
+ * @(A=1): spi1_io3_out
+ */
+enum IOMASK_GPIO_IOMAP_OUT_IIS1_DO {
+    GPIO_IOMAP_OUT_IIS1_DO                = IO_MASK(IO_INDEX0_SET(0, 0, 29) |\
+                                                    IO_INDEX1_SET(0, 0, 29) |\
+                                                    IO_INDEX2_SET(0, 0, 29) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_DO_VAL)),
+    GPIO_IOMAP_OUT_SPI1_IO3_OUT           = IO_MASK(IO_INDEX0_SET(0, 1, 29) |\
+                                                    IO_INDEX1_SET(0, 1, 29) |\
+                                                    IO_INDEX2_SET(0, 1, 29) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_IIS1_DO_VAL)),                                                                                             
+};
+
+/**
+ * @A : iofuncmask0[13]
+ * 
+ * @(A=0): clk_to_io
+ * @(A=1): uart4_tx
+ */
+enum IOMASK_GPIO_IOMAP_OUT_CLK_TO_IO {
+    GPIO_IOMAP_OUT_CLK_TO_IO              = IO_MASK(IO_INDEX0_SET(0, 0, 13) |\
+                                                    IO_INDEX1_SET(0, 0, 13) |\
+                                                    IO_INDEX2_SET(0, 0, 13) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_CLK_TO_IO_VAL)),
+    GPIO_IOMAP_OUT_UART4_TX               = IO_MASK(IO_INDEX0_SET(0, 1, 13) |\
+                                                    IO_INDEX1_SET(0, 1, 13) |\
+                                                    IO_INDEX2_SET(0, 1, 13) ,
+                                                    IO_FUNC(GPIO_IOMAP_OUT_CLK_TO_IO_VAL)),                                                                                             
+};
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+/*************************** (C) COPYRIGHT 2016-2022 HUGE-IC ***** END OF FILE *****/

sdk/include/chip/txw81x/misc.h

@@ -0,0 +1,356 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  HUGE-IC Application Team
+  * @version V1.0.0
+  * @date    2021.01.14
+  * @brief   This file contains all the PowerDomain firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
+  *
+  *
+  * Revision History
+  * V1.0.0  2021.01.14  First Release, move from sysctrl
+  *
+  ******************************************************************************
+  */
+
+#ifndef __MISC_H__
+#define __MISC_H__
+
+#include "typesdef.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+
+#ifdef VENUS_END
+/*******************************************************************/
+/*    Venus to be continue */
+/*******************************************************************/
+#endif
+
+
+/**
+  * @}
+  */
+
+///** @defgroup SYSMONITOR MACRO-DEF & Exported_Functions
+//  * @{
+//  */
+typedef struct
+{
+    __IO uint32 CHx_LMT_L;
+    __IO uint32 CHx_LMT_H;
+    __IO uint32 CHx_ERR_ADR;
+//         uint32 RESERVEDx;
+} SYS_MNT_CH_TypeDef;
+
+typedef struct
+{
+    __IO uint32 CTRL;
+    __IO uint32 PND;
+    __IO uint32 CLR;
+    __IO uint32 RD;
+    __IO uint32 WR;
+    __IO uint32 CPU_PC0;
+    __IO uint32 CPU_PC1;
+    __IO uint32 CPU_PC2;
+    __IO uint32 CPU_PC3;    
+    SYS_MNT_CH_TypeDef SYS_MNT_CH;
+} SYS_MNT_TypeDef;
+
+#define SYSMNT                  ((SYS_MNT_TypeDef    *) SYS_MNT_BASE)
+
+/** @addtogroup Template_Project
+  * @{
+  */
+#define LL_SYSMONITOR_CHN_EN(n)                 (BIT(n))
+#define LL_SYSMONITOR_CHN_CAP_RANGE_INTER(n)    (BIT(n+4))
+#define LL_SYSMONITOR_CHN_CAP_RANGE_OUTER(n)    (0)
+#define LL_SYSMONITOR_CAP_PC_EN                 (1UL << 6)
+#define LL_SYSMONITOR_INT_EN                    (1UL << 7)
+#define LL_SYSMONITOR_CH0_SEL(n)                (((n) & 0x1F) << 8)
+#define LL_SYSMONITOR_CH0_SEL_MSK               ((0x1F) << 8)
+#define LL_SYSMONITOR_CH0_CAP_READ              ((1UL) << 18)
+#define LL_SYSMONITOR_CH0_CAP_WRITE             ((1UL) << 19)
+#define LL_SYSMONITOR_CH0_CAP_MODE(n)           ((((n) & 0x3)) << 18)
+
+#define LL_SYSMONITOR_CLEAR_REGISTER()   do { SYSMNT->CLR = 1; } while(0)
+
+/** @addtogroup XXX
+  * @{
+  */ 
+typedef enum {
+    LL_SYSMONITOR_CHN_LMAC_WAVE_TX          = (0),
+    LL_SYSMONITOR_CHN_LMAC_WAVE_RX          = (1),
+    LL_SYSMONITOR_CHN_LMAC_TX               = (2),
+    LL_SYSMONITOR_CHN_LMAC_RX               = (3),
+    LL_SYSMONITOR_CHN_SDIO                  = (4),
+    LL_SYSMONITOR_CHN_USB20                 = (5),
+    LL_SYSMONITOR_CHN_USB11                 = (6),
+    LL_SYSMONITOR_CHN_GMAC_RX               = (7),
+    LL_SYSMONITOR_CHN_GMAC_TX               = (8),
+    LL_SYSMONITOR_CHN_CPU_I_CODE_BUS        = (9),
+    LL_SYSMONITOR_CHN_CPU_D_CODE_BUS        = (10),
+    LL_SYSMONITOR_CHN_CPU_SYSBUS_BUS        = (11),
+} TYPE_ENUM_LL_SYSMONITOR_CH;
+
+/** @addtogroup XXX
+  * @{
+  */ 
+typedef enum {
+    LL_SYSMONITOR_CAP_RANGE_INTER           = (0),
+    LL_SYSMONITOR_CAP_RANGE_OUTER           = (1),
+} TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE;
+
+/** @addtogroup XXX
+  * @{
+  */ 
+typedef enum {
+    LL_SYSMONITOR_CAP_MODE_READ             = (1),
+    LL_SYSMONITOR_CAP_MODE_WRITE            = (2),
+    LL_SYSMONITOR_CAP_MODE_READ_OR_WRITE    = (3),
+} TYPE_ENUM_LL_SYSMONITOR_CAP_MODE;
+
+typedef struct __ll_sysmonitor_cfg {
+    /*! System monitor interrupt enable
+     */
+    bool                                int_en;
+    /*! System monitor sub channel :  [0, 20]
+     */
+    TYPE_ENUM_LL_SYSMONITOR_CH          sub_chn;
+    /*! capture mode
+    */
+    TYPE_ENUM_LL_SYSMONITOR_CAP_MODE    cap_mode;
+    /*! capture range
+    */
+    TYPE_ENUM_LL_SYSMONITOR_CAP_RANGE   cap_range;
+    /*! Chx low limited address 
+     */
+    uint32                                 chx_limit_low;
+    /*! Chx high limited address
+     */
+    uint32                                 chx_limit_high;
+} TYPE_SYSMONITOR_CFG;
+
+void sys_monitor_config(TYPE_SYSMONITOR_CFG *p_cfg);
+void sys_monitor_reset(void);
+
+/**
+  * @}
+  */
+
+/** @defgroup EFUSE MACRO-DEF & Exported_Functions
+  * @{
+  */
+
+typedef struct
+{
+    __IO uint32 EFUSE_CON;
+    __IO uint32 EFUSE_TIME_CON0;
+    __IO uint32 EFUSE_TIME_CON1;
+    __IO uint32 EFUSE_TIME_CON2;
+    __IO uint32 EFUSE_STATUS;
+    __IO uint32 EFUSE_ADDR_CNT;
+    __IO uint32 EFUSE_DATA;
+} EFUSE_TypeDef;
+
+#define EFUSE                   ((EFUSE_TypeDef *) EFUSE_BASE)
+/* efuse timing define */
+#define LL_EFUSE_POWER_FREQ                 100000          /* 10us */
+#define LL_EFUSE_PROGRAM_FREQ               100000          /* 10us (9~11uS) */
+#define LL_EFUSE_READ_FREQ                  10000000       /* 100ns ( > 36ns)  */
+
+uint16 sysctrl_efuse_config_and_read(uint32 addr, uint8 *p_buf, uint16 len);
+void rf_para_efuse_check_valid(void);
+void sysctrl_efuse_mac_addr_calc(uint8 *addr_buf);
+void sysctrl_efuse_mac_addr_calc_uuid(uint8 *addr_buf);
+uint16 sysctrl_efuse_get_customer_id(void);
+uint32 sysctrl_efuse_get_smt_dat(void);
+int32 tsensor_meas(uint8 sensor_idx);
+
+/*******************************************************************/
+/*             RFADC                                               */
+/*******************************************************************/
+typedef struct {
+    __IO uint32 RFADCDIGCON;
+} RFADCDIG_TypeDef;
+    
+#define RFADCDIG                ((RFADCDIG_TypeDef *) RFADCDIG_BASE)
+    
+#define RFADCDIGCON_ACS_ON_MSK                   BIT(0)
+#define RFADCDIGCON_ACS_RW_MSK                   BIT(1)
+#define RFADCDIGCON_ACS_ADDR_SHIFT               2
+#define RFADCDIGCON_ACS_ADDR_MSK                (0x1f<<RFADCDIGCON_ACS_ADDR_SHIFT)
+#define RFADCDIGCON_ACS_DATA_SHIFT               7
+#define RFADCDIGCON_ACS_DATA_MSK                (0x3fffff<<RFADCDIGCON_ACS_DATA_SHIFT)
+    
+#define ADCOUTSEL                               0 // 0: output data after calibration; 1: output data before calibration
+
+/*******************************************************************/
+/*             RFADC                                               */
+/*******************************************************************/
+
+enum lf_clk_src {
+    FROM_HOSC  = 0,
+    FROM_RC32K = 2,
+    FROM_PB0   = 3,
+};
+
+enum lf_clk_count {
+    _1024_CYCLE = 0,
+    _512_CYCLE  = 1,
+    _256_CYCLE  = 2,
+    _128_CYCLE  = 3,
+    _64_CYCLE   = 4,
+    _32_CYCLE   = 5,
+    _16_CYCLE   = 6,
+    _8_CYCLE    = 7,
+};
+
+enum dac_default_state {
+    POWER_OFF = 0,
+    SLEEP     = 1,
+    STAND_BY  = 2,
+    POWER_ON  = 3
+};
+
+enum rf_bw {
+    BW_1M = 0,
+    BW_2M = 1,
+    BW_4M = 2,
+    BW_8M = 3
+};
+
+enum rf_parameter_type {
+	RF_EFUSE_ALL_SIM = 0,
+    ADC_CALIB_VAL    = 1,
+	ADDA_TIM_OFFSET  = 2,
+    TXDCOC_CALIB_VAL = 3,
+    TXIMB_CALIB_VAL  = 4,
+    RXDCOC_CALIB_VAL = 5,
+    RXIMB_CALIB_VAL  = 6
+};
+
+int32 tx_digi_gain_store(uint16 tx_digi_gain);
+int32 sysctrl_internal_rf_sel_lo_freq(uint8 lo_freq_idx);
+int32 is_xo_cs_calibed(void);
+int32 is_xo_cto_calibed(void);
+int32 xo_cs_store(uint8 xo_cs_val);
+int32 sysctrl_get_xo_drcs(void);
+int32 sysctrl_set_xo_drcs(uint16 xo_drcs);
+void adc_cfg_reg_wr(uint8 addr, uint32 data);
+uint32 adc_cfg_reg_rd(uint8 addr);
+int32 is_adc_calibed(void);
+void adc_init(void);
+int32 adc_calib_res_store(void);
+void adc_calib_res_restore(void);
+void rfadc_calib_mode_soft_test(void);
+
+int32 sysctrl_err_resp_icode_bus(uint8 enable);
+int32 sysctrl_err_resp_dcode_bus(uint8 enable);
+int32 sysctrl_err_resp_ahb2dma_bus(uint8 enable);
+int32 sysctrl_err_resp_sdiodevice_bus(uint8 enable);
+int32 sysctrl_err_resp_disable(void);
+
+int32 sysctrl_get_chip_flash_size(void);
+
+
+#ifdef PSRAM_HEAP
+/** use when DMA source is psram 
+ *  1、usage( this -> DMA kick) 
+ */
+__STATIC_INLINE void sys_dcache_clean_range (uint32_t *addr, int32_t dsize)
+{
+    if (((uint32)addr >= PSRAM_BASE) && 
+        ((uint32)addr < PSRAM_END_ADDR) && 
+        csi_is_cache_enable()) {
+        ASSERT(!(((uint32)addr) & (BIT(CACHE_CIR_INV_ADDR_Pos)-1)));
+        csi_dcache_clean_range(addr, dsize);
+    }
+}
+/* usefor TCPIP CHKSUM */
+__STATIC_INLINE void sys_dcache_clean_range_unaligned (uint32_t *addr, int32_t dsize)
+{
+    if (((uint32)addr >= PSRAM_BASE) && 
+        ((uint32)addr < PSRAM_END_ADDR) && 
+        csi_is_cache_enable()) {
+        csi_dcache_clean_range(addr, dsize);
+    }
+}
+
+
+/** use when DMA destination is psram 
+ *  1、usage : (  this -> DMA) ; 
+ */
+__STATIC_INLINE void sys_dcache_clean_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    if (((uint32)addr >= PSRAM_BASE) && 
+        ((uint32)addr < PSRAM_END_ADDR) && 
+        csi_is_cache_enable()) {
+        //ASSERT(!(((uint32)addr) & (BIT(CACHE_CIR_INV_ADDR_Pos)-1)));
+        /* data head */
+        if ((uint32_t)addr & 0xF) {
+            csi_dcache_clean_invalid_range(addr, 16);
+        }
+        
+        /* data tail */
+        if (((uint32_t)addr+dsize) & 0xF) {
+            csi_dcache_clean_invalid_range((addr+dsize), 16);
+        }
+        
+        /* data all */
+        csi_dcache_invalid_range(addr, dsize);
+    }
+}
+
+
+/** use when DMA destination is psram 
+ *  1、usage : ( DMA done-> this) ; 
+ *  2、Precondition: dma buffer addr & size is 16byte aligned 
+ *  3、DMA buffer size is not checked
+ */
+__STATIC_INLINE void sys_dcache_invalid_range (uint32_t *addr, int32_t dsize)
+{
+    if (((uint32)addr >= PSRAM_BASE) && 
+        ((uint32)addr < PSRAM_END_ADDR) && 
+        csi_is_cache_enable()) {
+        //ASSERT(!(((uint32)addr) & (BIT(CACHE_CIR_INV_ADDR_Pos)-1)));
+        csi_dcache_invalid_range(addr, dsize);
+    }
+}
+
+#else
+#define sys_dcache_clean_range(addr, dsize)
+#define sys_dcache_clean_range_unaligned(addr, dsize)
+#define sys_dcache_clean_invalid_range(addr, dsize)
+#define sys_dcache_invalid_range(addr, dsize)
+#endif
+
+
+
+int32 sysctrl_is_chipdcn_compid(void);
+/* 速率：x Bps */
+uint32_t sys_dma2ahb_bw_static(int32 printf_en);
+/* miss rate :  万分之x */
+uint32_t sys_csi_cache_static(int32 printf_en);
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__MISC_H__
+
+
+
+/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/
+
+

sdk/include/chip/txw81x/pin_names.h

@@ -0,0 +1,647 @@
+// Revision History
+// V1.0.0  06/01/2019  First Release, copy from 4001a project
+// V1.0.1  07/27/2019  change uart0 to A2/A3
+// V1.0.2  02/07/2020  change PIN_SPI_CS to PIN_SPI0_CS
+// V1.1.0  03/02/2020  add pa/pa-vmode pin
+
+#ifndef _PIN_NAMES_DEF_H_
+#define _PIN_NAMES_DEF_H_
+
+//#include "sys_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*---------------------------------------*/
+/*----------UART PIN DEFINITION----------*/
+/*---------------------------------------*/
+
+/* UART0 */
+#ifndef PIN_UART0_TX
+#define PIN_UART0_TX 255
+#endif
+
+#ifndef PIN_UART0_RX
+#define PIN_UART0_RX 255
+#endif
+
+#ifndef PIN_UART0_DE
+#define PIN_UART0_DE 255
+#endif
+
+#ifndef PIN_UART0_RE
+#define PIN_UART0_RE 255
+#endif
+
+/* UART1 */
+#ifndef PIN_UART1_TX
+#define PIN_UART1_TX 255
+#endif
+
+#ifndef PIN_UART1_RX
+#define PIN_UART1_RX 255
+#endif
+
+/* UART4 */
+#ifndef PIN_UART4_TX
+#define PIN_UART4_TX 255
+#endif
+
+#ifndef PIN_UART4_RX
+#define PIN_UART4_RX 255
+#endif
+
+#ifndef PIN_UART4_DE
+#define PIN_UART4_DE 255
+#endif
+
+#ifndef PIN_UART4_RE
+#define PIN_UART4_RE 255
+#endif
+
+/* UART5 */
+#ifndef PIN_UART5_TX
+#define PIN_UART5_TX 255
+#endif
+
+#ifndef PIN_UART5_RX
+#define PIN_UART5_RX 255
+#endif
+
+#ifndef PIN_UART5_DE
+#define PIN_UART5_DE 255
+#endif
+
+#ifndef PIN_UART5_RE
+#define PIN_UART5_RE 255
+#endif
+
+/*---------------------------------------*/
+/*----------IIC PIN DEFINITION-----------*/
+/*---------------------------------------*/
+
+/* IIC1 */
+#ifndef PIN_IIC1_SCL
+#define PIN_IIC1_SCL 255
+#endif
+
+#ifndef PIN_IIC1_SDA
+#define PIN_IIC1_SDA 255
+#endif
+
+/* IIC2 */
+#ifndef PIN_IIC2_SCL
+#define PIN_IIC2_SCL 255
+#endif
+
+#ifndef PIN_IIC2_SDA
+#define PIN_IIC2_SDA 255
+#endif
+
+
+/*---------------------------------------*/
+/*----------IIS PIN DEFINITION-----------*/
+/*---------------------------------------*/
+
+/* IIS0 */
+#ifndef PIN_IIS0_MCLK
+#define PIN_IIS0_MCLK 255
+#endif
+
+#ifndef PIN_IIS0_BCLK
+#define PIN_IIS0_BCLK 255
+#endif
+
+#ifndef PIN_IIS0_WCLK
+#define PIN_IIS0_WCLK 255
+#endif
+
+#ifndef PIN_IIS0_DATA
+#define PIN_IIS0_DATA 255
+#endif
+
+/* IIS1 */
+#ifndef PIN_IIS1_MCLK
+#define PIN_IIS1_MCLK 255
+#endif
+
+#ifndef PIN_IIS1_BCLK
+#define PIN_IIS1_BCLK 255
+#endif
+
+#ifndef PIN_IIS1_WCLK
+#define PIN_IIS1_WCLK 255
+#endif
+
+#ifndef PIN_IIS1_DATA
+#define PIN_IIS1_DATA 255
+#endif
+
+
+/*---------------------------------------*/
+/*----------PDM PIN DEFINITION-----------*/
+/*---------------------------------------*/
+
+/* PDM */
+#ifndef PIN_PDM_MCLK
+#define PIN_PDM_MCLK 255
+#endif
+
+#ifndef PIN_PDM_DATA
+#define PIN_PDM_DATA 255
+#endif
+
+
+/*---------------------------------------*/
+/*----------LED PIN DEFINITION-----------*/
+/*---------------------------------------*/
+
+/* LED */
+#ifndef PIN_LED_SEG0
+#define PIN_LED_SEG0 255
+#endif
+
+#ifndef PIN_LED_SEG1
+#define PIN_LED_SEG1  255
+#endif
+
+#ifndef PIN_LED_SEG2
+#define PIN_LED_SEG2  255
+#endif
+
+#ifndef PIN_LED_SEG3
+#define PIN_LED_SEG3  255
+#endif
+
+#ifndef PIN_LED_SEG4
+#define PIN_LED_SEG4  255
+#endif
+
+#ifndef PIN_LED_SEG5
+#define PIN_LED_SEG5  255
+#endif
+
+#ifndef PIN_LED_SEG6
+#define PIN_LED_SEG6  255
+#endif
+
+#ifndef PIN_LED_SEG7
+#define PIN_LED_SEG7  255
+#endif
+
+#ifndef PIN_LED_SEG8
+#define PIN_LED_SEG8  255
+#endif
+
+#ifndef PIN_LED_SEG9
+#define PIN_LED_SEG9  255
+#endif
+
+#ifndef PIN_LED_SEG10 
+#define PIN_LED_SEG10 255
+#endif
+
+#ifndef PIN_LED_SEG11
+#define PIN_LED_SEG11 255
+#endif
+
+#ifndef PIN_LED_COM0
+#define PIN_LED_COM0 255
+#endif
+
+#ifndef PIN_LED_COM1
+#define PIN_LED_COM1 255
+#endif
+
+#ifndef PIN_LED_COM2
+#define PIN_LED_COM2 255
+#endif
+
+#ifndef PIN_LED_COM3
+#define PIN_LED_COM3 255
+#endif
+
+#ifndef PIN_LED_COM4
+#define PIN_LED_COM4 255
+#endif
+
+#ifndef PIN_LED_COM5
+#define PIN_LED_COM5 255
+#endif
+
+#ifndef PIN_LED_COM6
+#define PIN_LED_COM6 255
+#endif
+
+#ifndef PIN_LED_COM7
+#define PIN_LED_COM7 255
+#endif
+
+
+/*---------------------------------------*/
+/*---------GMAC PIN DEFINITION-----------*/
+/*---------------------------------------*/
+
+/* GMAC */
+
+#ifndef PIN_GMAC_RMII_REF_CLKIN
+#define PIN_GMAC_RMII_REF_CLKIN PB_14
+#endif
+
+#ifndef PIN_GMAC_RMII_RXD0
+#define PIN_GMAC_RMII_RXD0      PB_12
+#endif
+
+#ifndef PIN_GMAC_RMII_RXD1
+#define PIN_GMAC_RMII_RXD1      PB_13
+#endif
+
+#ifndef PIN_GMAC_RMII_TXD0
+#define PIN_GMAC_RMII_TXD0      PB_15
+#endif
+
+#ifndef PIN_GMAC_RMII_TXD1
+#define PIN_GMAC_RMII_TXD1      PC_0
+#endif
+
+#ifndef PIN_GMAC_RMII_CRS_DV
+#define PIN_GMAC_RMII_CRS_DV    PC_2
+#endif
+
+#ifndef PIN_GMAC_RMII_TX_EN
+#define PIN_GMAC_RMII_TX_EN     PC_1
+#endif
+
+#ifndef PIN_GMAC_RMII_MDIO
+#define PIN_GMAC_RMII_MDIO      PC_4
+#endif
+
+#ifndef PIN_GMAC_RMII_MDC
+#define PIN_GMAC_RMII_MDC       PC_5
+#endif
+
+
+
+/*---------------------------------------*/
+/*---------SDIO PIN DEFINITION-----------*/
+/*---------------------------------------*/
+
+/* SDIO */
+#ifndef PIN_SDCLK
+#define PIN_SDCLK  255
+#endif
+
+#ifndef PIN_SDCMD
+#define PIN_SDCMD  255
+#endif
+
+#ifndef PIN_SDDAT0
+#define PIN_SDDAT0 255
+#endif
+
+#ifndef PIN_SDDAT1
+#define PIN_SDDAT1 255
+#endif
+
+#ifndef PIN_SDDAT2
+#define PIN_SDDAT2 255
+#endif
+
+#ifndef PIN_SDDAT3
+#define PIN_SDDAT3 255
+#endif
+
+
+/*---------------------------------------*/
+/*---------QSPI PIN DEFINITION-----------*/
+/*---------------------------------------*/
+
+/* QSPI */
+#ifndef PIN_QSPI_CS
+#define PIN_QSPI_CS  PB_4
+#endif
+
+#ifndef PIN_QSPI_CLK
+#define PIN_QSPI_CLK PB_1
+#endif
+
+#ifndef PIN_QSPI_IO0
+#define PIN_QSPI_IO0 PB_0
+#endif
+
+#ifndef PIN_QSPI_IO1
+#define PIN_QSPI_IO1 PB_5
+#endif
+
+#ifndef PIN_QSPI_IO2
+#define PIN_QSPI_IO2 PB_3
+#endif
+
+#ifndef PIN_QSPI_IO3
+#define PIN_QSPI_IO3 PB_2
+#endif
+
+#ifndef PIN_QSPI_CS1
+#define PIN_QSPI_CS1 PB_6
+#endif
+
+
+/*---------------------------------------*/
+/*---------SPI PIN DEFINITION------------*/
+/*---------------------------------------*/
+
+/* SPI0 */
+#ifndef PIN_SPI0_CS
+#define PIN_SPI0_CS  255
+#endif
+
+#ifndef PIN_SPI0_CLK
+#define PIN_SPI0_CLK 255
+#endif
+
+#ifndef PIN_SPI0_IO0
+#define PIN_SPI0_IO0 255
+#endif
+
+#ifndef PIN_SPI0_IO1
+#define PIN_SPI0_IO1 255
+#endif
+
+#ifndef PIN_SPI0_IO2
+#define PIN_SPI0_IO2 255
+#endif
+
+#ifndef PIN_SPI0_IO3
+#define PIN_SPI0_IO3 255
+#endif
+
+
+/* SPI1 */
+#ifndef PIN_SPI1_CS
+#define PIN_SPI1_CS  255
+#endif
+
+#ifndef PIN_SPI1_CLK
+#define PIN_SPI1_CLK 255
+#endif
+
+#ifndef PIN_SPI1_IO0
+#define PIN_SPI1_IO0 255
+#endif
+
+#ifndef PIN_SPI1_IO1
+#define PIN_SPI1_IO1 255
+#endif
+
+#ifndef PIN_SPI1_IO2
+#define PIN_SPI1_IO2 255
+#endif
+
+#ifndef PIN_SPI1_IO3
+#define PIN_SPI1_IO3 255
+#endif
+
+/* SPI5 */
+#ifndef PIN_SPI5_CLK
+#define PIN_SPI5_CLK 255
+#endif
+
+#ifndef PIN_SPI5_IO0
+#define PIN_SPI5_IO0 255
+#endif
+
+#ifndef PIN_SPI5_IO1
+#define PIN_SPI5_IO1 255
+#endif
+
+/* SPI6 */
+#ifndef PIN_SPI6_CLK
+#define PIN_SPI6_CLK 255
+#endif
+
+#ifndef PIN_SPI6_IO0
+#define PIN_SPI6_IO0 255
+#endif
+
+#ifndef PIN_SPI6_IO1
+#define PIN_SPI6_IO1 255
+#endif
+
+
+/*---------------------------------------*/
+/*---------ADC PIN DEFINITION------------*/
+/*---------------------------------------*/
+
+/* ADC */
+#ifndef PIN_ADC
+#define PIN_ADC 255
+#endif
+
+
+/*---------------------------------------*/
+/*---------DVP PIN DEFINITION------------*/
+/*---------------------------------------*/
+
+/* DVP */
+#ifndef PIN_DVP_HSYNC
+#define PIN_DVP_HSYNC  PB_7
+#endif
+
+#ifndef PIN_DVP_VSYNC
+#define PIN_DVP_VSYNC  PB_6
+#endif
+
+#ifndef PIN_DVP_PCLK
+#define PIN_DVP_PCLK   PB_12
+#endif
+
+#ifndef PIN_DVP_MCLK
+#define PIN_DVP_MCLK   PB_9
+#endif
+
+#ifndef PIN_DVP_DATA0
+#define PIN_DVP_DATA0  PB_14
+#endif
+
+#ifndef PIN_DVP_DATA1
+#define PIN_DVP_DATA1  PC_0
+#endif
+
+#ifndef PIN_DVP_DATA2
+#define PIN_DVP_DATA2  PC_1
+#endif
+
+#ifndef PIN_DVP_DATA3
+#define PIN_DVP_DATA3  PB_15
+#endif
+
+#ifndef PIN_DVP_DATA4
+#define PIN_DVP_DATA4  PB_13
+#endif
+
+#ifndef PIN_DVP_DATA5
+#define PIN_DVP_DATA5  PB_11
+#endif
+
+#ifndef PIN_DVP_DATA6
+#define PIN_DVP_DATA6  PB_10
+#endif
+
+#ifndef PIN_DVP_DATA7
+#define PIN_DVP_DATA7  PB_8
+#endif
+
+#ifndef PIN_DVP_RESET
+#define PIN_DVP_RESET  255
+#endif
+
+#ifndef PIN_DVP_PDN
+#define PIN_DVP_PDN    255
+#endif
+
+
+/*---------------------------------------*/
+/*---------SDH PIN DEFINITION------------*/
+/*---------------------------------------*/
+
+/* SDH */
+#ifndef PIN_SDH_CLK
+#define PIN_SDH_CLK  255
+#endif
+
+#ifndef PIN_SDH_CMD
+#define PIN_SDH_CMD  255
+#endif
+
+#ifndef PIN_SDH_DAT0
+#define PIN_SDH_DAT0 255
+#endif
+
+#ifndef PIN_SDH_DAT1
+#define PIN_SDH_DAT1 255
+#endif
+
+#ifndef PIN_SDH_DAT2
+#define PIN_SDH_DAT2 255
+#endif
+
+#ifndef PIN_SDH_DAT3
+#define PIN_SDH_DAT3 255
+#endif
+
+/*---------------------------------------*/
+/*---------TIMER PIN DEFINITION----------*/
+/*---------------------------------------*/
+
+/* NORMAL TIMER0 */
+#ifndef PIN_PWM_CHANNEL_0
+#define PIN_PWM_CHANNEL_0 255
+#endif
+
+#ifndef PIN_CAPTURE_CHANNEL_0
+#define PIN_CAPTURE_CHANNEL_0 255
+#endif
+
+/* NORMAL TIMER1 */
+#ifndef PIN_PWM_CHANNEL_1
+#define PIN_PWM_CHANNEL_1 255
+#endif
+
+#ifndef PIN_CAPTURE_CHANNEL_1
+#define PIN_CAPTURE_CHANNEL_1 255
+#endif
+
+/* LED_TIMER0 */
+#ifndef PIN_PWM_CHANNEL_2
+#define PIN_PWM_CHANNEL_2 255
+#endif
+
+/* SUPTMR0 */
+#ifndef PIN_PWM_CHANNEL_3
+#define PIN_PWM_CHANNEL_3 255
+#endif
+
+#ifndef PIN_PWM_CHANNEL_4
+#define PIN_PWM_CHANNEL_4 255
+#endif
+
+#ifndef LCD_TE
+#define LCD_TE 255
+#endif
+
+enum pin_name {
+
+    PA_0  =  0,
+    PA_1,
+    PA_2,
+    PA_3,
+    PA_4,
+    PA_5,
+    PA_6,
+    PA_7,
+    PA_8,
+    PA_9,
+    PA_10,
+    PA_11,
+    PA_12,
+    PA_13,
+    PA_14,
+    PA_15,
+ 
+    PB_0,
+    PB_1,
+    PB_2,
+    PB_3,
+    PB_4,
+    PB_5,
+    PB_6,
+    PB_7,
+    PB_8,
+    PB_9,
+    PB_10,
+    PB_11,
+    PB_12,
+    PB_13,
+    PB_14,
+    PB_15,
+
+    PC_0,
+    PC_1,
+    PC_2,
+    PC_3,
+    PC_4,
+    PC_5,
+    PC_6,
+    PC_7,
+    PC_8,
+    PC_9,
+    PC_10,
+    PC_11,
+    PC_12,
+    PC_13,
+    PC_14,
+    PC_15,
+
+    PE_0,
+    PE_1,
+    PE_2,
+    PE_3,
+    PE_4,
+    PE_5,
+    PE_6,
+    PE_7,
+    PE_8,
+    PE_9,
+    PE_10,
+    PE_11,
+    PE_12,
+    PE_13,
+    PE_14,
+    PE_15,    
+};
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/chip/txw81x/pmu.h

@@ -0,0 +1,553 @@
+/**
+  ******************************************************************************
+  * @file    pmu.h
+  * @author  HUGE-IC Application Team
+  * @version V1.0.0
+  * @date    2021.01.14
+  * @brief   This file contains all the PowerDomain firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
+  *
+  *
+  * Revision History
+  * V1.0.0  2021.01.14  First Release, move from sysctrl
+  *
+  ******************************************************************************
+  */
+
+#ifndef __PMU_H__
+#define __PMU_H__
+
+#include "typesdef.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define CORE_LVD_CON      (0x00>>0)
+#define CORE_LVD_CON1     (0x04>>0)
+#define CORE_LVD_CON2     (0x08>>0)
+#define CORE_PMUCON0 (0x10>>0)
+#define CORE_PMUCON1 (0x14>>0)
+#define CORE_PMUCON2 (0x18>>0)
+#define CORE_PMUCON3 (0x1c>>0)
+#define CORE_PMUCON4 (0x20>>0)
+#define CORE_PMUCON5 (0x24>>0)
+#define CORE_RFCON0  (0x28>>0)
+#define CORE_RFCON1  (0x2c>>0)
+#define CORE_PMUCON6 (0x30>>0)
+#define CORE_PMUCON7 (0x34>>0)
+#define CORE_PMUCON8 (0x38>>0)
+#define CORE_PMUCON9 (0x3c>>0)
+#define CORE_PMUCON10 (0x40>>0)
+#define CORE_PMUCON11 (0x44>>0)
+#define CORE_PMUCON12 (0x48>>0)
+#define CORE_PMUCON13 (0x4c>>0)
+#define CORE_PNDCLR  (0x50>>0)
+
+//-------------RTC part1 start---------------
+#define CORE_RTCWPR       (0x54>>0)	 //54
+#define CORE_RTCCTR       (0x58>>0)  //58 
+#define CORE_RTCPDR       (0x5c>>0)  //5c 
+#define CORE_RTCISR       (0x60>>0)  //60 
+#define CORE_RTCSSR       (0x64>>0)  //64 
+#define CORE_RTCTMR       (0x68>>0)  //68 
+#define CORE_RTCDAR       (0x6c>>0)  //6c 
+#define CORE_RTCALR0R     (0x70>>0)  //70 
+#define CORE_RTCWUTR      (0x74>>0)  //74 
+#define CORE_RTCTSSSR     (0x78>>0)  //78 
+#define CORE_RTCTSTMR     (0x7c>>0)  //7c
+//-------------RTC part1 end---------------
+
+#define CORE_TMRCON  (0x80>>0)
+#define CORE_TMRPR   (0x84>>0)
+#define CORE_TMRRPT  (0x88>>0)
+#define CORE_TMRTRIM (0x8c>>0)
+#define CORE_TMRPR2  (0x90>>0)
+
+//-------------RTC part2 start---------------
+//#define CORE_TMRRTCC (0x94>>0)
+#define CORE_RTCTSDAR     (0x94>>0)  //94 
+#define CORE_RTCCALR      (0x98>>0)  //98 
+#define CORE_RTCSSSR      (0x9c>>0)  //9c 
+//-------------RTC part2 start---------------
+
+#define CORE_WKCON   (0xa0>>0)
+#define CORE_WKCON1  (0xa4>>0)
+#define CORE_WKCON2  (0xa8>>0)
+#define CORE_SECCON  (0xb0>>0)
+#define CORE_SECDAT  (0xb4>>0)
+#define CORE_SECADR  (0xb8>>0)
+#define CORE_SECKEY  (0xbc>>0)
+#define CORE_CMPCON  (0xc0>>0)
+#define CORE_CMPCON1 (0xc4>>0)
+
+#if 0 //vernus
+
+#define CORE_TMR0CON      (0xd0>>0)
+#define CORE_TMR1CON      (0xd4>>0)
+#define CORE_TMR2CON      (0xd8>>0)
+#define CORE_TMR3CON      (0xdc>>0)
+
+#else //vernus200
+
+#define CORE_PMUCON14  (0xc8>>0)
+#define CORE_PMUCON15  (0xcc>>0)
+
+#define CORE_TMR_CON  (0xd0>>0)
+#define CORE_TMR0CON  (0xd4>>0)
+#define CORE_TMR1CON  (0xd8>>0)
+#define CORE_TMR2CON  (0xdc>>0)
+#define CORE_TMR3CON  (0xe0>>0)
+
+#define CORE_WDTCON   (0xe4>>0)
+#define CORE_WDTKEY   (0xe8>>0)
+#endif
+typedef struct
+{
+    __IO uint32 LVD_CON;
+    __IO uint32 LVD_CON1;
+    __IO uint32 LVD_CON2;
+         uint32 RESERVED0;
+    __IO uint32 PMUCON0;
+    __IO uint32 PMUCON1;
+    __IO uint32 PMUCON2;
+    __IO uint32 PMUCON3;
+    __IO uint32 PMUCON4;
+    __IO uint32 PMUCON5;
+    __IO uint32 RFCON0;
+    __IO uint32 RFCON1;
+    __IO uint32 PMUCON6;
+    __IO uint32 PMUCON7;
+    __IO uint32 PMUCON8;
+	__IO uint32 PMUCON9;  
+	__IO uint32 PMUCON10;                          //40
+	__IO uint32 PMUCON11;
+	__IO uint32 PMUCON12;
+	__IO uint32 PMUCON13;
+    __IO uint32 PNDCLR;                            //50
+    
+//-------------RTC part1 start---------------
+    __IO uint32 RTCWPR;                 //54                     
+    __IO uint32 RTCCTR;                 //58                        
+    __IO uint32 RTCPDR;                 //5c                           
+    __IO uint32 RTCISR;                 //60                       
+    __IO uint32 RTCSSR;                 //64                      
+    __IO uint32 RTCTMR;                 //68                      
+    __IO uint32 RTCDAR;                 //6c                    
+    __IO uint32 RTCALR0R;               //70                                           
+    __IO uint32 RTCWUTR;                //74                     
+    __IO uint32 RTCTSSSR;               //78                
+    __IO uint32 RTCTSTMR;               //7c
+    //uint32 RESERVED1[((0x80 - 0x50) / 4) - 1];
+//-------------RTC part1 end---------------
+
+    __IO uint32 TMRCON;                            //80
+    __IO uint32 TMRPR;
+    __IO uint32 TMRRPT;
+    __IO uint32 TMRTRIM;
+    __IO uint32 TMRPR2;                            //90
+    
+//-------------RTC part2 start---------------
+    //__IO uint32 TMRRTCC;                         //remove
+    __IO uint32 RTCTSDAR;               //94                          
+    __IO uint32 RTCCALR;                //98                      
+    __IO uint32 RTCSSSR;                //9c 
+    //uint32 RESERVED2[((0xa0 - 0x94) / 4) - 1];
+//-------------RTC part2 end---------------
+
+	__IO uint32 WKCON;                             //a0
+    __IO uint32 WKCON1;
+    __IO uint32 WKCON2;
+         uint32 RESERVED3[((0xb0 - 0xa8) / 4) - 1];
+    __IO uint32 SECCON;                            //b0
+    __IO uint32 SECDAT;
+    __IO uint32 SECADDR;
+	__IO uint32 SECKEY;
+    __IO uint32 CMPCON;                            //c0
+    __IO uint32 CMPCON1;                           //c4                 
+    __IO uint32 PMUCON14;                          //c8                 
+    __IO uint32 PMUCON15;                          //cc                                
+    __IO uint32 TMR_CON;                           //d0               
+    __IO uint32 TMR0CON0;                          //d4               
+    __IO uint32 TMR1CON0;                          //d8           
+    __IO uint32 TMR2CON0;                          //dc           
+    __IO uint32 TMR3CON0;                          //e0
+    __IO uint32 WDTCON;                            //e0
+    __IO uint32 WDTKEY;                            //e0
+} PMU_TypeDef;
+
+#define PMU               ((PMU_TypeDef *) PMU_BASE)
+
+#define PMU_REG_SET_BITS(reg, bits)                     do { pmu_reg_write((uint32)&reg, (reg)|(bits)); } while(0)
+#define PMU_REG_CLR_BITS(reg, bits)                     do { pmu_reg_write((uint32)&reg, (reg) & ~(bits)); } while(0)
+#define PMU_REG_SET_VALUE(reg, bit_mask, val, bit_pos)  do { pmu_reg_write((uint32)&reg, ((reg) & ~(bit_mask)) | (((val) << (bit_pos)) & (bit_mask)) ); } while(0)
+#define PMU_REG_BIT_FUN(fun_name, reg, bits)\
+__STATIC_INLINE void fun_name##_en(void) { PMU_REG_SET_BITS(reg, bits); }\
+__STATIC_INLINE void fun_name##_dis(void) { PMU_REG_CLR_BITS(reg, bits); }
+
+
+/* lvdcon */
+#define pmu_vcam_oc_int_en()        PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(31))
+#define pmu_vcam_oc_int_dis()       PMU_REG_SET_BITS(PMU->LVD_CON, BIT(31))
+#define PMU_VCAM_OC_PENDING         (PMU->LVD_CON & BIT(30))
+#define PMU_V15_OC_PENDING          (PMU->LVD_CON & BIT(29))
+#define PMU_VDD_OC_PENDING          (PMU->LVD_CON & BIT(28))
+#define PMU_VDD_LV_PENDING          (PMU->LVD_CON & BIT(27))
+#define PMU_VCC_LV_PENDING          (PMU->LVD_CON & BIT(26))
+#define PMU_VCC1_LV_PENDING         (PMU->LVD_CON & BIT(25))
+#define PMU_VCC15_LV_PENDING        (PMU->LVD_CON & BIT(24))
+#define pmu_vcc1_lv_int_en()        PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(23))
+#define pmu_vcc1_lv_int_dis()       PMU_REG_SET_BITS(PMU->LVD_CON, BIT(23))
+#define pmu_vcc15_oc_int_en()       PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(22))
+#define pmu_vcc15_oc_int_dis()      PMU_REG_SET_BITS(PMU->LVD_CON, BIT(22))
+#define pmu_lvd_oe_en()             PMU_REG_SET_BITS(PMU->LVD_CON, BIT(21))
+#define pmu_lvd_oe_dis()            PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(21))
+#define pmu_vdd_oc_int_en()         PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(20))
+#define pmu_vdd_oc_int_dis()        PMU_REG_SET_BITS(PMU->LVD_CON, BIT(20))
+#define pmu_vdd_lv_reset_en()       PMU_REG_SET_BITS(PMU->LVD_CON, BIT(19))
+#define pmu_vdd_lv_reset_dis()      PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(19))
+#define pmu_vcc_lv_reset_en()       PMU_REG_SET_BITS(PMU->LVD_CON, BIT(18))
+#define pmu_vcc_lv_reset_dis()      PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(18))
+#define pmu_vcc15_lv_reset_en()     PMU_REG_SET_BITS(PMU->LVD_CON, BIT(17))
+#define pmu_vcc15_lv_reset_dis()    PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(17))
+
+#define PMU_VDD18_OC_PENDING         (PMU->LVD_CON1 & BIT(31))
+#define PMU_VDD12_OC_PENDING         (PMU->LVD_CON1 & BIT(30))
+
+enum vcc15_oc_level {
+    VCC15_OC_200MA = 0,
+    VCC15_OC_90MA = 0x3,
+    VCC15_OC_70MA,
+    VCC15_OC_60MA,
+    VCC15_OC_50MA,
+};
+#define pmu_vcc15_oc_level_set(vcc15_oc_level)      PMU_REG_SET_VALUE(PMU->LVD_CON, 0x0001c000, vcc15_oc_level, 14)
+
+enum vdd_oc_level {
+    VDD_OC_50MA,
+    VDD_OC_100MA,
+    VDD_OC_150MA,
+    VDD_OC_200MA,
+};
+#define pmu_vdd_oc_level_set(vdd_oc_level)          PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00003000, vdd_oc_level, 12)
+
+enum vcc15_lv_level {
+    VCC15_LV_0V86_T_0V90,
+    VCC15_LV_1V00_T_1V05,
+    VCC15_LV_1V14_T_1V19,
+    VCC15_LV_1V29_T_1V35,
+
+};
+#define pmu_vcc15_lv_level_set(vcc15_lv_level)      PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000c00, vcc15_lv_level, 10)
+
+enum vdd_lv_level {
+    VDD_LV_0V64_T_0V68,
+    VDD_LV_0V74_T_0V78,
+    VDD_LV_0V84_T_0V88,
+    VDD_LV_0V84_T_0V98,
+};
+#define pmu_vdd_lv_level_set(vdd_lv_level)          PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000300, vdd_lv_level, 8)
+
+enum avcc_lv_level {
+    AVCC_LV_1V90_T_1V99,
+    AVCC_LV_2V06_T_2V16,
+    AVCC_LV_2V21_T_2V31,
+    AVCC_LV_2V33_T_2V44,
+    AVCC_LV_2V46_T_2V58,
+    AVCC_LV_2V62_T_2V74,
+    AVCC_LV_2V75_T_2V87,
+    AVCC_LV_2V90_T_3V04,
+};
+#define pmu_avcc_lv_level_set(avcc_lv_level)        PMU_REG_SET_VALUE(PMU->LVD_CON, 0x000000e0, avcc_lv_level, 5)
+
+enum vcc1_lv_level {
+    VCC1_LV_2V54_T_2V66,
+    VCC1_LV_1V46_T_1V53,
+};
+#define pmu_vcc1_lv_level_set(vcc1_lv_level)        PMU_REG_SET_VALUE(PMU->LVD_CON, 0x00000010, vcc1_lv_level, 4)
+
+#define pmu_vdd_lv_detect_en()                      PMU_REG_SET_BITS(PMU->LVD_CON, BIT(3))
+#define pmu_vdd_lv_detect_dis()                     PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(3))
+#define pmu_avcc_lv_detect_en()                     PMU_REG_SET_BITS(PMU->LVD_CON, BIT(2))
+#define pmu_avcc_lv_detect_dis()                    PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(2))
+#define pmu_vcc1_lv_detect_en()                     PMU_REG_SET_BITS(PMU->LVD_CON, BIT(1))
+#define pmu_vcc1_lv_detect_dis()                    PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(1))
+#define pmu_vcc15_lv_detect_en()                    PMU_REG_SET_BITS(PMU->LVD_CON, BIT(0))
+#define pmu_vcc15_lv_detect_dis()                   PMU_REG_CLR_BITS(PMU->LVD_CON, BIT(0))
+
+/* lvdcon1 */
+#define pmu_vcc_lv_detect_sync_en()                 PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(30))
+#define pmu_vcc_lv_detect_sync_dis()                PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(30))
+#define pmu_vdd_lv_detect_filter_en()               PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(29))
+#define pmu_vdd_lv_detect_filter_dis()              PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(29))
+#define pmu_vcc_lv_detect_filter_en()               PMU_REG_CLR_BITS(PMU->LVD_CON1, BIT(28))
+#define pmu_vcc_lv_detect_filter_dis()              PMU_REG_SET_BITS(PMU->LVD_CON1, BIT(28))
+#define pmu_vdd_oc_lv_ldetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
+#define pmu_vdd_oc_lv_ldetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0FE00000, level, 21)
+#define pmu_vdd_oc_lv_hdetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
+#define pmu_vdd_oc_lv_hdetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x01FC000, level, 14)
+#define pmu_vcc_oc_lv_ldetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
+#define pmu_vcc_oc_lv_ldetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x00003f80, level, 7)
+#define pmu_vcc_oc_lv_hdetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
+#define pmu_vcc_oc_lv_hdetect_filter_set(level)     PMU_REG_SET_VALUE(PMU->LVD_CON1, 0x0000007f, level, 0)
+
+/* lvdcon2 */
+#define pmu_vcc1_lv_detect_filter_en()              PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(29))
+#define pmu_vcc1_lv_detect_filter_dis()             PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(29))
+#define pmu_vcc15_lv_detect_filter_en()             PMU_REG_CLR_BITS(PMU->LVD_CON2, BIT(28))
+#define pmu_vcc15_lv_detect_filter_dis()            PMU_REG_SET_BITS(PMU->LVD_CON2, BIT(28))
+#define pmu_vcc1_oc_lv_ldetect_filter_set(level)    PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
+#define pmu_vcc1_oc_lv_ldetect_filter_set(level)    PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0FE00000, level, 21)
+#define pmu_vcc1_oc_lv_hdetect_filter_set(level)    PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
+#define pmu_vcc1_oc_lv_hdetect_filter_set(level)    PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x001FC000, level, 14)
+#define pmu_vcc15_oc_lv_ldetect_filter_set(level)   PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
+#define pmu_vcc15_oc_lv_ldetect_filter_set(level)   PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x00003f80, level, 7)
+#define pmu_vcc15_oc_lv_hdetect_filter_set(level)   PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
+#define pmu_vcc15_oc_lv_hdetect_filter_set(level)   PMU_REG_SET_VALUE(PMU->LVD_CON2, 0x0000007f, level, 0)
+
+/* CORE_PMUCON0 */
+#define pmu_port_wk_auto_dis_en()                   PMU_REG_SET_BITS(PMU->PMUCON0, BIT(29))
+#define pmu_port_wk_auto_dis_dis()                  PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(29))
+#define pmu_mclr_soft_en()                          PMU_REG_SET_BITS(PMU->PMUCON0, BIT(28))
+#define pmu_mclr_soft_dis()                         PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(28))
+#define pmu_led_io_mux_en()                         PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(27))
+#define pmu_led_io_mux_dis()                        PMU_REG_SET_BITS(PMU->PMUCON0, BIT(27))
+enum pd_tmr1_clk_sel {
+    PD_TMR1_CLK_RC128K,
+    PD_TMR1_CLK_XOSC,
+    PD_TMR1_CLK_RC10M,
+    PD_TMR1_CLK_LX32K,
+};
+#define pmu_pd_tmr1_clk_sel(pd_tmr1_clk_sel)        PMU_REG_SET_VALUE(PMU->PMUCON0, 0x06000000, pd_tmr1_clk_sel, 25)
+
+#define pmu_pd_mem2_en()                            PMU_REG_SET_BITS(PMU->PMUCON0, BIT(24))
+#define pmu_pd_mem2_dis()                           PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(24))
+#define pmu_fls_pg_en()                             PMU_REG_SET_BITS(PMU->PMUCON0, BIT(23))
+#define pmu_fls_pg_dis()                            PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(23))
+#define pmu_pd_mem32k_en()                          PMU_REG_SET_BITS(PMU->PMUCON0, BIT(22))
+#define pmu_pd_mem32k_dis()                         PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(22))
+#define pmu_pd_ulp_en()                             PMU_REG_SET_BITS(PMU->PMUCON0, BIT(21))
+#define pmu_pd_ulp_dis()                            PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(21))
+#define pmu_pd_rf_latch_en()                        PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(19))
+#define pmu_pd_rf_latch_dis()                       PMU_REG_SET_BITS(PMU->PMUCON0, BIT(19))
+#define pmu_pd_osc_en()                             PMU_REG_SET_BITS(PMU->PMUCON0, BIT(18))
+#define pmu_pd_osc_dis()                            PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(18))
+#define pmu_pd_osc_hw_trim_en()                     PMU_REG_SET_BITS(PMU->PMUCON0, BIT(17))
+#define pmu_pd_osc_hw_trim_dis()                    PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(17))
+enum pd_tmr_clk_sel {
+    PD_TMR_CLK_RC128K,
+    PD_TMR_CLK_XOSC,
+    PD_TMR_CLK_RC10M,
+    PD_TMR_CLK_LX32K,
+};
+#define pmu_pd_tmr_clk_sel(pd_tmr_clk_sel)          PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00018000, pd_tmr_clk_sel, 15)
+#define pmu_io_clk_en()                             PMU_REG_SET_BITS(PMU->PMUCON0, BIT(14))
+#define pmu_io_clk_dis()                            PMU_REG_CLR_BITS(PMU->PMUCON0, BIT(14))
+enum lpvdd_vol_level {
+    LPVDD_VOL_0V74,
+    LPVDD_VOL_0V81,
+    LPVDD_VOL_0V88,
+    LPVDD_VOL_0V95,
+    LPVDD_VOL_1V02,
+    LPVDD_VOL_1V09,
+    LPVDD_VOL_1V16,
+    LPVDD_VOL_1V23,
+};
+#define pmu_lpvdd_vol_set(lpvdd_vol_level)          PMU_REG_SET_VALUE(PMU->PMUCON0, 0x00000700, lpvdd_vol_level, 8)
+
+
+/* CORE_PMUCON1 */
+/* CORE_PMUCON2 */
+/* CORE_PMUCON3 */
+/* CORE_PMUCON4 */
+/* CORE_PMUCON5 */
+enum vdd15_vol_level {
+    VDD15_VOL_1V2,
+    VDD15_VOL_1V3,
+    VDD15_VOL_1V4,
+    VDD15_VOL_1V5,
+    VDD15_VOL_1V6,
+    VDD15_VOL_1V7,
+    VDD15_VOL_1V8,
+    VDD15_VOL_1V9,
+    VDD15_VOL_2V0,
+    VDD15_VOL_2V1,
+    VDD15_VOL_2V2,
+    VDD15_VOL_2V3,
+    VDD15_VOL_2V4,
+    VDD15_VOL_2V5,
+};
+#define pmu_vdd15_vol_set(vdd15_vol_level)          PMU_REG_SET_VALUE(PMU->PMUCON5, 0xF, vdd15_vol_level, 0)
+
+
+#define pmu_hirc_10mhz_en()                         PMU_REG_SET_BITS(PMU->PMUCON5, BIT(24))
+#define pmu_hirc_10mhz_dis()                        PMU_REG_CLR_BITS(PMU->PMUCON5, BIT(24))
+
+
+/* CORE_PMUCON7 */
+#define pmu_boot_direct_run_en()                    PMU_REG_SET_BITS(PMU->PMUCON7, BIT(0))
+#define pmu_boot_direct_run_dis()                   PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(0))
+#define pmu_get_boot_direct_run_pending()           ((PMU->PMUCON7 & BIT(0)))
+#define pmu_get_boot_direct_run_pending2()           ((PMU->PMUCON7 & BIT(23)))
+#define pmu_set_direct_run_pengding2()              PMU_REG_SET_BITS(PMU->PMUCON7, BIT(23))
+#define pmu_clr_direct_run_pengding2()              PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(23))
+
+#define pmu_set_direct_run_addr(addr)               PMU_REG_SET_VALUE(PMU->PMUCON7, 0xFF000000, ((addr >> 12) & 0xFF), 24)
+#define pmu_get_boot_code_pos()                     ((PMU->PMUCON7 & BIT(3)) ? 1 : 0)
+#define pmu_get_cp_fail_pending()                   ((PMU->PMUCON7 & BIT(2)) ? 1 : 0)
+#define pmu_clr_cp_fail_pending()                   PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(2))
+#define pmu_get_deadcode_pending()                  ((PMU->PMUCON7 & BIT(1)) ? 1 : 0)
+#define pmu_clr_deadcode_pending()                  PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(1))
+#define pmu_set_deadcode_pending()                  PMU_REG_SET_BITS(PMU->PMUCON7, BIT(1))
+
+#define GET_DIRECT_RUN_DISABLE_SIGN()               ((PMU->PMUCON7 & BIT(4)) ? 1 : 0)
+#define SET_DIRECT_RUN_DISABLE_SIGN(n)\
+    do {\
+        if (n)  PMU_REG_SET_BITS(PMU->PMUCON7, BIT(4));\
+        else    PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(4));\
+    } while(0)
+
+#define GET_SKIP_MASTER_BOOT_SIGN()     ((PMU->PMUCON7 & BIT(5)) ? 1 : 0)
+#define SET_SKIP_MASTER_BOOT_SIGN(n)\
+    do {\
+        if (n)  PMU_REG_SET_BITS(PMU->PMUCON7, BIT(5));\
+        else    PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(5));\
+    } while(0)
+
+#define GET_SKIP_TEST_MODE_SIGN()     ((PMU->PMUCON7 & BIT(6)))
+#define SET_SKIP_TEST_MODE_SIGN(n)\
+    do {\
+        if (n)  PMU_REG_SET_BITS(PMU->PMUCON7, BIT(6));\
+        else    PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(6));\
+    } while(0)
+
+#define GET_SKIP_PSRAM_SIGN()     ((PMU->PMUCON7 & BIT(7)))
+#define SET_SKIP_PSRAM_SIGN(n)\
+    do {\
+        if (n)  PMU_REG_SET_BITS(PMU->PMUCON7, BIT(7));\
+        else    PMU_REG_CLR_BITS(PMU->PMUCON7, BIT(7));\
+    } while(0)
+
+
+/* CORE_PMUCON8 */
+#define pmu_jtag_io_en()                            PMU_REG_SET_BITS(PMU->PMUCON8, BIT(0))
+#define pmu_jtag_io_dis()                           PMU_REG_CLR_BITS(PMU->PMUCON8, BIT(0))
+
+
+/* CORE_PMUCON11 */
+#define VCCFLS_PG_DISABLE()\
+    do {\
+         pmu_reg_write((uint32)&PMU->PMUCON0,  PMU->PMUCON0 & (~ BIT(23))); \
+         pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 | (BIT(17))); \
+    } while(0)
+    
+#define VCCFLS_PG_ENABLE()\
+    do {\
+         pmu_reg_write((uint32)&PMU->PMUCON11, PMU->PMUCON11 & (~ BIT(17)));\
+         pmu_reg_write((uint32)&PMU->PMUCON0,  PMU->PMUCON0 | BIT(23)); \
+    } while(0)
+
+#define pmu_vcam_lc_dis()                           PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(29))
+#define pmu_vcam_lc_en()                            PMU_REG_SET_BITS(PMU->PMUCON11, BIT(29))
+#define pmu_vcam_pg_en()                            PMU_REG_SET_BITS(PMU->PMUCON11, BIT(16))
+#define pmu_vcam_pg_dis()                           PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(16))
+#define pmu_vcam_oc_detect_en()                     PMU_REG_SET_BITS(PMU->PMUCON11, BIT(15))
+#define pmu_vcam_oc_detect_dis()                    PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(15))
+#define pmu_vcam_en()                               PMU_REG_SET_BITS(PMU->PMUCON11, BIT(14))
+#define pmu_vcam_dis()                              PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(14))
+#define pmu_vcam_discharge_en()                     PMU_REG_SET_BITS(PMU->PMUCON11, BIT(13))
+#define pmu_vcam_discharge_dis()                    PMU_REG_CLR_BITS(PMU->PMUCON11, BIT(13))
+
+enum vcam_vol_level {
+    VCAM_VOL_2V50,
+    VCAM_VOL_2V55,
+    VCAM_VOL_2V60,
+    VCAM_VOL_2V65,
+    VCAM_VOL_2V70,
+    VCAM_VOL_2V75,
+    VCAM_VOL_2V80,
+    VCAM_VOL_2V85,
+    VCAM_VOL_2V90,
+    VCAM_VOL_2V95,
+    VCAM_VOL_3V00,
+    VCAM_VOL_3V05,
+    VCAM_VOL_3V10,
+    VCAM_VOL_3V15,
+    VCAM_VOL_3V20,
+    VCAM_VOL_3V25,
+};
+#define pmu_set_vcam_vol(vcam_vol_level)            PMU_REG_SET_VALUE(PMU->PMUCON11, 0x01e00000, vcam_vol_level, 21)
+
+
+/* CORE_RFCON0 */
+#define pmu_xo_cs_set(xo_cs_vdd)                    PMU_REG_SET_VALUE(PMU->RFCON0, 0x03f80000, xo_cs_vdd, 19)
+#define xo_set_cs_sec(xo_cs_vdd)                    pmu_xo_cs_set(xo_cs_vdd)
+
+#define pmu_xosc_en()                               PMU_REG_SET_BITS(PMU->RFCON0, BIT(0))
+#define pmu_xosc_dis()                              PMU_REG_CLR_BITS(PMU->RFCON0, BIT(0))
+
+
+
+struct system_reset_info {
+    union {
+        uint32 system_reset_pending;
+        struct system_reset_pending_bits {
+            uint32  srp_mclr : 1,
+                    srp_soft : 1,
+                    srp_wdt : 1,
+                    srp_lvd : 1,
+                    srp_lvd_vcam_cur_ov : 1,
+                    srp_lvd_vcc15_cur_ov : 1,
+                    srp_lvd_vdd_cur_ov : 1,
+                    srp_lvd_vdd_vol_low : 1,
+                    
+                    srp_lvd_vcc_vol_low : 1,
+                    srp_lvd_vcc1_vol_low : 1,
+                    srp_lvd_vcc15_vol_low : 1,
+                    srp_deep_sleep : 1,
+                    srp_lvd_vdd18_cur_ov : 1,
+                    srp_lvd_vdd12_cur_ov : 1,
+                    srp_lp_wdt : 1,
+                    
+                    Reserved : 16,
+                    srp_detected : 1;
+        } system_reset_pending_bits_s;
+    };
+}  __attribute__((packed));
+
+
+extern struct system_reset_info sri;
+
+
+void pmu_reg_write(uint32 reg_addr, uint32 data) ;
+
+void pmu_dcdc_open(void);
+void pmu_tsensor_chan_sel_sec(uint8 chan_idx);
+void pmu_pd_set_anatop_en_sec(void);
+int jtag_map_set(uint8 val);
+
+void tsensor_open(void);
+void tsensor_close(void);
+
+void lvd_irq_handler(void *data);
+void sys_reset_detect(void);
+void sys_reset_pending_clr(void);
+void sys_reset_show(void);
+void pmu_vdd_core_set(uint32 vddcore);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PMU_H__
+
+
+
+/******************* (C) COPYRIGHT 2021 HUGE-IC *****END OF FILE****/
+
+

sdk/include/chip/txw81x/sysctrl.h

@@ -0,0 +1,860 @@
+/**
+  ******************************************************************************
+  * @file    sysctrl.h
+  * @author  HUGE-IC Application Team
+  * @version V1.0.0
+  * @date    2021.01.14
+  * @brief   This file contains all the PowerDomain firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2021 HUGE-IC</center></h2>
+  *
+  *
+  * Revision History
+  * V1.0.0  2021.01.14  First Release
+  *
+  ******************************************************************************
+  */
+
+// Define to prevent recursive inclusion //////////////////////////////
+#ifndef __SYSCTRL_H__
+#define __SYSCTRL_H__
+
+
+#include "typesdef.h"
+#include "pmu.h"
+#include "misc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @defgroup SYSCTRL_Exported_Constants
+  * @{
+  */
+
+#define CLK_RC128K             128000
+#define CLK_HXOSC              40000000
+#define CLK_SYSPLL             360000000
+#define CLK_USBPLL             480000000
+#define CLK_RC10M              10000000
+#define CLK_LXOSC32K           32000
+
+#define EFUSE_PACK_OFFSET               119
+#define EFUSE_BIOS_ID                   113
+#define EFUSE_5_10M_DIS_OFFSET          118
+#define EFUSE_5_10M_DIS_SIZE            1       //bit 2
+
+//芯片封装定义
+#define PACK_811_100                    0x01
+#define PACK_812_310                    0x02
+#define PACK_813_320                    0x03
+#define PACK_816_G00                    0x06    //QFN48
+    #define PACK_816_G00_FIX            0xF6    //QFN48 ， 改启动模式补救PCBA
+#define PACK_KL908                      0x07    //QFN48 PACK_816_G00 基础上增加VCC18 LDO封装
+    #define PACK_KL908F                 0x16    //QFN48
+#define PACK_816_810                    0x08    //QFN48
+#define PACK_817_810                    0x0A
+#define PACK_817_H24                    0x0B
+#define PACK_817_824                    0x0C
+#define PACK_817_812                    0x0D
+#define PACK_817_824F                   0x0F
+#define PACK_818_C04L                   0x10
+#define PACK_818_C08L                   0x11
+#define PACK_818_C016L                  0x12  
+#define PACK_818_C04F                   0x13
+#define PACK_818_C04LB                  0x14
+#define PACK_818_C08LP                  0x15
+#define PACK_817_824_GD                 0x1C
+
+struct __clock_cfg {
+    uint8  clk_source_sel;
+    uint8  clk_valid;
+    uint16 reserved;
+    uint32 exosc_clk_hz; /* read from efuse */
+    uint32 hirc_clk_hz;  /* read from efuse */
+    uint32 sys_clk;
+    uint32 syspll_clk;
+	uint32 max_flash_clk;
+    uint32 flash_clk_mod;
+    uint32 max_psram_clk;
+};
+
+typedef struct
+{
+    __IO uint32 SYS_KEY;
+    __IO uint32 SYS_CON0;
+    __IO uint32 SYS_CON1;
+    __IO uint32 SYS_CON2;
+    __IO uint32 SYS_CON3;
+    __IO uint32 SYS_CON4;
+    __IO uint32 SYS_CON5;
+    __IO uint32 SYS_CON6;
+    __IO uint32 SYS_CON7;
+    __IO uint32 SYS_CON8;
+    __IO uint32 SYS_CON9;
+    __IO uint32 SYS_CON10;
+    __IO uint32 SYS_CON11;
+    __IO uint32 SYS_CON12;
+    __IO uint32 SYS_CON13;
+    __IO uint32 SYS_CON14;
+    __IO uint32 SYS_CON15;
+    __IO uint32 CLK_CON0;
+    __IO uint32 CLK_CON1;
+    __IO uint32 CLK_CON2;
+    __IO uint32 CLK_CON3;
+    __IO uint32 CLK_CON4;
+    __IO uint32 CLK_CON5;
+    __IO uint32 CHIP_ID;
+    __IO uint32 CLK_CON6;
+    __IO uint32 CLK_CON7;
+    __IO uint32 SRAM0_PD_CON;
+    __IO uint32 AIP_CON0;
+    __IO uint32 AIP_CON1;
+    __IO uint32 IO_MAP;
+    __IO uint32 EFUSE_CON;
+    __IO uint32 SYS_ERR0;
+    __IO uint32 SYS_ERR1;
+    __IO uint32 HOSC_MNT;
+    __IO uint32 WK_CTRL;
+    __IO uint32 LP_CTRL;
+    __IO uint32 MBIST_CTRL;
+    __IO uint32 MPE[6];
+    __IO uint32 MPE_PND[6];
+    __IO uint32 MODE_REG;
+    __IO uint32 MBIST_MISR;
+    __IO uint32 MBIST_MISR1;
+    __IO uint32 MBIST_MISR2;
+    __IO uint32 MBIST_MISR3;
+    __IO uint32 MBIST_MISR4;
+    __IO uint32 MBIST_MISR5;
+    __IO uint32 MBIST_MISR6;
+    __IO uint32 MBIST_MISR7;
+    __IO uint32 USB20_PHY_CFG0;
+    __IO uint32 USB20_PHY_CFG1;
+    __IO uint32 USB20_PHY_CFG2;
+    __IO uint32 USB20_PHY_CFG3;
+    __IO uint32 USB20_PHY_DBG0;
+    __IO uint32 USB20_PHY_DBG1;
+         uint32 RESERVED0[16];
+    __IO uint32 IOFUNCINCON0;
+    __IO uint32 IOFUNCINCON1;
+    __IO uint32 IOFUNCINCON2;
+    __IO uint32 IOFUNCINCON3;
+    __IO uint32 IOFUNCINCON4;
+    __IO uint32 IOFUNCINCON5;
+    __IO uint32 IOFUNCINCON6;
+    __IO uint32 IOFUNCINCON7;
+    __IO uint32 IOFUNCINCON8;
+    __IO uint32 IOFUNCINCON9;
+    __IO uint32 IOFUNCINCON10;
+    __IO uint32 IOFUNCINCON11;
+    __IO uint32 IOFUNCINCON12;
+    __IO uint32 IOFUNCINCON13;
+    __IO uint32 IOFUNCINCON14;
+    __IO uint32 IOFUNCINCON15;
+    __IO uint32 IOFUNCMASK0;
+    __IO uint32 QSPI_MAP_CTL;
+    __IO uint32 QSPI_ENCDEC_CON0;
+    __IO uint32 QSPI_ENCDEC_CON1;
+    __IO uint32 TRNG;
+    __IO uint32 DCRC_TRIM;
+    __IO uint32 CPU1_CON0;
+    __IO uint32 CPU1_CON1; 
+    __IO uint32 IOFUNCMASK1;
+    __IO uint32 PE16CON;
+    __IO uint32 OSPI_MAP_CTL0;
+    __IO uint32 OSPI_MAP_CTL1;
+    __IO uint32 IOFUNCMASK2; 
+} SYSCTRL_TypeDef;
+
+
+#define SYSCTRL                 ((SYSCTRL_TypeDef    *) HG_SYSCTRL_BASE)
+
+#if SYS_KEY_OPT_EN
+#define sysctrl_unlock()                        do { SYSCTRL->SYS_KEY = 0x3fac87e4; } while(0)
+#define sysctrl_lock()                          do { SYSCTRL->SYS_KEY = ~ 0x3fac87e4; } while(0)
+#define SYSCTRL_REG_OPT_INIT()                  do { sysctrl_lock(); SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; } while(0)
+#define SYSCTRL_REG_OPT(expr)                   do { uint32 flag=disable_irq(); sysctrl_unlock(); expr; sysctrl_lock(); enable_irq(flag); } while(0)
+#define EFUSE_REG_OPT(expr)                     do { uint32 flag=disable_irq(); SYSCTRL->SYS_KEY = 0x4c5de9b3; expr; __NOP();__NOP();__NOP(); SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; sysctrl_lock(); enable_irq(flag); } while(0)
+#else
+#define sysctrl_unlock()
+#define sysctrl_lock()
+#define SYSCTRL_REG_OPT_INIT()                  do { SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; SYSCTRL->SYS_KEY = 0x3fac87e4; } while(0)
+#define SYSCTRL_REG_OPT(expr)                   do { expr; } while(0)
+#define EFUSE_REG_OPT(expr)                     do { uint32 flag=disable_irq(); SYSCTRL->SYS_KEY = 0x4c5de9b3; expr; __NOP();__NOP();__NOP(); SYSCTRL->SYS_KEY = ~ 0x4c5de9b3; enable_irq(flag); } while(0)
+#endif
+
+#define SYSCTRL_REG_BITS_S0S1(reg, bits)       do { SYSCTRL_REG_OPT( reg &= ~(bits); __NOP();__NOP();__NOP(); (reg) |= (bits); ); } while(0)
+#define SYSCTRL_REG_BITS_S1S0(reg, bits)       do { SYSCTRL_REG_OPT( reg |= (bits); __NOP();__NOP();__NOP(); (reg) &= ~(bits); ); } while(0)
+#define SYSCTRL_REG_SET_BITS(reg, bits)        do { SYSCTRL_REG_OPT( reg |=  (bits); ); } while(0)
+#define SYSCTRL_REG_CLR_BITS(reg, bits)        do { SYSCTRL_REG_OPT( reg &= ~(bits); ); } while(0)
+#define SYSCTRL_REG_SET_VALUE(reg, bit_mask, val, bit_pos)  do { SYSCTRL_REG_OPT( reg = ((reg) & ~(bit_mask)) | (((val) << (bit_pos)) & (bit_mask)); ); } while(0)
+#define SYSCTRL_REG_BIT_FUN(fun_name, reg, bits)\
+__STATIC_INLINE void fun_name##_en(void) { SYSCTRL_REG_SET_BITS(reg, bits); }\
+__STATIC_INLINE void fun_name##_dis(void) { SYSCTRL_REG_CLR_BITS(reg, bits); }
+
+enum iis_clk_src {
+    IIS_CLK_NONE, 
+    IIS_CLK_SYSPLL, 
+    IIS_CLK_USBPLL, 
+    IIS_CLK_XOSC, 
+};
+/* SYS_CON0 */
+#define sysctrl_iis1_clk_sel(iis_clk_src)         SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, BIT(31)|BIT(30), iis_clk_src, 30) 
+#define sysctrl_rssi_ck_sel_rssi_done()           SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(29))
+#define sysctrl_rssi_ck_sel_rssi_en()             SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(29))
+#define sysctrl_rssi_sel_rssi_done()              SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(28))
+#define sysctrl_rssi_sel_rssi_en()                SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(28))
+#define sysctrl_dbg_seg9_sel(n)                   SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, 0xFF00000, n, 20) 
+#define sysctrl_dbg_seg8_sel(n)                   SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, 0xFF000, n, 12)
+
+#define sysctrl_iis0_clk_sel(iis_clk_src)         SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, BIT(11)|BIT(10), iis_clk_src, 10)
+#define sysctrl_mac_pa_en()                       SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(9))
+#define sysctrl_mac_pa_dis()                      SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(9))
+#define sysctrl_qspi_dlychain_cfg(n)              SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON0, 0x1F0, n, 4)
+#define sysctrl_qspi_clkin_dis()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(3))
+#define sysctrl_qspi_clkin_en()                   SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(3))
+#define sysctrl_mjpeg_reset()                     SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON0, BIT(2))
+#define sysctrl_iis1_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON0, BIT(1))
+#define sysctrl_wdt_at_lp_gate_en()               SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON0, BIT(0))
+#define sysctrl_wdt_at_lp_gate_dis()              SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON0, BIT(0))
+
+
+/* SYS_CON1 */
+#define sysctrl_qspi_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(31))
+#define sysctrl_sha_reset()                       SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(30))
+#define sysctrl_usb20sie_reset()                  SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(29))
+#define sysctrl_dvp_reset()                       SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(28))
+#define sysctrl_dma2ahb_sched_reset()             SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(27))
+#define sysctrl_dbg_dma_reset()                   SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(26))
+#define sysctrl_rf_dig_calib_reset()              SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(25))
+#define sysctrl_saradc_sys_reset()                SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(24))
+#define sysctrl_modem_reset()                     SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(22))
+#define sysctrl_mac_reset()                       SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(21))
+#define sysctrl_sdhc_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(20))
+#define sysctrl_sdio_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(19))
+#define sysctrl_usb20_phy_reset()                 SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(18))
+#define sysctrl_pdm_reset()                       SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(17))
+#define sysctrl_gmac_sys_rst()                    SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(16))
+#define sysctrl_sysaes_reset()                    SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(15))
+#define sysctrl_crc_reset()                       SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(14))
+#define sysctrl_iis0_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(13))
+#define sysctrl_timer_reset()                     SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(12))
+#define sysctrl_uart1_reset()                     SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(11))
+#define sysctrl_uart0_reset()                     SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(10))
+#define sysctrl_tk_reset()                        SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(8))
+#define sysctrl_spi2_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(7))
+#define sysctrl_spi1_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(6))
+#define sysctrl_spi0_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(5))
+#define sysctrl_wdt_reset()                       SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, (BIT(4)|BIT(3)))
+#define sysctrl_m2m_dma_reset()                   SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(2))
+#define sysctrl_memory_reset()                    SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(1))
+#define sysctrl_gpio_reset()                      SYSCTRL_REG_BITS_S0S1(SYSCTRL->SYS_CON1, BIT(0))
+
+
+/* SYS_CON2 */
+#define sysctrl_pdm_mclk_div(n)                   SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON2, 0x7F00000, n, 20) /* N > 1 */
+enum pdm_clk_src {
+    PDM_CLK_NONE, 
+    PDM_CLK_SYSPLL, 
+    PDM_CLK_USBPLL, 
+    PDM_CLK_XOSC, 
+};
+#define sysctrl_pdm_clk_sel(pdm_clk_src)          SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON2, BIT(19)|BIT(18), pdm_clk_src, 18) 
+#define sysctrl_xosc_loss_nmi_dis()               SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(17))
+#define sysctrl_xosc_loss_nmi_en()                SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(17))
+#define sysctrl_xosc_loss_swrc_dis()              SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(16))
+#define sysctrl_xosc_loss_swrc_en()               SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(16))
+#define sysctrl_sdio_cmd_wk_en()                  SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(10))
+#define sysctrl_sdio_cmd_wk_dis()                 SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(10))
+#define sysctrl_cpu_clk_en()                      SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(9))
+#define sysctrl_cpu_clk_dis()                     SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(9))
+#define sysctrl_gmac_dma_disable()                SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(7))
+#define sysctrl_gmac_dma_enable()                 SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(7))
+#define sysctrl_syserr_int_dis()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(6))
+#define sysctrl_syserr_int_en()                   SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(6))
+#define sysctrl_apb1_wr_optimize_dis()            SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(5)) /* sfr write optimze from 3 to 2 cycle */
+#define sysctrl_apb1_wr_optimize_en()             SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(5))
+#define sysctrl_apb0_wr_optimize_dis()            SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(4))
+#define sysctrl_apb0_wr_optimize_en()             SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(4))
+#define sysctrl_nmi_port_dis()                    SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(3)) /* PA4 */
+#define sysctrl_nmi_port_en()                     SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(3))
+#define sysctrl_iis_duplex_dis()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON2, BIT(0))
+#define sysctrl_iis_duplex_en()                   SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON2, BIT(0))
+
+/* SYS_CON3 */
+#define sysctrl_gmac_dbc_pll_sel(n)               SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(31), n, 31) 
+#define sysctrl_dvp_dbc_pll_sel(n)                SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(30), n, 30) 
+#define sysctrl_iis1_mclk_sel(n)                  SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(29), n, 29) 
+#define sysctrl_iis0_mclk_sel(n)                  SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(28), n, 28) 
+#define sysctrl_iis01_mclk_sel(n)                 SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(27), n, 27) 
+enum gpio_dbc_clk_src {
+    GPIO_DEBUNCE_CLK_RC128K, 
+    GPIO_DEBUNCE_CLK_XOSC, 
+    GPIO_DEBUNCE_CLK_FCLK, 
+    GPIO_DEBUNCE_CLK_RC32K,
+};
+#define sysctrl_gpioc_dbc_clk_sel(gpio_dbc_clk_src)   SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(25)|BIT(24), gpio_dbc_clk_src, 24) 
+#define sysctrl_gpiob_dbc_clk_sel(gpio_dbc_clk_src)   SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(23)|BIT(22), gpio_dbc_clk_src, 22) 
+#define sysctrl_gpioa_dbc_clk_sel(gpio_dbc_clk_src)   SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(21)|BIT(20), gpio_dbc_clk_src, 20) 
+// #define sysctrl_trng_clk_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON3, BIT(19), n, 19) 
+#define sysctrl_err_rsp_sdio_bus_en()                 SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(18))
+#define sysctrl_err_rsp_sdio_bus_dis()                SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(18))
+
+
+// #define sysctrl_tk_clk_en()                           SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(17))
+// #define sysctrl_tk_clk_dis()                          SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(17))
+#define sysctrl_err_rsp_dbus_en()                     SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(16))
+#define sysctrl_err_rsp_dbus_dis()                    SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(16))
+#define sysctrl_err_rsp_ibus_en()                     SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(15))
+#define sysctrl_err_rsp_ibus_dis()                    SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(15))
+#define sysctrl_audio_mem_pd_en()                     SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(14))
+#define sysctrl_audio_mem_pd_dis()                    SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(14))
+#define sysctrl_pll1_clk_sel_120M()                   SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(12))
+#define sysctrl_pll1_clk_sel_div3()                   SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(12))
+#define sysctrl_pll_src_upll_div4()                   SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(12))
+// #define sysctrl_pll_src_spll_div2()                   SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(11))
+// #define sysctrl_pll_src_spll_div3()                   SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(11))
+#define sysctrl_bb_clk_en()                           SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(5))
+#define sysctrl_bb_clk_dis()                          SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(5))
+#define sysctrl_usb_wk_en()                           SYSCTRL_REG_SET_BITS(SYSCTRL->SYS_CON3, BIT(4))
+#define sysctrl_usb_wk_dis()                          SYSCTRL_REG_CLR_BITS(SYSCTRL->SYS_CON3, BIT(4))
+
+/* SYS_CON6 */
+#define sysctrl_dbg_seg3_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0xFF000000, n, 24)
+#define sysctrl_dbg_seg2_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0x00FF0000, n, 16)
+#define sysctrl_dbg_seg1_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0x0000FF00, n, 8)
+#define sysctrl_dbg_seg0_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON6, 0x000000FF, n, 0)
+
+/* SYS_CON7 */
+#define sysctrl_dbg_seg7_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0xFF000000, n, 24)
+#define sysctrl_dbg_seg6_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0x00FF0000, n, 16)
+#define sysctrl_dbg_seg5_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0x0000FF00, n, 8)
+#define sysctrl_dbg_seg4_sel(n)                       SYSCTRL_REG_SET_VALUE(SYSCTRL->SYS_CON7, 0x000000FF, n, 0)
+
+/* SYS_CON12 */
+#define sysctrl_usb_trim_en(n)                        SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON12, BIT(14))
+#define sysctrl_usb_trim_dis(n)                       SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON12, BIT(14))
+
+/* CLK_CON0 */
+
+
+/* CLK_CON1 */
+#define sysctrl_rf_dac_clk_n_posedge()                SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(31))
+#define sysctrl_rf_dac_clk_n_negedge()                SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(31))
+#define sysctrl_rf_adc_clk_n_posedge()                SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(30))
+#define sysctrl_rf_adc_clk_n_negedge()                SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(30))
+#define sysctrl_rf_adc_sample_clk_n_posedge()         SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(29))
+#define sysctrl_rf_adc_sample_clk_n_negedge()         SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(29))
+ enum dvp_pll_src {
+     DVP_PLL_SRC_XOSC, 
+     DVP_PLL_SRC_SPLL, 
+     DVP_PLL_SRC_UPLL,
+ };
+#define sysctrl_dvp_pll_sel(dvp_pll_src) 		  SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, BIT(28)|BIT(27), dvp_pll_src, 27)
+#define sysctrl_qspi_pll_sel(n)          		  SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, BIT(26), n, 26)
+#define sysctrl_qspi_clk_sel_spll()               do {  SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 &= ~(BIT(3));\
+                                                         SYSCTRL->CLK_CON0 &= ~(BIT(26)); );\
+                                                  } while(0)
+#define sysctrl_qspi_clk_sel_upll()               do {  SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 &= ~(BIT(3));\
+                                                         SYSCTRL->CLK_CON1 |= (BIT(26)); );\
+                                                  } while(0)
+#define sysctrl_qspi_clk_sel_hxosc()              do {  SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 |= (BIT(3));\
+                                                         SYSCTRL->CLK_CON1 &= ~(BIT(26)); );\
+                                                  } while(0)
+#define sysctrl_qspi_clk_sel_rc10m()              do {  SYSCTRL_REG_OPT( SYSCTRL->CLK_CON0 |= (BIT(3));\
+                                                         SYSCTRL->CLK_CON1 |= (BIT(26)); );\
+                                                  } while(0)
+ enum qspi_clk_src {
+     QSPI_CLK_NONE, 
+     QSPI_CLK_USBPLL, 
+     QSPI_CLK_XOSC, 
+     QSPI_CLK_RC10M,
+ };
+#define sysctrl_qspi_clk_src_sel(qspi_clk_src)\
+do {\
+    if (qspi_clk_src & BIT(1))    SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON0, BIT(3));\
+    else                          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON0, BIT(3));\
+    if (qspi_clk_src & BIT(0))    SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON1, BIT(26));\
+    else                          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON1, BIT(26));\
+} while (0)
+
+#define sysctrl_qspi_clk_src_get() (SYSCTRL->CLK_CON0 & BIT(3)) ? ((SYSCTRL->CLK_CON1 & BIT(26)) ? 0x3 : 0x2) : ((SYSCTRL->CLK_CON1 & BIT(26)) ? 0x1 : 0x0);
+
+enum ospi_clk_src {
+   OSPI_CLK_NONE, 
+   OSPI_CLK_USBPLL, 
+   OSPI_CLK_XOSC, 
+   OSPI_CLK_RC10M,
+};
+#define sysctrl_ospi_clk_src_sel(ospi_clk_src)  SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON4, BIT(22)|BIT(21), ospi_clk_src, 21)
+#define sysctrl_ospi_clk_src_get()              ((SYSCTRL->CLK_CON4 & (BIT(22)|BIT(21))) >> 21)
+ 
+#define sysctrl_ospi_clk_en()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON4, BIT(23));
+#define sysctrl_ospi_clk_dis()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON4, BIT(23));
+#define sysctrl_ospi_set_clk_div(n)             SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON4, 0x1f000000, ((n)-1), 24)
+#define sysctrl_ospi_get_clk_div()              ((SYSCTRL->CLK_CON4 & 0x1f000000) >> 24)
+#define sysctrl_ospi_reset()                    SYSCTRL_REG_BITS_S0S1(SYSCTRL->CLK_CON4, BIT(20))
+
+#define sysctrl_audac_reset()                   SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON4, BIT(17))
+#define sysctrl_audac_en()                      SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON4, BIT(17));
+
+#define sysctrl_auadc_reset()                   SYSCTRL_REG_BITS_S0S1(SYSCTRL->CLK_CON4, BIT(16))
+
+
+ enum rfadc_pll_sel {
+     RF_ADC_PLL_80MHZ, 
+     RF_ADC_PLL_40MHZ = 2,
+     RF_ADC_PLL_20MHZ = 3,
+ };
+#define sysctrl_adda_cnt_pr(rfadc_pll_sel)   SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, BIT(25)|BIT(24), rfadc_pll_sel, 24)
+#define sysctrl_apb1_clk_div(n)              SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x00FF0000, n, 16)
+#define sysctrl_apb0_clk_div(n)              SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x0000FF00, n, 8)
+#define sysctrl_mac_clk_sel(n)               SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x000000C0, n, 6)
+#define sysctrl_sys_clk_div(n)               SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON1, 0x0000003F, n, 0)
+
+/* CKL_CON2 */
+#define sysctrl_dvp_clk_open()             SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(31))
+#define sysctrl_dvp_clk_close()            SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(31))
+#define sysctrl_qspi_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(30))
+#define sysctrl_qspi_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(30))
+#define sysctrl_tmr0_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(29))
+#define sysctrl_tmr0_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(29))
+#define sysctrl_test_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(28))
+#define sysctrl_test_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(28))
+#define sysctrl_stmr_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(27))
+#define sysctrl_stmr_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(27))
+#define sysctrl_tmr3_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(26))
+#define sysctrl_tmr3_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(26))
+#define sysctrl_rfdac_clk_open()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(25))
+#define sysctrl_rfdac_clk_close()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(25))
+#define sysctrl_rfadda_clk_open()          SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(24))
+#define sysctrl_rfadda_clk_close()         SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(24))
+#define sysctrl_rf_pclk_open()             SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(23))
+#define sysctrl_rf_pclk_close()            SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(23))
+#define sysctrl_modem_clk_open()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(22))
+#define sysctrl_modem_clk_close()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(22))
+#define sysctrl_mac_clk_open()             SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(21))
+#define sysctrl_mac_clk_close()            SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(21))
+#define sysctrl_sdhc_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(20))
+#define sysctrl_sdhc_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(20))
+#define sysctrl_sddev_clk_open()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(19))
+#define sysctrl_sddev_clk_close()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(19))
+#define sysctrl_usb20_clk_open()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(18))
+#define sysctrl_usb20_clk_close()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(18))
+#define sysctrl_pdm_clk_open()             SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(17))
+#define sysctrl_pdm_clk_close()            SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(17))
+#define sysctrl_simtmr_clk_open()          SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(16))
+#define sysctrl_simtmr_clk_close()         SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(16))
+#define sysctrl_sysaes_clk_open()          SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(15))
+#define sysctrl_sysaes_clk_close()         SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(15))
+#define sysctrl_crc_clk_open()             SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(14))
+#define sysctrl_crc_clk_close()            SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(14))
+#define sysctrl_iis0_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(13))
+#define sysctrl_iis0_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(13))
+#define sysctrl_tmr1_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(12))
+#define sysctrl_tmr1_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(12))
+#define sysctrl_uart1_clk_open()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(11))
+#define sysctrl_uart1_clk_close()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(11))
+#define sysctrl_uart0_clk_open()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(10))
+#define sysctrl_uart0_clk_close()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(10))
+#define sysctrl_tmr2_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(8))
+#define sysctrl_tmr2_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(8))
+#define sysctrl_spi2_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(7))
+#define sysctrl_spi2_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(7))
+#define sysctrl_spi1_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(6))
+#define sysctrl_spi1_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(6))
+#define sysctrl_spi0_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(5))
+#define sysctrl_spi0_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(5))
+#define sysctrl_wdt_clk_open()             SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(3))
+#define sysctrl_wdt_clk_close()            SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(3))
+#define sysctrl_ahb1_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(2))
+#define sysctrl_ahb1_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(2))
+#define sysctrl_ahb0_clk_open()            SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(1))
+#define sysctrl_ahb0_clk_close()           SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(1))
+#define sysctrl_adkey_clk_open()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON2, BIT(0))
+#define sysctrl_adkey_clk_close()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON2, BIT(0))
+
+
+/* CLK_CON3 */
+#define sysctrl_dvp_mclk_div(n)            SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON3, 0xFC000000, n, 26)
+#define sysctrl_cache_en()                 SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(25))
+#define sysctrl_cache_dis()                SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(25))
+#define sysctrl_lmac_fifo_en()             SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(24))
+#define sysctrl_lmac_fifo_dis()            SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(24))
+#define sysctrl_lvd_dbc_clk_en()           SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(23))
+#define sysctrl_lvd_dbc_clk_dis()          SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(23))
+enum lvd_dbc_clk_src {
+    LVD_DEBUNCE_CLK_RC128K, 
+    LVD_DEBUNCE_CLK_XOSC, 
+    LVD_DEBUNCE_CLK_FCLK, 
+    LVD_DEBUNCE_CLK_RC32K,
+};
+#define sysctrl_lvd_dbg_clk_sel(lvd_dbc_clk_src)   SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON3, BIT(22)|BIT(21), lvd_dbc_clk_src, 21) 
+#define sysctrl_sysmonitor_clk_open()              SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(20))
+#define sysctrl_sysmonitor_clk_close()             SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(20))
+#define sysctrl_m2mdma_clk_open()                  SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(19))
+#define sysctrl_m2mdma_clk_close()                 SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(19))
+#define sysctrl_iis1_clk_open()                    SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(18))
+#define sysctrl_iis1_clk_close()                   SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(18))
+#define sysctrl_gmac_clk_open()                    SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(17))
+#define sysctrl_gmac_clk_close()                   SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(17))
+#define sysctrl_rom_clk_open()                     SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(16))
+#define sysctrl_rom_clk_close()                    SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(16))
+#define sysctrl_apb1_clk_open()                    SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(15))
+#define sysctrl_apb1_clk_close()                   SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(15))
+#define sysctrl_mjpeg_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(14))
+#define sysctrl_mjpeg_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(14))
+#define sysctrl_sdio_fifo_open()      		       SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(14))
+#define sysctrl_sdio_fifo_close()                  SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(14))
+#define sysctrl_qspi_pll_div(n)                    SYSCTRL_REG_SET_VALUE(SYSCTRL->CLK_CON3, BIT(13)|BIT(12)|BIT(11), n, 11)
+#define sysctrl_qspi_get_clk_div()                 ((SYSCTRL->CLK_CON3 & 0x00003800) >> 11)
+#define sysctrl_sram10_clk_open()                  SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(10))
+#define sysctrl_sram10_clk_close()                 SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(10))
+#define sysctrl_sram9_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(9))
+#define sysctrl_sram9_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(9))
+#define sysctrl_sram8_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(8))
+#define sysctrl_sram8_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(8))
+#define sysctrl_sram7_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(7))
+#define sysctrl_sram7_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(7))
+#define sysctrl_sram6_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(6))
+#define sysctrl_sram6_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(6))
+#define sysctrl_sram5_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(5))
+#define sysctrl_sram5_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(5))
+#define sysctrl_sram4_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(4))
+#define sysctrl_sram4_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(4))
+#define sysctrl_sram3_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(3))
+#define sysctrl_sram3_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(3))
+#define sysctrl_sram2_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(2))
+#define sysctrl_sram2_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(2))
+#define sysctrl_sram1_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(1))
+#define sysctrl_sram1_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(1))
+#define sysctrl_sram0_clk_open()                   SYSCTRL_REG_SET_BITS(SYSCTRL->CLK_CON3, BIT(0))
+#define sysctrl_sram0_clk_close()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->CLK_CON3, BIT(0))
+
+
+/* CHIP_ID */
+#define sysctrl_get_chip_dcn()                     ((uint16)(SYSCTRL->CHIP_ID >> 16))
+        
+        
+/* SRAM0_PD_CON */         
+#define sysctrl_sram0_pd_exit_cnt(n)               SYSCTRL_REG_SET_VALUE(SYSCTRL->SRAM0_PD_CON, 0x001FF800, n, 11)
+#define sysctrl_sram0_pd_enter_cnt(n)              SYSCTRL_REG_SET_VALUE(SYSCTRL->SRAM0_PD_CON, 0x000007Fe, n, 1)
+#define sysctrl_sram0_hw_pd_en()                   SYSCTRL_REG_SET_BITS(SYSCTRL->SRAM0_PD_CON, BIT(0))
+#define sysctrl_sram0_hw_pd_dis()                  SYSCTRL_REG_CLR_BITS(SYSCTRL->SRAM0_PD_CON, BIT(0))
+
+
+/* IO_MAP */
+
+/* MBIST_CTRL */
+#define sysctrl_get_softreset_pending()        ((SYSCTRL->MBIST_CTRL & BIT(31)))
+#define sysctrl_clr_softreset_pending()        ((SYSCTRL->MBIST_CTRL = 0x80000000))
+
+
+/* EFUSE_CON */
+#define sysctrl_efuse_pwron_init()                 SYSCTRL_REG_SET_BITS(SYSCTRL->EFUSE_CON, BIT(1)|BIT(0))
+
+
+/* SYS_ERR0 */
+
+
+/* SYS_ERR1 */
+
+
+/* HOSC_MNT */
+#define sysctrl_hosc_mnt_high_limit(n)             SYSCTRL_REG_SET_VALUE(SYSCTRL->HOSC_MNT, 0xFFFF0000, n, 16)
+#define sysctrl_hosc_mnt_en()                      SYSCTRL_REG_SET_BITS(SYSCTRL->HOSC_MNT, BIT(15))
+#define sysctrl_hosc_mnt_dis()                     SYSCTRL_REG_CLR_BITS(SYSCTRL->HOSC_MNT, BIT(15))
+#define sysctrl_hosc_lost_pend_clr()               SYSCTRL_REG_SET_BITS(SYSCTRL->HOSC_MNT, BIT(14))
+#define sysctrl_hosc_mnt_low_limit(n)              SYSCTRL_REG_SET_VALUE(SYSCTRL->HOSC_MNT, 0x00003FFF, n, 0)
+
+/* WK_CTRL */
+/* LP_CTRL */
+
+/* MPE0~5 */
+void sysctrl_memory_protect_config(uint32 start_addr, uint32 size, uint8 enable);
+#define sysctrl_get_mem_protect_pending()   ((SYSCTRL->MPE_PND[0] | SYSCTRL->MPE_PND[1] | SYSCTRL->MPE_PND[2]))
+
+/* MODE_REG */
+#define sysctrl_get_buck_cmpfb_sta()              ((SYSCTRL->MODE_REG & BIT(31)))
+#define sysctrl_get_buck_dtmod_index_sta()        ((SYSCTRL->MODE_REG & BIT(30)))
+#define sysctrl_get_buck_ipeaktrimout_sta()       ((SYSCTRL->MODE_REG & BIT(29)))
+#define sysctrl_get_buck_irptrimout_sta()         ((SYSCTRL->MODE_REG & BIT(28)))
+#define sysctrl_get_ft_mode()                     ((SYSCTRL->MODE_REG & BIT(1)))
+#define sysctrl_get_cp_mode()                     ((SYSCTRL->MODE_REG & BIT(0)))
+
+
+/* QSPI_MAP_CTL */    
+#define sysctrl_set_qspi_iomap(iomap)             SYSCTRL_REG_OPT(SYSCTRL->QSPI_MAP_CTL = iomap;);
+#define sysctrl_get_qspi_iomap()                  ((SYSCTRL->QSPI_MAP_CTL))
+
+/* QSPI_ENCDEC_CON0 */  
+#define sysctrl_get_xip_scramble_sta()            (SYSCTRL->QSPI_ENCDEC_CON0 & (BIT(31)))
+#define sysctrl_xip_scramble_disable()            SYSCTRL_REG_OPT( SYSCTRL->QSPI_ENCDEC_CON0 &= ~(BIT(31)); );
+#define sysctrl_xip_scramble_enable()             SYSCTRL_REG_OPT( SYSCTRL->QSPI_ENCDEC_CON0 |= (BIT(31)); );
+#define sysctrl_xip_scramble_toggle()             SYSCTRL_REG_OPT( SYSCTRL->QSPI_ENCDEC_CON0 ^= (BIT(31)); );
+
+/* TRNG */    
+#define sysctrl_get_trng()                        ((SYSCTRL->TRNG))
+
+/* DCRC_TRIM */   
+#define sysctrl_set_dc_trim_init_val(n)           SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x00fc0000, n, 18)
+#define sysctrl_set_dc_trim_range(n)              SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x0003c000, n, 14)
+#define sysctrl_set_dc_trim_step(n)               SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x00003e00, n, 9)
+#define sysctrl_set_dc_trim_1us_prd(n)            SYSCTRL_REG_SET_VALUE(SYSCTRL->DCRC_TRIM, 0x000001fe, n, 1)
+#define sysctrl_dc_trim_en()                      SYSCTRL_REG_SET_BITS(SYSCTRL->DCRC_TRIM, BIT(0))
+#define sysctrl_dc_trim_dis()                     SYSCTRL_REG_CLR_BITS(SYSCTRL->DCRC_TRIM, BIT(0))
+
+
+typedef struct 
+{
+    __IO  uint32 CTRL_CON;     //0x00
+    __IO  uint32 BURST_CON0;   //0x04
+    __IO  uint32 BURST_CON1;   //0x08
+    __IO  uint32 BASE_CON0;    //0x0c
+    __IO  uint32 BASE_CON1;    //0x10
+    __IO  uint32 BASE_CON2;    //0x14
+    __IO  uint32 BASE_CON3;    //0x18
+    __IO  uint32 BASE_CON4;    //0x1c
+    __IO  uint32 BASE_CON5;    //0x20
+    __IO  uint32 BASE_CON6;    //0x24
+    __IO  uint32 BASE_CON7;    //0x28
+    __IO  uint32 FIFO_EN;      //0x2c
+    __IO  uint32 BW_STA_CYCLE; //0x30
+    __IO  uint32 BW_STA_CNT;   //0x34
+    __IO  uint32 FLASH_RD_EN;  //0x38 : 0x20028008
+} SCHED_TypeDef;
+
+#define SCHED                 ((SCHED_TypeDef    *) HG_SCHED_BASE)
+
+
+/* DMA2AHB */
+enum sysctrl_dma2ahb_burst_obj {
+    DMA2AHB_BURST_OBJ_QSPI, 
+    DMA2AHB_BURST_OBJ_OSPI,
+};
+
+/* unit: byte, total memery is pingpong, need x2 */
+enum sysctrl_dma2ahb_burst_size {
+    DMA2AHB_BURST_SIZE_0, 
+    DMA2AHB_BURST_SIZE_16,
+    DMA2AHB_BURST_SIZE_32,
+    DMA2AHB_BURST_SIZE_64,
+};
+
+enum sysctrl_dma2ahb_burst_chanel {
+    DMA2AHB_BURST_CH_LCD_ROTATE_RD , 
+    DMA2AHB_BURST_CH_VPP_IPF_RD ,       /* flash & psram */
+    DMA2AHB_BURST_CH_OSD0_RD    , 
+    DMA2AHB_BURST_CH_LMAC_RX_WR , 
+    DMA2AHB_BURST_CH_LMAC_TX_RD , 
+    DMA2AHB_BURST_CH_LMAC_WAVE_RD  , 
+    DMA2AHB_BURST_CH_LMAC_WAVE_WR  , 
+    DMA2AHB_BURST_CH_GMAC_TX_RD    , 
+
+    DMA2AHB_BURST_CH_SCALE3_Y_WR , 
+    DMA2AHB_BURST_CH_SCALE3_U_WR , 
+    DMA2AHB_BURST_CH_SCALE3_V_WR , 
+    DMA2AHB_BURST_CH_MJPEG1_SCALE2_YUV_WR  , 
+    DMA2AHB_BURST_CH_UNUSED,    
+    DMA2AHB_BURST_CH_MJPEG1_RD  ,       /* flash & psram */
+    DMA2AHB_BURST_CH_MJPEG0_VPP_WR  , 
+    DMA2AHB_BURST_CH_OSD_ENC_RD    , 
+    
+    DMA2AHB_BURST_CH_OSD_ENC_WR    , 
+    DMA2AHB_BURST_CH_LMAC_HDR_RD, 
+    DMA2AHB_BURST_CH_SYSAES_WR  , 
+    DMA2AHB_BURST_CH_SYSAES_RD  ,       /* flash & psram */
+    DMA2AHB_BURST_CH_SHA_RD     ,       /* flash & psram */
+    DMA2AHB_BURST_CH_CRC_RD     ,       /* flash & psram */
+    DMA2AHB_BURST_CH_M2M0_RD    , 
+     /* flash & psram */
+    DMA2AHB_BURST_CH_M2M0_WR    , 
+    
+    DMA2AHB_BURST_CH_M2M1_RD    ,       /* flash & psram */
+    DMA2AHB_BURST_CH_M2M1_WR    , 
+    DMA2AHB_BURST_CH_AUDIO_RD   , 
+    DMA2AHB_BURST_CH_CODEC_RD    , 
+    DMA2AHB_BURST_CH_CODEC_WR    , 
+    DMA2AHB_BURST_CH_SDH_RD     , 
+    DMA2AHB_BURST_CH_SDH_WR     , 
+};
+
+
+/* CTRLCON */
+int32 ll_sysctrl_dma2ahb_burst_set(enum sysctrl_dma2ahb_burst_chanel ch, enum sysctrl_dma2ahb_burst_size size) ;
+
+__STATIC_INLINE void ll_sysctrl_dma2ahb_select(enum sysctrl_dma2ahb_burst_obj obj) {
+    SCHED->CTRL_CON = (SCHED->CTRL_CON & ~(0x1UL << 0)) | ((obj & 0x1) << 0);  
+}
+__STATIC_INLINE void ll_sysctrl_dma2ahb_osd_enc_rd_lmac_wave_rd_priority_switch(uint8 enable) {
+    if (enable) {
+        SCHED->CTRL_CON |= (BIT(4));
+    } else {
+        SCHED->CTRL_CON &= ~(BIT(4));
+    }
+}
+
+__STATIC_INLINE void ll_sysctrl_dma2ahb_pri_switch(uint32 pri) {
+		SCHED->CTRL_CON &= ~(0xfff<<8);
+        SCHED->CTRL_CON |= (pri<<8);
+}
+__STATIC_INLINE void ll_sysctrl_dma2ahb_m2m1_wr_lmac_wave_wr_priority_switch(uint8 enable) {
+    if (enable) {
+        SCHED->CTRL_CON |= (BIT(5));
+    } else {
+        SCHED->CTRL_CON &= ~(BIT(5));
+    }
+}
+
+__STATIC_INLINE void ll_sysctrl_dma2ahb_m2m1_rd_gmac_tx_rd_priority_switch(uint8 enable) {
+    if (enable) {
+        SCHED->CTRL_CON |= (BIT(6));
+    } else {
+        SCHED->CTRL_CON &= ~(BIT(6));
+    }
+}
+
+__STATIC_INLINE int32 ll_sysctrl_dma2ahb_is_busy(enum sysctrl_dma2ahb_burst_chanel ch) {
+    return (SCHED->FIFO_EN & BIT(ch));
+}
+
+__STATIC_INLINE int32 ll_sysctrl_dma2ahb_busy_sta(void) {
+    return SCHED->FIFO_EN;
+}
+
+#define sysctrl_dma2ahb_bw_io_freq_set(hz)  do {SCHED->BW_STA_CYCLE = hz;} while (0)
+#define sysctrl_dma2ahb_bw_calc_en()        do {SCHED->CTRL_CON |= BIT(1);} while (0)
+#define sysctrl_dma2ahb_bw_calc_dis()       do {SCHED->CTRL_CON &= ~ BIT(1);} while (0)
+#define sysctrl_get_dma2ahb_bw_byteps()     (SCHED->BW_STA_CNT)
+#define sysctrl_dma2ahb_bw_is_calc_en()     (SCHED->CTRL_CON & BIT(1))
+
+
+
+/**
+  * @}
+  */
+
+
+
+int32 sys_get_apbclk(void);
+int32 sys_get_sysclk(void);
+int32 sys_set_sysclk(uint32 system_clk);
+
+void mcu_reset(void);
+void mcu_watchdog_timeout(uint8 tmo_sec);
+void mcu_watchdog_timeout_level(uint8 level);
+void mcu_watchdog_irq_request(void *hdl);
+void mcu_watchdog_feed(void);
+#ifdef CONFIG_SLEEP
+void lp_watchdog_timeout(uint8 tmo_sec);
+void lp_watchdog_feed(void);
+#endif
+void system_enter_sleep(void);
+void system_exit_sleep(void);
+
+void sysctrl_cmu_init(void);
+bool sysctrl_cmu_upll_init(void);
+bool sysctrl_cmu_sysclk_set(uint32 clk, bool is_upll);
+#define sysctrl_gmac_clk_sel_clk_from_io()
+
+
+/**
+ * @brief   system_clock_set
+ * @param   clk_hz : clk wish to be set
+ * @retval  OK or ERR
+ * @note    
+ */
+int32 system_clock_set(uint32 clk_hz);
+/**
+* @brief   system_clock_get
+* @retval  system clk_hz
+* @note    this function will get the clock form sotfware temp storage
+*/
+uint32 system_clock_get(void);
+
+/**
+ * @brief   system_clock_get_refresh
+ * @retval  system clk_hz
+ * @note    this function will get the clock form hardware
+ */
+uint32 system_clock_get_refresh(void);
+
+/**
+ * @brief   peripheral_clock_set
+ * @param   peripheral  : HG_Peripheral_Type  
+ * @param   clk_hz      : Peripheral clk_hz
+ * @retval  ok or err
+ * @note    peripheral on same bus apb0/1 clk must be same
+ */
+int32 peripheral_clock_set(HG_Peripheral_Type peripheral, uint32 clk_hz);
+
+/**
+ * @brief   peripheral_clock_get
+ * @param   peripheral  : HG_Peripheral_Type  
+ * @retval  clk_hz
+ */
+uint32 peripheral_clock_get(HG_Peripheral_Type peripheral);
+
+uint16 sysctrl_get_chip_id(void);
+uint32 sysctrl_efuse_get_chip_uuid(uint8* pbuf, uint32 len);
+uint32 sysctrl_efuse_get_aes_key_but_return_crc16(void);
+
+uint32 sysctrl_efuse_validity_get(void);
+
+void sysctrl_efuse_validity_handle(void);
+void sysctrl_efuse_info_show(void);
+
+uint32 sysctrl_efuse_vddi_get(void);
+
+uint32 sysctrl_efuse_tsensor_get(void);
+
+uint32 sysctrl_efuse_vddi_gears_get(void);
+
+uint32 sysctrl_efuse_adda_vref_get(void);
+
+uint32 sysctrl_efuse_aubias_sel_vref100_vdd(void);
+
+uint32 sysctrl_efuse_aubias_sel_vcmau_vdd(void);
+
+uint32 sysctrl_efuse_aubias_sel_vcc27au_vdd(void);
+
+uint32 sysctrl_efuse_audio_en(void);
+
+void sysctrl_rst_lmac_phy(void);
+
+int32 sysctrl_err_resp_disable(void);
+uint8 sysctrl_efuse_get_bios_id(void);
+uint8 sysctrl_efuse_get_module_type(void);
+void system_clocks_show(void);
+void sysctrl_gpio_funcmap_default(void);
+
+void system_goto_boot(void);
+void system_reboot_test_mode(void);
+void system_reboot_normal_mode(void);
+int32 system_is_wifi_test_mode(void);
+void system_qspi_pretect_all(void);
+uint8 get_chip_pack(void);
+uint8 get_bios_id(void);
+
+#define sysctrl_dma_bridge_reset()
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__SYSCTRL_H__
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2019 HUGE-IC *****END OF FILE****/

sdk/include/chip/txw81x/test_atcmd.h

@@ -0,0 +1,76 @@
+#ifndef _TXW81X_TEST_ATCMD_H_
+#define _TXW81X_TEST_ATCMD_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+int32 atcmd_reg_rd_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_reg_wt_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_test_start_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_test_addr_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_temp_en_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_type_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_rf_pwr_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_pha_amp_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_step_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_cont_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_start_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_trig_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_frm_type_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_mcs_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_lo_freq_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_edca_cw_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_edca_aifs_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_edca_txop_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 at_cmd_cfg_rx_agc_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_lmac_print_period_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_bss_bw_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_set_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_set_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 at_cmd_cca_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_rx_cnt_clr_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_rx_cnt_get_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_tx_delay_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_wave_dump_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_write_mac_addr_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_write_tx_dpd_gain_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_write_xosc_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_dbg_level_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 sys_atcmd_reset(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_max_txcnt_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_pcf_en_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_pcf_chn_hdl(const char *cmd, char *argv[], uint32 argc);
+
+#ifdef CONFIG_SLEEP
+int32 atcmd_sleep_dbg_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_sleep_alg_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_sleep_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_dtim_hdl(const char *cmd, char *argv[], uint32 argc);
+#endif    
+
+int32 atcmd_set_tx_timeout_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_set_cca_cert_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_set_srrc_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_start_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_tx_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_rx_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_rx_cnt_clr_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_rx_cnt_get_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_tx_delay_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_chan_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_rx_timeout_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_ble_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_write_ble_tx_gain_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_io_test_hdl(const char *cmd, char *argv[], uint32 argc);
+int32 atcmd_io_test_res_get_hdl(const char *cmd, char *argv[], uint32 argc);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

sdk/include/chip/txw81x/ticker.h

@@ -0,0 +1,52 @@
+#ifndef _TICKER_H_
+#define _TICKER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//#define TIMER0_BASE             (APB1_BASE + 0x5000)
+#define TIMER0                  ((struct hgtimer_v2_hw *) TIMER0_BASE)
+
+
+#define HW_TIMER_PSC        7//HGTIMER_V2_TIMER_PSC_128
+
+/**
+  * @brief  Time(us) to timer tick
+  * @param  n : Time in us
+  * @retval Time(us) to timer tick
+  */
+#define HW_TIMER_T2C(n)         (((n)*(system_clock_get()/1000000)) >> (HW_TIMER_PSC))
+/**
+  * @brief  timer tick to Time(us)
+  * @param  n : timer tick
+  * @retval timer tick to Time(us)
+  */
+#define HW_TIMER_C2T(n)         ((n)*(1 << HW_TIMER_PSC)/(system_clock_get()/1000000))
+
+/**
+  * @brief  The tick timer is initialized.
+  * @param  None
+  * @retval None
+  * @note   Use the lowest priority interrupt.
+  */
+//void hw_timer_init(void);
+
+/**
+  * @brief  get the tick of the timer.
+  * @param  None
+  * @retval None
+  */
+//uint32 hw_timer_get_tick(uint8 start);
+
+/**
+  * @brief  tick timer interrupt handler.
+  * @param  None
+  * @retval None
+  */
+//void hw_timer_irq_handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/chip/txw81x/txw81x.h

@@ -0,0 +1,340 @@
+#ifndef _TXW81X_DEF_H_
+#define _TXW81X_DEF_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+/* Includes ------------------------------------------------------------------*/
+#include "typesdef.h"
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+enum IRQn
+{
+/******  Peripheral Interrupt Numbers *********************************************************/
+    USB20DMA_IRQn               = 0,
+    USB20MC_IRQn                = 1,
+    UART0_IRQn                  = 2,
+    UART1_IRQn                  = 3,
+    LCD_IRQn                    = 4,
+    
+    QSPI_IRQn                   = 5,
+    SPI0_IRQn                   = 6,
+    SPI1_IRQn                   = 7,
+    SPI2_IRQn                   = 8,
+    OSPI_IRQn                   = 9,
+    
+    TIM0_IRQn                   = 10,
+    TIM1_IRQn                   = 11,
+    TIM2_IRQn                   = 12,
+    TIM3_IRQn                   = 13,
+    SCALE1_IRQn                 = 14,
+    
+    AUDIO_SUBSYS0_IRQn          = 15, //ALAW & HS & VAD 
+    AUDIO_SUBSYS1_IRQn          = 16, //ADC
+    AUDIO_SUBSYS2_IRQn          = 17, //DAC
+    SDIO_IRQn                   = 18,
+    SDIO_RST_IRQn               = 19,
+    
+    SDHOST_IRQn                 = 20,
+    LMAC_IRQn                   = 21,
+    GMAC_IRQn                   = 22,
+    M2M0_IRQn                   = 23,
+    M2M1_IRQn                   = 24,
+    
+    CORET_IRQn                  = 25, //CPU TIMER
+    SPACC_PKA_IRQn              = 26, //SHA/SYS_AES 
+    CRC_IRQn                    = 27,
+    ADKEY01_IRQn                = 28,
+    PD_TMR_IRQn                 = 29,
+    
+    WKPND_IRQn                  = 30,
+    PDWKPND_IRQn                = 31,
+    LVD_IRQn                    = 32,
+    WDT_IRQn                    = 33,
+    SYS_ERR_IRQn                = 34,
+    
+    IIS0_IRQn                   = 35,
+    IIS1_IRQn                   = 36,
+    GPIOABCE_IRQn               = 37,
+    //GPIODE_IRQn                 = 38,
+    DVP_IRQn                    = 39,
+    
+    MJPEG01_IRQn                = 40,
+    //CSI2_IRQn                   = 41,
+    VPP_IRQn                    = 42,
+    PRC_IRQn                    = 43,
+    STMR012345_IRQn             = 44,
+    
+    PDM_IRQn                    = 45,
+    LED_TMR_IRQn                = 46,
+    SCALE2_IRQn                 = 47,
+    GFSK_IRQn                   = 48,
+    CMPOUT01_IRQn               = 49,
+    
+    UART45_IRQn                 = 50,
+    SCALE3_IRQn                 = 51,
+    //SPI5_IRQn                   = 52,
+    //SPI6_IRQn                   = 53,
+    //LED_IRQn                    = 54, 
+    
+    //SUPTMR3_IRQn                = 55,
+    //SUPTMR4_IRQn                = 56,
+    //SUPTMR5_IRQn                = 57,
+    USB20PHY_RTC_IRQn           = 58,
+    //TK_IRQn                     = 59,
+    //CPU0_SPINLOCK_IRQn          = 60,
+    //CPU0_SEND_MAIL_IRQn         = 61,
+    //CPU0_RECV_MAIL_IRQn         = 62,
+    //AUDIO_SUBSYS_IRQn           = 63,
+    SHA_VIRTUAL_IRQn             = 64,
+    AES_VIRTUAL_IRQn             = 65,
+    UART4_IRQn                   = 66,
+    UART5_IRQn                   = 67,
+    GPIOA_IRQn					         = 68,
+    GPIOB_IRQn					         = 69,
+    GPIOC_IRQn					         = 70,
+    GPIOE_IRQn					         = 71,
+    AUVAD_IRQn                   = 72,
+    AUHS_IRQn                    = 73,
+    AUALAW_IRQn                  = 74,
+    IRQ_NUM,
+};
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* --------  Configuration of the CK803 Processor and Core Peripherals  ------- */
+#define __CK803_REV               0x0000U   /* Core revision r0p0 */
+#define __MPU_PRESENT             0         /* MGU present or not */
+#define __VIC_PRIO_BITS           3         /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0         /* Set to 1 if different SysTick Config is used */
+
+#include "csi_core.h"                     /* Processor and core peripherals */
+#include "stdint.h"
+
+////////
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE                  ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE                   ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define SRAM_END_ADDR               ((uint32_t)0x20044000) /*!< SRAM end address in the alias region */
+#define PSRAM_BASE                  ((uint32_t)0x38000000) /*!< SRAM base address in the alias region */
+#define PSRAM_END_ADDR              (PSRAM_BASE + 16*1024*1024) /*!< SRAM end address in the alias region */
+#define PERIPH_BASE                 ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+/*!< Peripheral memory map */
+#define APB0_BASE                PERIPH_BASE
+#define APB1_BASE               (PERIPH_BASE + 0x10000)
+#define AHB_BASE                (PERIPH_BASE + 0x20000)
+
+#define QSPI_BASE               (APB0_BASE + 0x0000)
+#define HG_OSPI_BASE            (APB0_BASE + 0x1000)
+#define HG_SCHED_BASE           (APB0_BASE + 0x2000)
+#define HG_UART0_BASE           (APB0_BASE + 0x4000)
+#define HG_UART1_BASE           (APB0_BASE + 0x4100)
+#define HG_UART2_BASE           (APB0_BASE + 0x4200)
+#define HG_UART3_BASE           (APB0_BASE + 0x4300)
+#define HG_UART4_BASE           (APB0_BASE + 0x4b70)
+#define HG_UART5_BASE           (APB0_BASE + 0x4b90)
+#define SPI0_BASE               (APB0_BASE + 0x4400)
+#define SPI1_BASE               (APB0_BASE + 0x4500)
+#define SPI2_BASE               (APB0_BASE + 0x4600)
+#define SPI3_BASE               (APB0_BASE + 0x4700)
+#define SPI4_BASE               (APB0_BASE + 0x4800)
+#define SPI5_BASE               (APB0_BASE + 0x4b20)
+#define SPI6_BASE               (APB0_BASE + 0x4b38)
+#define HG_LED_BASE             (APB0_BASE + 0x4b50)
+#define IIC1_BASE               (APB0_BASE + 0x4500)
+#define IIC2_BASE               (APB0_BASE + 0x4600)
+#define IIC3_BASE               (APB0_BASE + 0x4700)
+#define IIC4_BASE               (APB0_BASE + 0x4800)
+#define HG_IIS0_BASE            (APB0_BASE + 0x80C0)
+#define HG_IIS1_BASE            (APB0_BASE + 0x80E0)
+#define HG_PDM_BASE             (APB0_BASE + 0x8110)
+#define PRC_BASE                (APB0_BASE + 0x5000)
+#define OF_BASE                 (APB0_BASE + 0x5020)
+#define DVP_BASE                (APB0_BASE + 0x5040)
+#define VPP_BASE                (APB0_BASE + 0x5080)
+#define JPG0_BASE               (APB0_BASE + 0x5100)
+#define JPG1_BASE               (APB0_BASE + 0x5200)
+#define MJPEG0_TAB_BASE        (APB0_BASE + 0x5180)
+#define MJPEG1_TAB_BASE        (APB0_BASE + 0x5280)
+#define CSI2_HOST_BASE          (APB0_BASE + 0x5700)
+
+#define TK_BASE                 (APB0_BASE + 0x6000)
+
+#define SCALE0_BASE             (APB0_BASE + 0x7000)
+#define SCALE1_BASE             (APB0_BASE + 0x7100)
+#define LCDC_BASE               (APB0_BASE + 0x7000)
+#define SCALE2_BASE             (APB0_BASE + 0x71A0)
+#define SCALE3_BASE             (APB0_BASE + 0x7200)
+#define AUDIO_BASE              (APB0_BASE + 0x8000)
+
+#define COMP_BASE               (APB0_BASE + 0x9000)
+#define EFUSE_BASE              (APB0_BASE + 0xa000)
+
+#define HG_SYSAES_BASE          (APB1_BASE + 0x2000)
+//#define RFADCDIG_BASE           (APB1_BASE + 0x4000)
+#define HG_SHA_BASE             (APB1_BASE + 0x4000)
+#define WDT_BASE                (APB1_BASE + 0x5000)
+#define TIMER_ALL_BASE          (APB1_BASE + 0x5128)
+#define TIMER0_BASE             (APB1_BASE + 0x5100)
+#define TIMER1_BASE             (APB1_BASE + 0x5200)
+#define TIMER2_BASE             (APB1_BASE + 0x5300)
+#define TIMER3_BASE             (APB1_BASE + 0x5400)
+#define TIMER4_BASE             (APB1_BASE + 0x5500)
+//#define TIMER5_BASE             (APB1_BASE + 0x5600)
+//#define TIMER6_BASE             (APB1_BASE + 0x5700)
+//#define TIMER7_BASE             (APB1_BASE + 0x5800)
+#define SUPTMR_BASE             (APB1_BASE + 0x5600)
+#define SIMPLE_TIMER0_BASE      (APB1_BASE + 0x5B00)
+#define SIMPLE_TIMER1_BASE      (APB1_BASE + 0x5B10)
+#define SIMPLE_TIMER2_BASE      (APB1_BASE + 0x5B20)
+#define SIMPLE_TIMER3_BASE      (APB1_BASE + 0x5B30)
+#define SIMPLE_TIMER4_BASE      (APB1_BASE + 0x5B40)
+#define SIMPLE_TIMER5_BASE      (APB1_BASE + 0x5B50)
+
+
+
+//#define HG_RTC_BASE             (APB1_BASE + 0x8050)
+#define HG_CRC32_BASE           (APB1_BASE + 0x7000)
+#define PMU_BASE                (APB1_BASE + 0x8000)
+#define LVD_BASE                (APB1_BASE + 0x8000)
+#define RFDIG_BASE              (APB1_BASE + 0x9000)
+#define ADKEY_BASE              (APB1_BASE + 0xa000)
+#define ADKEY1_BASE             (APB1_BASE + 0xa00c)
+#define ZH_RFSPI_BASE           (APB1_BASE + 0xb000)
+#define RFDIGCAL_BASE           (APB1_BASE + 0xd000)
+
+#define HG_SYSCTRL_BASE         (AHB_BASE + 0x0000)
+#define HG_GPIOA_BASE           (AHB_BASE + 0x0a00)
+#define HG_GPIOB_BASE           (AHB_BASE + 0x0b00)
+#define HG_GPIOC_BASE           (AHB_BASE + 0x0c00)
+#define HG_GPIOD_BASE           (AHB_BASE + 0x0d00)
+#define HG_GPIOE_BASE           (AHB_BASE + 0x0e00)
+#define HG_GPIOF_BASE           (AHB_BASE + 0x0f00)
+#define HG_GPIOG_BASE           (AHB_BASE + 0x1000)
+#define HG_GPIOH_BASE           (AHB_BASE + 0x1100)
+
+#define M2M_DMA_BASE            (AHB_BASE + 0x1200)
+#define M2M_DMA0_BASE           (AHB_BASE + 0x1200)
+#define M2M_DMA1_BASE           (AHB_BASE + 0x121C)
+#define SYS_MNT_BASE            (AHB_BASE + 0x1300)
+#define SDHOST_BASE             (AHB_BASE + 0x1400)
+#define LED_TIMER0_BASE         (PMU_BASE + 0x000d0)
+#define LED_TIMER1_BASE         (PMU_BASE + 0x000d4)
+#define LED_TIMER2_BASE         (PMU_BASE + 0x000d8)
+#define LED_TIMER3_BASE         (PMU_BASE + 0x000dc)
+
+
+#define HG_SUPTMR_COMM_BASE     (SUPTMR_BASE       )
+#define HG_SUPTMR0_BASE         (APB1_BASE + 0x5B00)
+#define HG_SUPTMR1_BASE         (APB1_BASE + 0x5B10)
+#define HG_SUPTMR2_BASE         (APB1_BASE + 0x5B20)
+#define HG_SUPTMR3_BASE         (APB1_BASE + 0x5B30)
+#define HG_SUPTMR4_BASE         (APB1_BASE + 0x5B40)
+#define HG_SUPTMR5_BASE         (APB1_BASE + 0x5B50)
+
+#define HG_SDIO20_SLAVE_BASE    (AHB_BASE + 0x20000)
+#define MODEM_BASE              (AHB_BASE + 0x40000)
+#define LMAC_BASE               (AHB_BASE + 0x42000)
+#define HG_GMAC_BASE            (AHB_BASE + 0x51000)
+#define HG_USB20_DEVICE_BASE    (AHB_BASE + 0xd0000)
+
+
+typedef enum {
+    HG_AHB_PT_ALL,
+    HG_AHB_PT_GPIOA_DEBUNCE,
+    HG_AHB_PT_GPIOB_DEBUNCE,
+    HG_AHB_PT_GPIOC_DEBUNCE,
+    HG_AHB_PT_M2M_DMA,
+    HG_AHB_PT_SYS_MNT,
+    HG_AHB_PT_SDMMC,
+    HG_AHB_PT_SDIO,
+    HG_AHB_PT_MODEM,
+    HG_AHB_PT_LMAC,
+    HG_AHB_PT_GMAC,
+    HG_AHB_PT_USB20,
+
+    HG_APB0_PT_ALL,
+    HG_APB0_PT_QSPI,
+    HG_APB0_PT_OSPI,    
+    HG_APB0_PT_UART0,
+    HG_APB0_PT_UART1,
+    HG_APB0_PT_UART4,
+    HG_APB0_PT_UART5,
+    HG_APB0_PT_SPI0,
+    HG_APB0_PT_SPI1,
+    HG_APB0_PT_SPI2,
+    HG_APB0_PT_SPI3,
+    HG_APB0_PT_SPI5,
+    HG_APB0_PT_SPI6,
+    HG_APB0_PT_LED,
+    HG_APB0_PT_IIC0,
+    HG_APB0_PT_IIC1,
+    HG_APB0_PT_IIC2,
+    HG_APB0_PT_IIC3,
+    HG_APB0_PT_IIS0,
+    HG_APB0_PT_IIS1,
+    HG_APB0_PT_PDM,
+    HG_APB0_PT_JPEG,
+    HG_APB0_PT_DVP,
+    HG_APB0_PT_CMP,
+    HG_APB0_PT_EFUSE,
+
+    HG_APB1_PT_ALL,
+    HG_APB1_PT_AES,
+    HG_APB1_PT_WDT,
+    HG_APB1_PT_TMR0,
+    HG_APB1_PT_TMR1,
+    HG_APB1_PT_TMR2,
+    HG_APB1_PT_TMR3,
+    HG_APB1_PT_STMR,
+    HG_APB1_PT_SUPTMR,
+    HG_APB1_PT_CRC,
+    HG_APB1_PT_PMU,
+    HG_APB1_PT_LVD,
+    HG_APB1_PT_ADKEY,
+    
+
+    
+} HG_Peripheral_Type;
+    
+
+/**
+  * @}
+  */
+
+enum phy_rf_mode {
+    INT_PHY_EXT_RF_MODE = 1, //for ext-rf case
+    PHY_RF_NORMAL_MODE  = 2, //tx4001 ic normal case
+    INT_RF_EXT_PHY_MODE = 3, //for transceiver case
+};
+
+#define EFUSE_OFFSET       3
+
+#define OSC_CLK     32000000UL
+
+#define M2M_DMA
+
+#define IS_DCACHE_ADDR(addr) ((uint32)(addr) >= 0x38000000 && (uint32)(addr) < 0x38f00000) //psram
+#define IS_PSRAM_ADDR(addr)  ((uint32)(addr) >= 0x38000000 && (uint32)(addr) < 0x38f00000) //psram
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

sdk/include/dev.h

@@ -0,0 +1,99 @@
+#ifndef _HUGEIC_DEV_H_
+#define _HUGEIC_DEV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct dev_obj;
+
+struct devobj_ops{
+#ifdef CONFIG_SLEEP
+    int32 (*suspend)(struct dev_obj *obj);
+    int32 (*resume)(struct dev_obj *obj);
+#endif
+};
+
+#ifndef OS_BLKLIST
+#define OS_BLKLIST
+struct os_blklist{
+    void *hdl;
+};
+#endif
+
+struct dev_obj{
+    uint16 dev_id;
+    uint8  busy; /* device 被使用状态，由驱动代码设置。
+                    有8bit可用，驱动代码根据 read/write/... 设置不同的bit位 */
+    uint8  suspend: 1, /* device进入suspend状态，由dev_suspend API设置 */
+           rev: 7;
+    struct dev_obj *next;
+#ifdef CONFIG_SLEEP
+    struct os_blklist blklist;
+#endif
+    const struct devobj_ops *ops;
+};
+
+#define DEV_BUSY(dev, val, set)      dev_busy((struct dev_obj *)(dev), val, set)
+#define DEV_SUSPENDED(dev, suspend)  dev_suspended((struct dev_obj *)(dev), suspend)
+#define HALDEV_SUSPENDED(dev)        if(dev_suspended((struct dev_obj *)dev, 1)) return RET_ERR
+
+/**
+ * dev core module initialize
+ * @return return RET_OK if initialize sucess, else return RET_ERR.
+ **/
+extern int32 dev_init(void);
+
+/**
+ * get dev by dev_id
+ * @param[in] dev_id device id
+ * @return return device object if device exist, else return NULL.
+ **/
+extern struct dev_obj *dev_get(int32 dev_id);
+
+/*
+* set or clear device busy flag.
+*/
+extern void dev_busy(struct dev_obj *dev, uint8 busy, uint8 set);
+
+/**
+ * register device into dev manager.
+ * @param[in] dev_id device id.
+ * @param[in] device object to register.
+ * @return return RET_OK if register sucess, else return RET_ERR.
+ **/
+extern int32 dev_register(uint32 dev_id, struct dev_obj *device);
+
+/**
+ * unregister device into dev manager.
+ * @param[in] device object to unregister.
+ * @return return RET_OK if register sucess, else return RET_ERR.
+ **/
+extern int32 dev_unregister(struct dev_obj *device);
+
+/* 检查指定的device是否已经被suspend，
+   参数suspend：表示如果device已经被suspend，是否suspend当前task
+*/
+int32 dev_suspended(struct dev_obj *dev, uint8 suspend);
+/**
+ * device suspend when system enter sleep.
+ * @param[in] dsleep sleep or deep sleep.
+ * @return return RET_OK if unregister sucess, else return RET_ERR.
+ **/
+extern int32 dev_suspend(uint16 type);
+extern int32 dev_suspend_hook(struct dev_obj *dev, uint16 type);
+
+/**
+ * device resume when system resume.
+ * @return return RET_OK if unregister sucess, else return RET_ERR.
+ **/
+extern int32 dev_resume(uint16 type, uint32 wkreason);
+extern int32 dev_resume_hook(struct dev_obj *dev, uint16 type, uint32 wkreason);
+
+extern int32 pin_func(int32 dev_id, int32 request);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/adc/hgadc_v0.h

@@ -0,0 +1,61 @@
+#ifndef _HGADC_V0_H
+#define _HGADC_V0_H
+#include "hal/adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hgadc_v0;
+
+typedef struct _adc_channel_data {
+    /* pointer of config function */
+    int32 (*func)(struct hgadc_v0 *dev, uint32 channel, uint32 enable);
+
+    /* channel */
+    uint16 channel;
+}adc_channel_data;
+
+
+typedef struct _adc_channel_node {
+    /* data type */
+    adc_channel_data data;
+
+    /* for list opreation */
+    struct _adc_channel_node *next;
+    
+    /* channel amount */
+    uint8 channel_amount;
+}adc_channel_node;
+
+
+
+struct hgadc_v0 {
+    struct adc_device   dev;
+    uint32              hw;
+    adc_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint32              irq_num;
+    struct os_mutex     adc_lock;
+    struct os_semaphore adc_done;
+    adc_channel_node    head_node;
+    uint32              refer_vddi;
+    uint32              refer_vddi_adc_data;
+    uint32              refer_tsensor;
+    uint32              refer_adda_vref;
+    uint32              rf_vddi_en:1,
+                        opened    :1,
+                        irq_en    :1;
+};
+
+
+
+
+
+int32 hgadc_v0_attach(uint32 dev_id, struct hgadc_v0 *adc);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/audio/components/alaw/aualaw.h

@@ -0,0 +1,181 @@
+#ifndef _AUALAW_H
+#define _AUALAW_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief AUALAW irq_flag type
+  */
+enum aualaw_irq_flag {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUALAW_IRQ_FLAG_HALF = BIT(0),
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUALAW_IRQ_FLAG_FULL = BIT(1),
+};
+
+/**
+  * @brief AUALAW ioctl_cmd type
+  */
+enum aualaw_ioctl_cmd {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUALAW_IOCTL_CMD_NONE,
+};
+
+
+
+/* User interrupt handle */
+typedef void (*aualaw_irq_hdl)(uint32 irq, uint32 irq_data);
+
+/* AUALAW api for user */
+
+struct aualaw_device {
+    struct dev_obj dev;
+};
+
+struct aualaw_hal_ops {
+    struct devobj_ops ops;
+    int32(*open)(struct aualaw_device *aualaw);
+    int32(*close)(struct aualaw_device *aualaw);
+    int32(*encode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
+    int32(*decode)(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
+    int32(*ioctl)(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
+};
+
+
+
+/* AUALAW API functions */
+
+
+
+/**
+ * @brief aualaw_open
+ *
+ *
+ * @note  .
+ *
+ * @param aualaw       The address of aualaw device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aualaw_open(struct aualaw_device *aualaw);
+
+/**
+ * @brief aualaw_close
+ *
+ *
+ * @note  .
+ *
+ * @param aualaw       The address of aualaw device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aualaw_close(struct aualaw_device *aualaw);
+
+/**
+ * @brief aualaw_encode
+ *
+ *
+ * @note  .
+ *
+ * @param aualaw       The address of aualaw device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aualaw_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
+
+/**
+ * @brief aualaw_decode
+ *
+ *
+ * @note  .
+ *
+ * @param aualaw       The address of aualaw device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aualaw_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
+
+/**
+ * @brief aualaw_ioctl
+ *
+ *
+ * @note  .
+ *
+ * @param aualaw       The address of aualaw device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aualaw_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief aualaw_request_irq
+ *
+ *
+ * @note  .
+ *
+ * @param aualaw       The address of aualaw device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aualaw_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
+
+/**
+ * @brief aualaw_release_irq
+ *
+ *
+ * @note  .
+ *
+ * @param aualaw       The address of aualaw device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aualaw_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/audio/components/alaw/hg_aualaw_v0.h

@@ -0,0 +1,22 @@
+#ifndef _HG_AUALAW_V0_H_
+#define _HG_AUALAW_V0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+int32 hg_aualaw_v0_init(void);
+int32 hg_aualaw_v0_open(struct aualaw_device *aualaw);
+int32 hg_aualaw_v0_close(struct aualaw_device *aualaw);
+int32 hg_aualaw_v0_encode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
+int32 hg_aualaw_v0_decode(struct aualaw_device *aualaw, void* dat_buf, uint32 bytes, void* result_buf);
+int32 hg_aualaw_v0_ioctl(struct aualaw_device *aualaw, enum aualaw_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+int32 hg_aualaw_v0_request_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag, aualaw_irq_hdl irq_hdl, uint32 irq_data);
+int32 hg_aualaw_v0_release_irq(struct aualaw_device *aualaw, enum aualaw_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGI2S_V0_H_ */

sdk/include/dev/audio/components/eq/aueq.h

@@ -0,0 +1,126 @@
+#ifndef _AUEQ_H
+#define _AUEQ_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+  * @brief AUEQ ioctl_cmd type
+  */
+enum aueq_ioctl_cmd {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUEQ_IOCTL_CMD_NONE,
+};
+
+
+/*!
+ * @brief coefficient configuration
+ * @note
+ *     a example of coefficient for 5 band:
+ *     struct aueq_cfg cfg[5];
+ *     cfg[0].b[0] = 0.1;
+ *     cfg[0].b[1] = 0.3;
+ *     ...
+ *     cfg[1].b[1] = 0.6;
+ */
+struct aueq_cfg{
+  double b[3];
+  double a[2];
+};
+
+
+/* AUEQ api for user */
+
+struct aueq_device {
+    struct dev_obj dev;
+};
+
+struct aueq_hal_ops {
+    struct devobj_ops ops;
+    int32(*open)(struct aueq_device *aueq, struct aueq_cfg *p_cfg);
+    int32(*close)(struct aueq_device *aueq);
+    int32(*run)(struct aueq_device *aueq, void* dat_buf, uint32 bytes);
+    int32(*ioctl)(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+};
+
+
+
+/* AUEQ API functions */
+
+
+
+/**
+ * @brief aueq_open
+ *
+ *
+ * @note  .
+ *
+ * @param aueq       The address of aueq device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aueq_open(struct aueq_device *aueq, struct aueq_cfg *p_cfg);
+
+/**
+ * @brief aueq_close
+ *
+ *
+ * @note  .
+ *
+ * @param aueq       The address of aueq device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aueq_close(struct aueq_device *aueq);
+
+/**
+ * @brief aueq_encode
+ *
+ *
+ * @note  .
+ *
+ * @param aueq       The address of aueq device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aueq_run(struct aueq_device *aueq, void* dat_buf, uint32 bytes);
+
+
+/**
+ * @brief aueq_ioctl
+ *
+ *
+ * @note  .
+ *
+ * @param aueq       The address of aueq device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aueq_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/audio/components/eq/biquad_filter.h

@@ -0,0 +1,59 @@
+#ifndef BIQUAD_FILTER_H
+#define BIQUAD_FILTER_H
+
+
+typedef int						s32, S32;
+typedef unsigned int			u32, U32, uint;
+typedef long long int			s64, S64;
+typedef unsigned long long		u64, U64;
+typedef short int               s16, S16;
+typedef unsigned short int      u16, U16;
+typedef signed char             s8, S8;
+typedef unsigned char           u8, U8;
+
+//模拟64bit芯片运算
+int CLIP_INT24(int in);
+int CLIP_INT16(int in);
+void ML0(s32 x, s32 y);
+void MLA(s32 x, s32 y);
+void MSB(s32 x, s32 y);
+s32 MLZ(s32 n);
+s32 MLZ_QUICK(s32 n);
+s32 MLZ_FIX(s32 n);
+u32 get_acc_64_high_32(void);
+u32 get_acc_64_low_32(void);
+
+
+
+typedef struct {
+    int b[3];
+    int a[2];
+    int x[2];
+    int y[2];
+    int fixed_point_num;
+} TYPE_BIQUAD_FILTER;
+
+int biquad_filter_calc(TYPE_BIQUAD_FILTER *filter_ctl, int x);
+//void biquad_filter_ctl_init(TYPE_BIQUAD_FILTER *filter_ctl, int fixed_point_num);
+
+#if 0
+void eq_lpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                         double fs, double f0, double q);
+void eq_hpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                         double fs, double f0, double q);
+void eq_bpf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                         double fs, double f0, double q);
+void eq_notch_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                           double fs, double f0, double q);
+void eq_apf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                         double fs, double f0, double q);
+void eq_peaking_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                             double fs, double f0, double gain, double q);
+void eq_low_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                               double fs, double f0, double gain, double q);
+void eq_high_shelf_coeff_calc(TYPE_BIQUAD_FILTER *filter_ctl,
+                                double fs, double f0, double gain, double q);
+#endif
+
+#endif /* BIQUAD_FILTER_H */
+

sdk/include/dev/audio/components/eq/hg_aueq_v0.h

@@ -0,0 +1,19 @@
+#ifndef _HG_AUEQ_V0_H_
+#define _HG_AUEQ_V0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+int32 hg_aueq_v0_init(void);
+int32 hg_aueq_v0_open(struct aueq_device *aueq, struct aueq_cfg *p_cfg);
+int32 hg_aueq_v0_close(struct aueq_device *aueq);
+int32 hg_aueq_v0_run(struct aueq_device *aueq, void* dat_buf, uint32 bytes);
+int32 hg_aueq_v0_ioctl(struct aueq_device *aueq, enum aueq_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HG_AUEQ_V0_H_ */

sdk/include/dev/audio/components/fade/aufade.h

@@ -0,0 +1,192 @@
+#ifndef _AUFADE_H
+#define _AUFADE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+  * @brief AUFADE calculate mode types
+  */
+enum aufade_mode {
+	AUFADE_IN  = BIT(0),
+	
+	AUFADE_OUT = BIT(1),
+};
+
+/**
+ * @brief AUFADE step types
+ */
+enum aufade_step {
+  AUFADE_STEP_1,
+
+  AUFADE_STEP_2,
+
+  AUFADE_STEP_4,
+
+  AUFADE_STEP_8,
+};
+
+/**
+ * @brief AUFADE sample types
+ */
+enum aufade_sample {
+  AUFADE_SAMPLE_1,
+
+  AUFADE_SAMPLE_2,
+
+  AUFADE_SAMPLE_3,
+
+  AUFADE_SAMPLE_4,
+};
+
+/**
+  * @brief AUFADE irq_flag type
+  */
+enum aufade_irq_flag {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUFADE_IRQ_FLAG_NONE = BIT(0),
+};
+
+/**
+  * @brief AUFADE ioctl_cmd type
+  */
+enum aufade_ioctl_cmd {
+
+	AUFADE_IOCTL_CMD_SET_STEP = BIT(0),
+
+  AUFADE_IOCTL_CMD_SET_SAMPLE = BIT(1),
+};
+
+
+
+/* User interrupt handle */
+typedef void (*aufade_irq_hdl)(uint32 irq, uint32 irq_data);
+
+/* AUFADE api for user */
+
+struct aufade_device {
+    struct dev_obj dev;
+};
+
+struct aufade_hal_ops {
+    struct devobj_ops ops;
+    int32(*open)(struct aufade_device *aufade);
+    int32(*close)(struct aufade_device *aufade);
+    int32(*start)(struct aufade_device *aufade, enum aufade_mode mode);
+    int32(*ioctl)(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
+};
+
+
+
+/* AUFADE API functions */
+
+
+
+/**
+ * @brief aufade_open
+ *
+ *
+ * @note  .
+ *
+ * @param aufade       The address of aufade device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aufade_open(struct aufade_device *aufade);
+
+/**
+ * @brief aufade_close
+ *
+ *
+ * @note  .
+ *
+ * @param aufade       The address of aufade device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aufade_close(struct aufade_device *aufade);
+
+/**
+ * @brief aufade_start
+ *
+ *
+ * @note  .
+ *
+ * @param aufade       The address of aufade device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aufade_start(struct aufade_device *aufade, enum aufade_mode mode);
+
+/**
+ * @brief aufade_ioctl
+ *
+ *
+ * @note  .
+ *
+ * @param aufade       The address of aufade device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aufade_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief aufade_request_irq
+ *
+ *
+ * @note  .
+ *
+ * @param aufade       The address of aufade device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aufade_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
+
+/**
+ * @brief aufade_release_irq
+ *
+ *
+ * @note  .
+ *
+ * @param aufade       The address of aufade device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 aufade_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/audio/components/fade/hg_aufade_v0.h

@@ -0,0 +1,23 @@
+#ifndef _HG_AUFADE_V0_H_
+#define _HG_AUFADE_V0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dev/audio/components/fade/aufade.h"
+#include "hg_audio_v0_hw.h"
+
+int32 hg_aufade_v0_init(void);
+int32 hg_aufade_v0_open(struct aufade_device *aufade);
+int32 hg_aufade_v0_close(struct aufade_device *aufade);
+int32 hg_aufade_v0_start(struct aufade_device *aufade, enum aufade_mode mode);
+int32 hg_aufade_v0_ioctl(struct aufade_device *aufade, enum aufade_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+int32 hg_aufade_v0_request_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag, aufade_irq_hdl irq_hdl, uint32 irq_data);
+int32 hg_aufade_v0_release_irq(struct aufade_device *aufade, enum aufade_irq_flag irq_flag);
+int32 hg_aufade_v0_set_gain(struct hg_audio_hw_v0 *audio_hw, uint32 gain);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HG_AUFADE_V0_H_ */

sdk/include/dev/audio/components/vad/auvad.h

@@ -0,0 +1,203 @@
+#ifndef _AUVAD_H
+#define _AUVAD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+  * @brief AUVAD calculate mode types
+  */
+enum auvad_calc_mode {
+	AUVAD_CALC_MODE_ENERGY = BIT(0),
+	
+	AUVAD_CALC_MODE_ZCR    = BIT(1),
+};
+
+
+/**
+  * @brief AUVAD irq_flag type
+  */
+enum auvad_irq_flag {
+
+    /*!
+     * @brief:
+     * 
+     */
+    NONE = BIT(0),
+};
+
+/**
+  * @brief AUVAD ioctl_cmd type
+  */
+enum auvad_ioctl_cmd {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUVAD_IOCTL_CMD_SET_CALC_MODE,
+
+	/*!
+     * @brief:
+     * 
+     */
+    AUVAD_IOCTL_CMD_SET_THRESHOLD_TH0,
+    
+	/*!
+     * @brief:
+     * 
+     */
+    AUVAD_IOCTL_CMD_SET_THRESHOLD_TH1,
+    
+	/*!
+     * @brief:
+     * 
+     */
+    AUVAD_IOCTL_CMD_SET_THRESHOLD_ZCR,
+};
+
+
+
+/* User interrupt handle */
+typedef void (*auvad_irq_hdl)(uint32 irq, uint32 irq_data);
+
+/* AUVAD api for user */
+
+struct auvad_device {
+    struct dev_obj dev;
+};
+
+struct auvad_hal_ops {
+    struct devobj_ops ops;
+    int32(*open)(struct auvad_device *auvad, enum auvad_calc_mode mode);
+    int32(*close)(struct auvad_device *auvad);
+    int32(*calc)(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
+    int32(*ioctl)(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
+};
+
+
+
+/* AUVAD API functions */
+
+
+
+/**
+ * @brief auvad_open
+ *
+ *
+ * @note  .
+ *
+ * @param auvad       The address of auvad device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auvad_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
+
+/**
+ * @brief auvad_close
+ *
+ *
+ * @note  .
+ *
+ * @param auvad       The address of auvad device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auvad_close(struct auvad_device *auvad);
+
+/**
+ * @brief auvad_encode
+ *
+ *
+ * @note  .
+ *
+ * @param auvad       The address of auvad device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auvad_encode(struct auvad_device *auvad, void* dat_buf, uint32 bytes, void* result_buf);
+
+/**
+ * @brief auvad_decode
+ *
+ *
+ * @note  .
+ *
+ * @param auvad       The address of auvad device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auvad_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
+
+/**
+ * @brief auvad_ioctl
+ *
+ *
+ * @note  .
+ *
+ * @param auvad       The address of auvad device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auvad_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief auvad_request_irq
+ *
+ *
+ * @note  .
+ *
+ * @param auvad       The address of auvad device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auvad_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
+
+/**
+ * @brief auvad_release_irq
+ *
+ *
+ * @note  .
+ *
+ * @param auvad       The address of auvad device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auvad_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/audio/components/vad/hg_auvad_v0.h

@@ -0,0 +1,21 @@
+#ifndef _HG_AUVAD_V0_H_
+#define _HG_AUVAD_V0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+int32 hg_auvad_v0_init(void);
+int32 hg_auvad_v0_open(struct auvad_device *auvad, enum auvad_calc_mode mode);
+int32 hg_auvad_v0_close(struct auvad_device *auvad);
+int32 hg_auvad_v0_calc(struct auvad_device *auvad, void* dat_buf, uint32 bytes, uint32 calc_type, void* result_buf);
+int32 hg_auvad_v0_ioctl(struct auvad_device *auvad, enum auvad_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+int32 hg_auvad_v0_request_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag, auvad_irq_hdl irq_hdl, uint32 irq_data);
+int32 hg_auvad_v0_release_irq(struct auvad_device *auvad, enum auvad_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HG_AUVAD_V0_H_ */

sdk/include/dev/audio/hg_auadc_v0.h

@@ -0,0 +1,21 @@
+#ifndef _HG_AUADC_V0_H_
+#define _HG_AUADC_V0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+int32 hg_auadc_v0_init(struct auadc_device *auadc);
+int32 hg_auadc_v0_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
+int32 hg_auadc_v0_close(struct auadc_device *auadc);
+int32 hg_auadc_v0_read(struct auadc_device *auadc, void* buf, uint32 bytes);
+int32 hg_auadc_v0_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+int32 hg_auadc_v0_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
+int32 hg_auadc_v0_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGI2S_V0_H_ */

sdk/include/dev/audio/hg_audac_v0.h

@@ -0,0 +1,22 @@
+#ifndef _HG_AUDAC_V0_H_
+#define _HG_AUDAC_V0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32 hg_audac_v0_init(struct audac_device *audac);
+int32 hg_audac_v0_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
+int32 hg_audac_v0_close(struct audac_device *audac);
+int32 hg_audac_v0_write(struct audac_device *audac, void* buf, uint32 bytes);
+int32 hg_audac_v0_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+int32 hg_audac_v0_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
+int32 hg_audac_v0_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGI2S_V0_H_ */

sdk/include/dev/audio/hg_audio_v0.h

@@ -0,0 +1,73 @@
+#ifndef _HG_AUDIO_V0_H_
+#define _HG_AUDIO_V0_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * Type of device
+ */
+#define AUDIO_TYPE_AUADC    BIT(0)
+#define AUDIO_TYPE_AUDAC    BIT(1)
+#define AUDIO_TYPE_AUHS     BIT(2)
+#define AUDIO_TYPE_AUVAD    BIT(3)
+#define AUDIO_TYPE_AUALAW   BIT(4)
+#define AUDIO_TYPE_AUFADE   BIT(5)
+#define AUDIO_TYPE_AUEQ     BIT(6)
+
+
+
+/** @brief AUDIO operating handle structure
+  * @{
+  */
+
+
+/*!
+ * Common dat areas struct
+ */
+union __comm_dat{
+    uint32 comm;
+    struct {
+        uint32  adc_en      		:1,
+                dac_en      		:1,
+                hs_en       		:1,
+                alaw_en         	:1,
+                vad_en          	:1,
+                aufade_en           :1,
+                eq_en               :1,
+				ana_power_on    	:1,
+				ana_power_adc_on	:1,
+				ana_power_dac_on	:1;
+    } comm_bits;
+};
+
+struct hg_audio_v0 {
+    /* Pointer of device */
+    struct dev_obj      dev;
+    
+    uint32              hw;
+
+    /* common areas */
+    union __comm_dat    comm_dat;
+    /* Pointer of common areas */
+    void               *p_comm; 
+
+    void               *irq_hdl;
+    uint32              irq_data;
+    uint16              irq_num;
+
+    /* Type of device */
+    uint16              dev_type;
+};
+
+
+int32 hg_audio_v0_attach(uint32 dev_id, struct hg_audio_v0 *audio);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGI2S_V0_H_ */

sdk/include/dev/capture/hgcapture_v0.h

@@ -0,0 +1,53 @@
+#ifndef _HGCAPTURE_V0_H
+#define _HGCAPTURE_V0_H
+#include "hal/capture.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define HGCAPTURE_MAX_CAPTURE_CHANNEL 4
+
+enum hgcapture_v0_func_cmd {
+    HGCAPTURE_V0_FUNC_CMD_MASK                  = BIT(7),
+    HGCAPTURE_V0_FUNC_CMD_INIT                  = HGCAPTURE_V0_FUNC_CMD_MASK | 1,
+    HGCAPTURE_V0_FUNC_CMD_DEINIT                = HGCAPTURE_V0_FUNC_CMD_MASK | 2,
+    HGCAPTURE_V0_FUNC_CMD_START                 = HGCAPTURE_V0_FUNC_CMD_MASK | 3,
+    HGCAPTURE_V0_FUNC_CMD_STOP                  = HGCAPTURE_V0_FUNC_CMD_MASK | 4,
+    /* IOCTL CMD */
+
+    /* IRQ_FLAG */
+    HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE   = HGCAPTURE_V0_FUNC_CMD_MASK | 5,
+    HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW  = HGCAPTURE_V0_FUNC_CMD_MASK | 6,
+    
+    HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ           = HGCAPTURE_V0_FUNC_CMD_MASK | 7,
+
+    HGCAPTURE_V0_FUNC_CMD_SUSPEND               = HGCAPTURE_V0_FUNC_CMD_MASK | 8,
+    HGCAPTURE_V0_FUNC_CMD_RESUME                = HGCAPTURE_V0_FUNC_CMD_MASK | 9,
+};
+
+struct hgcapture_v0_config {
+    uint32           irq_data;
+    capture_irq_hdl  irq_hdl;
+    uint16           func_cmd;
+    /* Only for config REG in lower layer code */
+    uint16           cap_sel:1, 
+                     cap_pol:1;
+};
+
+struct hgcapture_v0 {
+    struct capture_device  dev;
+    void                  *channel[HGCAPTURE_MAX_CAPTURE_CHANNEL];
+    uint8                  opened[HGCAPTURE_MAX_CAPTURE_CHANNEL];
+};
+
+
+
+int32 hgcapture_v0_attach(uint32 dev_id, struct hgcapture_v0 *capture);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/crc/hg_crc.h

@@ -0,0 +1,30 @@
+#ifndef _HG_CRC_H_
+#define _HG_CRC_H_
+#include "hal/crc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hg_crc {
+    struct crc_dev          dev;
+    void                   *hw;
+
+    struct os_mutex         lock;
+    struct os_semaphore     done;
+    uint32                  irq_num;
+    uint32                  flags;
+
+#ifdef CONFIG_SLEEP
+    uint32                 *regs;
+#endif
+};
+
+int32 hg_crc_attach(uint32 dev_id, struct hg_crc *crc_c);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HG_CRC_H_ */
+

sdk/include/dev/csi/hgdvp.h

@@ -0,0 +1,46 @@
+#ifndef HG_DVP_H
+#define HG_DVP_H
+#include "tx_platform.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/dvp.h"
+
+#ifdef TXW80X
+typedef enum {
+	HSIE_ISR     = 0,
+	VSIE_ISR,
+	SSCIE_EIGHT_ISR,
+	FHFIE_ISR,
+	FOVIE_ISR,
+	SIP_ISR,
+	JPEG_DONE,
+	DVP_IRQ_NUM
+}DVP_IRQ_E;
+#endif
+
+#ifdef TXW81X
+typedef enum {
+	FOVIE_ISR = 0,
+	SII_ISR,	
+	DVP_IRQ_NUM
+}DVP_IRQ_E;
+	
+#endif
+ 
+
+struct hgdvp {
+    struct dvp_device   dev;
+    //struct hgdvp_hw     *hw;
+	uint32              hw;
+    dvp_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint32              irq_num;
+    uint32              opened:1, use_dma:1, dsleep:1;
+	uint32 *cfg_backup;
+};
+
+
+int32 hgdvp_attach(uint32 dev_id, struct hgdvp *dvp);
+
+#endif
+

sdk/include/dev/dma/dw_dmac.h

@@ -0,0 +1,387 @@
+#ifndef _DW_DMAC_H_
+#define _DW_DMAC_H_
+
+#include "hal/dma.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! max dmac hardware channel
+ */
+#define DW_DMAC_MAX_DMAC_CHN                    4
+/*! max dmac hardware channel mask
+ */
+#define DW_DMAC_MAX_DMAC_CHN_MASK               0xF
+
+/**
+  * @brief DMAC controller (IP)
+  */
+struct dw_dmac_hw_ch {
+    __IO uint32 SARL;
+    __IO uint32 SARH;
+    __IO uint32 DARL;
+    __IO uint32 DARH;
+    __IO uint32 FIFO0[2];     //LLPL,LLPH, NO USE
+    __IO uint32 CTLL;
+    __IO uint32 CTLH;
+    __IO uint32 FIFO1[8];     //SSTATL,SSTATH,DSTATL,DSTATH,SSTATARL,SSTATARH,DSTATARL,DSTATARH
+    __IO uint32 CFGL;
+    __IO uint32 CFGH;
+    __IO uint32 SGRL;
+    __IO uint32 SGRH;
+    __IO uint32 DSRL;
+    __IO uint32 DSRH;
+};
+    
+/**
+  * @brief DMAC
+  */
+struct hgdma_dw_hw {
+    struct dw_dmac_hw_ch CH[4];
+    __IO uint32        FIFO0[22*4];
+    __IO uint32        RawTfrL;
+    __IO uint32        RawTfrH;
+    __IO uint32        RawBlockL;
+    __IO uint32        RawBlockH;
+    __IO uint32        RawSrcTranL;
+    __IO uint32        RawSrcTranH;
+    __IO uint32        RawDstTranL;
+    __IO uint32        RawDstTranH;
+    __IO uint32        RawErrL;
+    __IO uint32        RawErrH;
+    __IO uint32        FIFO1[5*2];
+    __IO uint32        MaskTfrL;
+    __IO uint32        MaskTfrH;
+    __IO uint32        MaskBlockL;
+    __IO uint32        MaskBlockH;
+    __IO uint32        MaskSrcTranL;
+    __IO uint32        MaskSrcTranH;
+    __IO uint32        MaskDstTranL;
+    __IO uint32        MaskDstTranH;
+    __IO uint32        MaskErrL;
+    __IO uint32        MaskErrH;
+    __IO uint32        ClearTfrL;
+    __IO uint32        ClearTfrH;
+    __IO uint32        ClearBlockL;
+    __IO uint32        ClearBlockH;
+    __IO uint32        ClearSrcTranL;
+    __IO uint32        ClearSrcTranH;
+    __IO uint32        ClearDstTranL;
+    __IO uint32        ClearDstTranH;
+    __IO uint32        ClearErrL;
+    __IO uint32        ClearErrH;
+    __IO uint32        FIFO2[2];
+    __IO uint32        ReqSrcRegL;
+    __IO uint32        ReqSrcRegH;
+    __IO uint32        ReqDstRegL;
+    __IO uint32        ReqDstRegH;
+    __IO uint32        SglReqSrcRegL;
+    __IO uint32        SglReqSrcRegH;
+    __IO uint32        SglReqDstRegL;
+    __IO uint32        SglReqDstRegH;
+    __IO uint32        LstSrcRegL;
+    __IO uint32        LstSrcRegH;
+    __IO uint32        LstDstRegL;
+    __IO uint32        LstDstRegH;
+    __IO uint32        DmaCfgRegL;
+    __IO uint32        DmaCfgRegH;
+    __IO uint32        ChEnRegL;
+    __IO uint32        ChEnRegH;
+    __IO uint32        FIFO3[2];
+    __IO uint32        DmaTestRegL;
+    __IO uint32        DmaTestRegH;
+};
+
+struct hgdma_dw {
+    struct dma_device      dev;
+    struct hgdma_dw_hw   *hw;
+    uint32               irq_num;
+    uint32               opened;
+    struct os_semaphore  mem_chn;
+    struct os_semaphore  dev_chn;
+    struct os_mutex      dev_mutex;
+    dma_irq_hdl          irq_hdl[DW_DMAC_MAX_DMAC_CHN];
+    uint32               irq_data[DW_DMAC_MAX_DMAC_CHN];
+    uint32               state[DW_DMAC_MAX_DMAC_CHN];
+    uint32               chn_used_flag;
+};
+
+/** @brief DW DMAC register constant table definition
+  * @{
+  */
+
+/***** DW_PARAMS Register *****/
+/*! number of channels
+ */
+#define DW_DMAC_PARAMS_NR_CHAN                  4
+/*! number of AHB masters
+ */
+#define DW_DMAC_PARAMS_NR_MASTER                2
+
+
+/***** DWC_PARAMS Register *****/
+/*! multi block transfer
+ */
+#define DW_DMACC_PARAMS_MBLK_EN                 11
+
+
+/***** CTLx Register *****/
+/*! irqs enabled
+ */
+#define DW_DMAC_CTLL_INT_EN                     (1UL << 0)
+/*! The size of each element of destination transmission.
+ */
+#define DW_DMAC_CTLL_DST_WIDTH(n)               (((n)&0x7) << 1)
+/*! The size of each element of source transmission.
+ */
+#define DW_DMAC_CTLL_SRC_WIDTH(n)               (((n)&0x7) << 4)
+/*! Indicates destination address how to change on every source transfer.
+ */
+#define DW_DMAC_CTLL_DST_DIR(n)                 (((n)&0x3) << 7)
+/*! Indicates source address how to change on every source transfer.
+ */
+#define DW_DMAC_CTLL_SRC_DIR(n)                 (((n)&0x3) << 9)
+/*! Number of data items to be written to de destination every time. 
+ */
+#define DW_DMAC_CTLL_DST_MSIZE(n)               (((n)&0x7) << 11)
+/*! Number of data items to be read from the source every time. 
+ */
+#define DW_DMAC_CTLL_SRC_MSIZE(n)               (((n)&0x7) << 14)
+/*! src gather
+ */
+#define DW_DMAC_CTLL_S_GATH_EN                  (1UL << 17)
+/* dst scatter 
+ */
+//#define DW_DMAC_CTLL_D_SCAT_EN                (1UL << 18)
+/*! Transfer type and flow control.
+ */
+#define DW_DMAC_CTLL_FC(n)                      (((n)&0x7) << 20)
+/*! dst master select : 1 for memory, 0 for peripherals
+ */
+#define DW_DMAC_CTLL_DMS(n)                     (((n)&0x3) << 23)
+/*! src master select : 1 for memory, 0 for peripherals
+ */
+#define DW_DMAC_CTLL_SMS(n)                     (((n)&0x3) << 25)
+/* dest block chain 
+ */
+//#define DW_DMAC_CTLL_LLP_D_EN                   (1UL << 27)
+/* src block chain 
+ */
+//#define DW_DMAC_CTLL_LLP_S_EN                   (1UL << 28)
+
+
+/***** CTL_HI Register *****/
+/*! Block transfer done
+ */
+#define DW_DMAC_CTLH_DONE                       (0x00001000)
+/*! Block transfer size. The max block size is 4095.
+ */
+#define DW_DMAC_CTLH_BLOCK_TS_MASK              (0x00000FFF)
+
+
+/***** CFG_LO Register *****/
+/*! Channel priority mask
+ */
+#define DW_DMAC_CFGL_CH_PRIOR_MASK              (0x7UL << 5)
+/*! Channel priority
+ */
+#define DW_DMAC_CFGL_CH_PRIOR(n)                (((n)&0x7) << 5)
+/*! Channle Suspend. Suspends all DMA data transfers from the source until this
+ *  bit is cleared.
+ */
+#define DW_DMAC_CFGL_CH_SUSP                    (1UL << 8)
+/*! Indicates if there is data left in the channel FIFO.
+ */
+#define DW_DMAC_CFGL_FIFO_EMPTY                 (1UL << 9)
+/*! Destination software or hardware handshaking select.
+ */
+#define DW_DMAC_CFGL_HS_DST                     (1UL << 10)
+/*! Source software or hardware handshaking select.
+ */
+#define DW_DMAC_CFGL_HS_SRC                     (1UL << 11)
+//#define DW_DMAC_CFGL_LOCK_CH_LEVEL(n)           (((n)&0x3) << 12)
+//#define DW_DMAC_CFGL_LOCK_BUS_LEVEL(n)          (((n)&0x3) << 14)
+//#define DW_DMAC_CFGL_LOCK_CH                    (1UL << 16)
+//#define DW_DMAC_CFGL_LOCK_BUS                   (1UL << 17)
+/*! Destination handshaking interface polarity.
+ */
+#define DW_DMAC_CFGL_HS_DST_POL                 (1UL << 18)
+/*! Source handshaking interface polarity.
+ */
+#define DW_DMAC_CFGL_HS_SRC_POL                 (1UL << 19)
+/*! Maximum AMBA burst length that is used for DMA transfers on this channel.
+ */
+#define DW_DMAC_CFGL_MAX_BURST(n)               (((n)&0x2FF) << 20)
+/*! Automatic source reload.
+ */
+#define DW_DMAC_CFGL_RELOAD_SAR                 (1UL << 30)
+/*! Automatic desination reload.
+ */
+#define DW_DMAC_CFGL_RELOAD_DAR                 (1UL << 31)
+
+
+/***** CFG_HI Register *****/
+/*! Flow control mode.
+ */
+#define DW_DMAC_CFGH_FCMODE                     (1UL << 0)
+/*! FIFO mode select.
+ */
+#define DW_DMAC_CFGH_FIFO_MODE                  (1UL << 1)
+/*! Protection control.
+ */
+#define DW_DMAC_CFGH_PROTCTL(n)                 (((n)&0x7) << 2)
+//#define DW_DMAC_CFGH_DS_UPD_EN                  (1UL << 5)
+//#define DW_DMAC_CFGH_SS_UPD_EN                  (1UL << 6)
+/*! Assigns a hardware handshaking interface to the source of channel.
+ */
+#define DW_DMAC_CFGH_SRC_PER(n)                 (((n)&0xF) << 7)
+/*! Assigns a hardware handshaking interface to the destination of channel.
+ */
+#define DW_DMAC_CFGH_DST_PER(n)                 (((n)&0xF) << 11)
+
+
+/***** SGR Register *****/
+/*! Source gather interval.
+ */
+#define DW_DMAC_SGR_SGI(n)                      (((n)&0xFFFFF) << 0)
+/*! Source gather count.
+ */
+#define DW_DMAC_SGR_SGC(n)                      (((n)&0xF) << 20)
+
+
+/***** DSR Register *****/
+//#define DW_DMAC_DSR_DSI(x)                      (((n)&0xFFFFF) << 0)
+//#define DW_DMAC_DSR_DSC(x)                      (((n)&0xF) << 20)
+
+
+/***** DmaCfgReg Register *****/
+/*! dmac enable.
+ */
+#define DW_DMAC_CFG_DMA_EN                      (1UL << 0)
+
+/***** ChEnRegL/MaskTfrL/MaskErrL/MaskDstTranL/MaskSrcTranL/MaskBlockL/ Register *****/
+/*! Source gather count.
+ */
+#define DW_DMAC_WRITE_EN(n)                     ((1 << (n+8)) | (1 << n))
+/*! Source gather count.
+ */
+#define DW_DMAC_WRITE_DIS(n)                    (1 << (n+8))
+
+#define DW_DMAC_XFER_DONE(n)                    (1 << (n))
+#define DW_DMAC_XFER_ERR(n)                     (1 << (n+8))
+
+
+/**
+  * @}
+  */
+
+/** @brief DW DMAC external constant definition
+  * @{
+  */
+
+/**
+  * @breif Number of data items to be transferred(of width TR_WIDTH)
+  */
+enum dw_dmac_msize {
+    /*! damc data width : 1 TR_WIDTH
+     */
+    DW_DMAC_MSIZE_1,
+    /*! damc data width : 4 TR_WIDTH
+     */
+
+    DW_DMAC_MSIZE_4,
+    /*! damc data width : 8 TR_WIDTH
+     */
+    DW_DMAC_MSIZE_8,
+    // The following MSIZE is not supported.
+//    DW_DMAC_MSIZE_16,
+//    DW_DMAC_MSIZE_32,
+//    DW_DMAC_MSIZE_64,
+//    DW_DMAC_MSIZE_128,
+//    DW_DMAC_MSIZE_256,
+};
+
+/**
+  * @brief The size of each element of destination transmission. The unit is bit.
+  */
+enum dw_dmac_tr_width {
+    /*! damc xfer width : 8 bit
+     */
+    DW_DMAC_TR_8,
+    /*! damc xfer width : 16bit
+     */
+    DW_DMAC_TR_16,
+    /*! damc xfer width : 32bit
+     */
+    DW_DMAC_TR_32,
+    // The following TR_WIDTH is not supported.0
+//    DW_DMAC_TR_64,
+//    DW_DMAC_TR_128,
+//    DW_DMAC_TR_256,
+};
+
+/**
+  * @brief Indicates destination address how to change on every source transfer.
+  */
+enum dw_dmac_addr_dir {
+    /*! Increment
+     */
+    DW_DMAC_ADDR_INC,
+    /*! Decrement
+     */
+    DW_DMAC_ADDR_DEC,
+    /*! No change
+     */
+    DW_DMAC_ADDR_NO_CHANGE,
+};
+
+/**
+  * @breif flow controller
+@verbatim   
+-------------------------------------------------------------------------------
+CTLL.TT_FC Field        Transfer Type                   Flow Controller    
+-------------------------------------------------------------------------------
+      000               Memory to Memory                DW_anb_dmac
+      001               Memory to Peripheral            DW_anb_dmac
+      010               Peripheral to Memory            DW_anb_dmac
+      011               Peripheral to Peripheral        DW_anb_dmac
+      100               Peripheral to Memory            Peripheral
+      101               Peripheral to Peripheral        Source Peripheral
+      110               Memory to Peripheral            Peripheral
+      111               Peripheral to Peripheral        Destination Peripheral
+@endverbatim
+  */
+enum dw_dmac_fc {
+    /*! Memory to Memory
+     */
+    DW_DMAC_FC_D_M2M,
+    /*! Memory to Peripheral
+     */
+    DW_DMAC_FC_D_M2P,
+    /*! Peripheral to Memory
+     */
+    DW_DMAC_FC_D_P2M,
+    /*! Peripheral to Peripheral
+     */
+    DW_DMAC_FC_D_P2P,
+    // The following flow control is not supported.
+//  DW_DMAC_FC_P_P2M,
+//  DW_DMAC_FC_SP_P2P,
+//  DW_DMAC_FC_P_M2P,
+//  DW_DMAC_FC_DP_P2P,
+};
+
+/**
+  * @}
+  */
+
+int32 dw_dmac_search_src_id(uint32 addr);
+int32 dw_dmac_search_dest_id(uint32 addr);
+int32 dw_dmac_attach(uint32 dev_id, struct hgdma_dw *dmac);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/dma/hg_m2m_dma.h

@@ -0,0 +1,78 @@
+#ifndef _HG_M2M_DMA_H_
+#define _HG_M2M_DMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HG_M2M_DMA_NUM              2
+    
+/** 
+  * @brief  M2M_DMA
+  */
+struct mem_dma_ch {
+    __IO uint32 DMA_CON;
+    __IO uint32 DMA_SAIE;
+    __IO uint32 DMA_DATA;
+    __IO uint32 DMA_SADR;
+    __IO uint32 DMA_TADR;
+    __IO uint32 DMA_DLEN;
+#ifdef TXW81X
+    __IO uint32 DMA_ISIZE;
+#endif
+};
+
+struct mem_dma_hw {
+    struct mem_dma_ch dma_ch[HG_M2M_DMA_NUM];
+};
+
+struct mem_dma_dev {
+    struct dma_device  dev;
+    struct mem_dma_hw  *hw;
+    uint32             irq_num;
+    uint32             busy_flag   : 8,
+                       dma1_status : 1,
+                       dma1_mutex  : 1,
+                       suspend    : 1,
+                       reserved    : 21;
+
+    struct os_semaphore done[HG_M2M_DMA_NUM];
+                       
+};
+
+
+/** @brief M2M DMA register constant table definition
+  * @{
+  */
+
+/***** DMA_CON *****/
+#define HG_M2M_DMA_CON_ENDIAN_SET(n)        ((n) << 3)
+#define HG_M2M_DMA_CON_ENDIAN_RES           (3UL << 3)
+#define HG_M2M_DMA_CON_BLKCPY               (2UL << 1)
+#define HG_M2M_DMA_CON_MEMSET               (1UL << 1)
+#define HG_M2M_DMA_CON_MEMCPY               (0UL << 1)
+#define HG_M2M_DMA_CON_DTE                  (1UL << 0)
+
+/***** DMA_SAIE *****/
+#define HG_M2M_DMA_SAIE_TCIE                (1UL << 16)
+#define HG_M2M_DMA_SAIE_TCP_PENDING         (1UL << 0)
+
+/***** DMA_ISIZE *****/
+#define HG_M2M_DMA_ISZIE_DST_WIDTH(n)       ((n) << 16)
+#define HG_M2M_DMA_ISZIE_SRC_WIDTH(n)       ((n) << 0)
+
+/***** DMA_DLEN *****/
+#define HG_M2M_DMA_DLEN_BLK_HEIGHT(n)       ((n) << 20)
+#define HG_M2M_DMA_DLEN_BLK_WIDTH(n)        ((n) << 0)
+
+/**
+  * @}
+  */
+
+int32 hg_m2m_dma_dev_attach(uint32 dev_id, struct mem_dma_dev *p_dma);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/emac/hg_gmac_eva_v2.h

@@ -0,0 +1,92 @@
+#ifndef _HG_GMAC_EVA_V2_H_
+#define _HG_GMAC_EVA_V2_H_
+
+#include "osal/task.h"
+#include "lib/net/ethphy/eth_phy.h"
+#include "hal/netdev.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define gmac_v2_dbg(fmt, ...)               os_printf(fmt, ##__VA_ARGS__)
+
+struct hg_gmac_data_v2 {
+    struct hg_gmac_v2_rx_descriptor volatile  *p_rx_des;
+    struct hg_gmac_v2_tx_descriptor volatile  *p_tx_des;
+
+    uint8                                  *p_rx_malloc;
+    uint8                                  *p_tx_malloc;
+    
+    /*! In order not to splicing buf, the buf of the last RX descriptor
+     *  should be able to fill one frame.
+     */
+    /*!
+     *      struct hg_gmac_v2_tx_descriptor  rx_des[rx_des_num];
+     *      uint8                         rx_buf[rx_des_num-1][HG_GMAC_V2_RX_PER_BUF_SIZE];
+     *      uint8                         last_rx_buf[HG_GMAC_V2_RX_FRAME_MAX_SIZE];
+     */
+    uint32                                  rx_des_num;
+    struct hg_gmac_v2_rx_descriptor        *p_rx_des_buf;
+
+    uint8                                  *p_rx_buf;
+    /*!
+     *      struct hg_gmac_v2_tx_descriptor  tx_des[tx_des_num];
+     *      uint8                         tx_buf[tx_des_num][HG_GMAC_V2_TX_PER_BUF_SIZE];
+     */
+    uint32                                  tx_des_num;
+    struct hg_gmac_v2_tx_descriptor        *p_tx_des_buf;
+    uint8                                  *p_tx_buf;
+};
+
+struct hg_gmac_eva_v2_statistics {
+    uint32                          tx_cnt;
+    uint32                          rx_cnt;
+    uint32                          ru_pending_cnt;
+    uint32                          rx_err_cnt;
+};
+
+struct hg_gmac_eva_v2 {
+    struct netdev                   dev;
+    uint32                          hw;
+    uint32                          modbus_devid,
+                                    phy_devid,
+                                    crc_devid;
+    struct crc_dev                 *crcdev;
+    uint32                          mdio_pin;
+    uint32                          mdc_pin;
+    uint32                          irq_num;
+    uint32                          opened;
+	uint32 							rgmii_en;
+    struct hg_gmac_data_v2          ctrl_data;
+    uint8                           mac_addr[6];
+    netdev_input_cb                 input_cb;
+    void                           *input_priv;
+    uint32                          tx_buf_size;
+    uint32                          rx_buf_size;
+    struct os_task                  receive_task;
+    struct ethernet_phy_device     *phydev;
+    struct ethernet_mdio_bus       *mdio_bus;
+    
+    /* Save link information */
+    int32                           speed;
+    int32                           duplex;
+    int32                           link_status;
+    
+    struct os_semaphore             receive_sema;
+    struct os_mutex                 mdio_mutex;
+    struct os_mutex                 send_mutex;
+    
+    struct hg_gmac_eva_v2_statistics statistics;
+};
+
+
+int32 hg_gmac_v2_attach(uint32 dev_id, struct hg_gmac_eva_v2 *gmac);
+int32 hg_gmac_v2_has_received_frame(struct netdev *ndev);
+int32 hg_gmac_v2_receive_data(struct netdev *emac_dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/gpio/hggpio_v3.h

@@ -0,0 +1,28 @@
+#ifndef _HUGEIC_GPIO_V3_H_
+#define _HUGEIC_GPIO_V3_H_
+#include "hal/gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HGGPIO_V3_MAX_PINS            (16)
+
+struct hggpio_v3 {
+    struct gpio_device dev;
+    uint32 hw;
+    int32 pin_id[HGGPIO_V3_MAX_PINS];
+    gpio_irq_hdl irq_hdl[HGGPIO_V3_MAX_PINS];
+    uint32 pin_num[2];
+    uint8 irq_num;
+};
+
+int32 hggpio_v3_attach(uint32 dev_id, struct hggpio_v3 *gpio);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+

sdk/include/dev/gpio/hggpio_v4.h

@@ -0,0 +1,57 @@
+#ifndef _HUGEIC_GPIO_V4_H_
+#define _HUGEIC_GPIO_V4_H_
+#include "hal/gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HGGPIO_V4_MAX_PINS            (16)
+
+struct gpio_bk{
+    __IO uint32_t MODE;
+    __IO uint32_t OTYPE;
+    __IO uint32_t OSPEEDL;
+    __IO uint32_t OSPEEDH;
+    __IO uint32_t PUPL;
+    __IO uint32_t PUPH;
+    __IO uint32_t PUDL;
+    __IO uint32_t PUDH;
+    __IO uint32_t ODAT;
+    __IO uint32_t AFRL;
+    __IO uint32_t AFRH;
+    __IO uint32_t IMK;
+    __IO uint32_t DEBEN;
+    __IO uint32_t AIOEN;
+    __IO uint32_t TRG0;
+    __IO uint32_t IEEN;
+    __IO uint32_t IOFUNCOUTCON0;
+    __IO uint32_t IOFUNCOUTCON1;
+    __IO uint32_t IOFUNCOUTCON2;
+    __IO uint32_t IOFUNCOUTCON3;
+};
+
+struct hggpio_v4 {
+    struct gpio_device dev;
+    uint32 hw;
+	uint32 comm_irq_num;
+    int32 pin_id[HGGPIO_V4_MAX_PINS];
+    gpio_irq_hdl irq_hdl[HGGPIO_V4_MAX_PINS];
+    uint32 pin_num[2];
+    uint8 irq_num;
+    uint32_t flag;
+#ifdef CONFIG_SLEEP
+    struct gpio_bk       bk;
+#endif    
+};
+
+
+int32 hggpio_v4_attach(uint32 dev_id, struct hggpio_v4 *gpio);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+

sdk/include/dev/i2c/hgi2c.h

@@ -0,0 +1,59 @@
+/**
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HGI2C_H
+#define __HGI2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+struct hgi2c {
+    struct i2c_device       dev;
+    uint32                  hw;
+    i2c_irq_hdl             irq_hdl;
+    uint32                  irq_data;
+    uint32                  irq_num;
+    struct os_mutex         i2c_lock;
+    struct os_semaphore     i2c_done;
+    uint32                  irq_tx_done_en: 1,
+                            irq_rx_done_en: 1,
+                            flag_tx_done  : 1,
+                            flag_rx_done  : 1,
+                            opened        : 1,
+                            dsleep        : 1;
+#ifdef CONFIG_SLEEP
+            struct {
+                uint32 con0;
+                uint32 con1;
+                uint32 baud;
+                uint32 tdmalen;
+                uint32 rdmalen;
+                uint32 tstadr;
+                uint32 rstadr;
+                uint32 slavesta;
+                uint32 ssp_dly;
+            }bp_regs;
+            uint32               bp_irq_flags;
+            i2c_irq_hdl          bp_irq_hdl;
+            uint32               bp_irq_data;
+            struct os_mutex      bp_suspend_lock;
+            struct os_mutex      bp_resume_lock;
+#endif
+
+}; 
+
+
+
+int32 hgi2c_attach(uint32 dev_id, struct hgi2c *hgi2c_s);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif //__HGI2C_H
+
+/*************************** (C) COPYRIGHT 2018 HUGE-IC ***** END OF FILE *****/

sdk/include/dev/i2c/hgi2c_v1.h

@@ -0,0 +1,64 @@
+/**
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __HGI2C_V1_H
+#define __HGI2C_V1_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+struct hgi2c_v1 {
+    struct i2c_device       dev;
+    uint32                  hw;
+    i2c_irq_hdl             irq_hdl;
+    uint32                  irq_data;
+    uint32                  irq_num;
+    struct os_mutex         i2c_lock;
+    struct os_semaphore     i2c_done;
+    uint32                  irq_tx_done_en: 1,
+                            irq_rx_done_en: 1,
+                            flag_tx_done  : 1,
+                            flag_rx_done  : 1,
+                            opened        : 1,
+                            dsleep        : 1;
+#ifdef CONFIG_SLEEP
+            struct {
+				__IO uint32_t con0;
+				__IO uint32_t con1;
+				__IO uint32_t timecon;
+				__IO uint32_t tdmalen;
+				__IO uint32_t rdmalen;
+				__IO uint32_t tstadr;
+				__IO uint32_t rstadr;
+				__IO uint32_t slavesta;
+				__IO uint32_t ownadrcon;
+				__IO uint32_t timeoutcon;
+				__IO uint32_t rxtimeoutcon;
+				__IO uint32_t rstadr1;
+				__IO uint32_t vsync_tcon;
+				__IO uint32_t hsync_tcon;
+            }bp_regs;
+            uint32               bp_irq_flags;
+            i2c_irq_hdl          bp_irq_hdl;
+            uint32               bp_irq_data;
+            struct os_mutex      bp_suspend_lock;
+            struct os_mutex      bp_resume_lock;
+#endif
+
+}; 
+
+
+
+int32 hgi2c_v1_attach(uint32 dev_id, struct hgi2c_v1 *hgi2c_s);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif //__HGI2C_V1_H
+
+/*************************** (C) COPYRIGHT 2018 HUGE-IC ***** END OF FILE *****/

sdk/include/dev/i2s/hgi2s_v0.h

@@ -0,0 +1,49 @@
+#ifndef _HGI2S_V0_H_
+#define _HGI2S_V0_H_
+#include "hal/i2s.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/** @brief I2S operating handle structure
+  * @{
+  */
+struct hgi2s_v0 {
+    struct i2s_device   dev      ;
+    uint32              hw       ;
+    i2s_irq_hdl         irq_hdl  ;
+    uint32              irq_data ;
+    uint16              irq_num  ;
+    uint16              opened   :1,
+                        dsleep   :1,
+                        duplex_en:1;
+#ifdef CONFIG_SLEEP
+    struct {
+        uint32 con;
+        uint32 bit_set;
+        uint32 baud;
+        uint32 ws_con;
+        uint32 dma_stadr;
+        uint32 dma_len;
+    }bp_regs;
+    uint32               bp_irq_flags;
+    i2s_irq_hdl          bp_irq_hdl;
+    uint32               bp_irq_data;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+};
+
+
+int32 hgi2s_v0_attach(uint32 dev_id, struct hgi2s_v0 *i2s);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGI2S_V0_H_ */

sdk/include/dev/jpg/hgjpg.h

@@ -0,0 +1,67 @@
+#ifndef HG_JPG_H
+#define HG_JPG_H
+#include "hal/jpeg.h"
+//typedef int (*jgp_isr_func)(uint32);
+//typedef int32 (*jpg_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param);
+
+
+#ifdef TXW80X
+typedef enum {
+	DONE_IRQ,
+	JPG_OUTBUF_FULL,
+	JPG_BUF_ERR,
+	
+//	JPG_READ_EMPTY,	
+//	JPG_WRITE_FULL,
+	JPG_IRQ_NUM
+}JPG_IRQ_E;
+#endif
+
+#ifdef TXW81X
+typedef enum {
+	DONE_IRQ,
+	JPG_OUTBUF_FULL,
+	JPG_BUF_ERR,
+	JPG_PIXEL_DONE,
+
+//	JPG_READ_EMPTY,	
+//	JPG_WRITE_FULL,
+	JPG_IRQ_NUM
+}JPG_IRQ_E;
+#endif
+
+
+struct hgjpg {
+    struct jpg_device       dev;
+	uint32              hw;
+	uint32              thw;
+    //jpg_irq_hdl             irq_hdl;
+    uint32              irq_num;
+  	uint32              opened    :1,
+                        init    :1,
+						dsleep:	1;
+	int32  addr_count;
+	uint32 *cfg_backup;
+};
+
+//int32 jpg_open(struct jpg_device *p_jpg);
+//int32 jpg_close(struct jpg_device *p_jpg);
+//int32 jpg_init(struct jpg_device *p_jpg,uint32 table_index,uint32 qt,uint32 buflen,uint32 head_reserver);
+//int32 jpg_set_size(struct jpg_device *p_jpg,uint32 h,uint32 w);
+//int32 jpg_set_len(struct jpg_device *p_jpg,uint32 buflen,uint32 head_reserver);
+//int32 jpg_updata_dqt(struct jpg_device *p_jpg,uint32* dqtbuf);
+//int32 jpg_set_addr(struct jpg_device *p_jpg,uint32 addr);
+//int32 jpg_set_qt(struct jpg_device *p_jpg,uint32 qt);
+//int32 jpg_get_len(struct jpg_device *p_jpg);
+//int32 jpg_get_outbuf_num(struct jpg_device *p_jpg);
+//int32 jpg_request_irq(struct jpg_device *p_jpg,uint32 irq, jgp_isr_func isr, void *dev_id);
+//int32 jpg_release_irq(struct jpg_device *p_jpg,uint32 irq);
+void hgjpg_attach(uint32 dev_id, struct hgjpg *jpg);
+
+
+
+
+
+
+
+#endif

sdk/include/dev/lcdc/hglcdc.h

@@ -0,0 +1,29 @@
+#ifndef HG_LCDC_H
+#define HG_LCDC_H
+#include "tx_platform.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/lcdc.h"
+
+
+typedef enum {
+	LCD_DONE_IRQ,
+	LCD_TE_IRQ,
+	OSD_EN_IRQ,
+	TIMEOUT_IRQ,
+	LCD_IRQ_NUM
+}LCD_IRQ_E;
+
+
+struct hglcdc {
+    struct lcdc_device   dev;
+	uint32              hw;
+    lcdc_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint32              irq_num;
+    uint32              opened:1, use_dma:1, dsleep:1;
+	uint32 *cfg_backup;
+};
+int32 hglcdc_attach(uint32 dev_id, struct hglcdc *lcdc);
+#endif
+

sdk/include/dev/led/hgled_v0.h

@@ -0,0 +1,28 @@
+#ifndef _HGLED_V0_H
+#define _HGLED_V0_H
+#include "hal/led.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hgled_v0 {
+    struct led_device   dev;
+    uint32              hw;
+    led_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint32              irq_num;
+    uint16              seg_cnt;
+    uint16              com_cnt;
+    uint32              tube_type;
+    uint32              opened;
+};
+
+
+int32 hgled_v0_attach(uint32 dev_id, struct hgled_v0 *led);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/of/hgof.h

@@ -0,0 +1,18 @@
+#ifndef HG_OF_H
+#define HG_OF_H
+#include "tx_platform.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/of.h"
+
+
+struct hgof {
+    struct of_device   dev;
+	uint32              hw;
+    uint32              irq_data;
+    uint32              irq_num;
+    uint32              opened:1, use_dma:1;
+};
+
+void hgof_attach(uint32 dev_id, struct hgof *of);
+#endif

sdk/include/dev/pdm/hgpdm_v0.h

@@ -0,0 +1,41 @@
+#ifndef _HGPDM_V0_H_
+#define _HGPDM_V0_H_
+#include "hal/pdm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+struct hgpdm_v0 {
+    struct pdm_device   dev;
+    uint32              hw;
+    pdm_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint16              irq_num;
+    uint16              opened:1,
+                        dsleep:1;
+#ifdef CONFIG_SLEEP
+    struct {
+        uint32 con;
+        uint32 dmacon;
+        uint32 dmastadr;
+        uint32 dmalen;
+    }bp_regs;
+    uint32               bp_irq_flags;
+    pdm_irq_hdl          bp_irq_hdl;
+    uint32               bp_irq_data;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+};
+
+
+int32 hgpdm_v0_attach(uint32 dev_id, struct hgpdm_v0 *pdm);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/dev/prc/hgprc.h

@@ -0,0 +1,29 @@
+#ifndef HG_PRC_H
+#define HG_PRC_H
+#include "tx_platform.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/prc.h"
+
+typedef enum {
+	PRC_ISR = 0,
+	PRC_IRQ_NUM,
+}PRC_IRQ_E;
+ 
+
+struct hgprc {
+    struct prc_device   dev;
+    //struct hgdvp_hw     *hw;
+	uint32              hw;
+    prc_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint32              irq_num;
+    uint32              opened:1, use_dma:1, dsleep:1;
+	uint32 *cfg_backup;
+};
+
+
+void hgprc_attach(uint32 dev_id, struct hgprc *prc);
+
+#endif
+

sdk/include/dev/pwm/hgpwm_v0.h

@@ -0,0 +1,58 @@
+#ifndef _HGPWM_V0_H
+#define _HGPWM_V0_H
+#include "hal/pwm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define HGPWM_MAX_PWM_CHANNEL 6
+
+enum hgpwm_v0_func_cmd {
+    HGPWM_V0_FUNC_CMD_MASK                                     = BIT(6),
+    HGPWM_V0_FUNC_CMD_INIT                                     = HGPWM_V0_FUNC_CMD_MASK | 1,
+    HGPWM_V0_FUNC_CMD_DEINIT                                   = HGPWM_V0_FUNC_CMD_MASK | 2,
+    HGPWM_V0_FUNC_CMD_START                                    = HGPWM_V0_FUNC_CMD_MASK | 3,
+    HGPWM_V0_FUNC_CMD_STOP                           		   = HGPWM_V0_FUNC_CMD_MASK | 4,
+    /* IOCTL CMD */
+    HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY          	       = HGPWM_V0_FUNC_CMD_MASK | 5,
+    HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY          		   = HGPWM_V0_FUNC_CMD_MASK | 6,
+    HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM                 = HGPWM_V0_FUNC_CMD_MASK | 7,
+    HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE               = HGPWM_V0_FUNC_CMD_MASK | 8,
+    HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER                      = HGPWM_V0_FUNC_CMD_MASK | 14,
+    HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY        = HGPWM_V0_FUNC_CMD_MASK | 15,
+    /* IRQ_FLAG */
+    HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE                      = HGPWM_V0_FUNC_CMD_MASK | 9,
+    HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD                       = HGPWM_V0_FUNC_CMD_MASK | 10,
+
+    HGPWM_V0_FUNC_CMD_RELEASE_IRQ                              = HGPWM_V0_FUNC_CMD_MASK | 11,
+
+    HGPWM_V0_FUNC_CMD_SUSPEND                                  = HGPWM_V0_FUNC_CMD_MASK | 12,
+    HGPWM_V0_FUNC_CMD_RESUME                                   = HGPWM_V0_FUNC_CMD_MASK | 13,
+};
+
+struct hgpwm_v0_config {
+    uint32       period;
+    uint32       duty;
+    pwm_irq_hdl  irq_hdl;
+    uint32       irq_data;
+    uint32       func_cmd;
+	uint32       param1;
+	uint32       param2;
+};
+
+struct hgpwm_v0 {
+    struct pwm_device  dev;
+    void              *channel[HGPWM_MAX_PWM_CHANNEL];
+    uint8              opened[HGPWM_MAX_PWM_CHANNEL];
+};
+
+
+
+int32 hgpwm_v0_attach(uint32 dev_id, struct hgpwm_v0 *pwm);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/rtc/hgrtc_v0.h

@@ -0,0 +1,38 @@
+#ifndef _HGRTC_V1_H
+#define _HGRTC_V1_H
+#include "hal/rtc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+struct hgrtc_v0 {
+    struct rtc_device    dev;
+    uint32               hw;
+    rtc_irq_hdl          irq_hdl;
+    uint32               irq_data;
+    uint32               irq_num;
+    struct os_mutex      os_lock_set_time;
+    struct os_mutex      os_lock_get_time;
+    struct rtc_time_type time;
+    struct {
+        //1：闰年；0：平年
+        uint8  leap_year;
+    }time_ctrl;
+    
+    uint8                irq_second:1,
+                         opened    :1;
+};
+
+
+
+int32 hgrtc_v0_attach(uint32 dev_id, struct hgrtc_v0 *rtc);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/scale/hgscale.h

@@ -0,0 +1,30 @@
+#ifndef HG_SCALE_H
+#define HG_SCALE_H
+#include "tx_platform.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/scale.h"
+
+typedef enum {
+	FRAME_END,
+	INBUF_OV,
+	SCALE_IRQ_NUM
+}SCALE_IRQ_E;
+ 
+
+struct hgscale {
+    struct scale_device   dev;
+	uint32              hw;
+    scale_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint32              irq_num;
+    uint32              opened:1, use_dma:1, dsleep:1;
+	uint32 *cfg_backup;
+};
+
+
+int32 hgscale1_attach(uint32 dev_id, struct hgscale *scale);
+int32 hgscale2_attach(uint32 dev_id, struct hgscale *scale);
+int32 hgscale3_attach(uint32 dev_id, struct hgscale *scale);
+
+#endif

sdk/include/dev/sdio/hgsdio20_slave.h

@@ -0,0 +1,36 @@
+#ifndef _HGSDIO20_SLAVE_H_
+#define _HGSDIO20_SLAVE_H_
+#include "hal/sdio_slave.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hgsdio20_slave {
+    struct sdio_slave dev;
+    void  *hw;
+    sdio_slave_irq_hdl irq_hdl;
+    uint32 irq_data;
+    struct os_mutex tx_lock;
+    struct os_semaphore tx_done;
+    uint8 *rx_buff;
+
+    uint8  irq_num;
+    uint8  rst_irq_num;
+    uint8  flags;
+    uint8  opened: 1, rev: 7;
+
+    uint16 rx_len;
+    uint8  speed, rev2;
+    uint8  func0_cis[17];
+    uint8  func1_cis[53];
+};
+
+int32 hgsdio20_slave_attach(uint32 dev_id, struct hgsdio20_slave *slave);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGSDIO20_SLAVE_H_ */
+

sdk/include/dev/sha/hgsha_v0.h

@@ -0,0 +1,43 @@
+#ifndef _HGSHA_V0_H_
+#define _HGSHA_V0_H_
+#include "hal/sha.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+struct hgsha_v0 {
+    struct sha_dev      dev;
+    void                *hw;
+    struct os_mutex     lock;
+    struct os_semaphore done;
+    uint32              irq_hw_num;
+    uint32              irq_num;
+    uint32              alg_type;
+    uint8               buf[64];
+    unsigned long long  bit_len;
+    uint32              buf_cnt;
+    uint32              blk_size;
+    void *              task;
+    void *              usr_p;
+    volatile uint32     flags_intr_busy      :1,
+                        flags_intr_handing   :1,
+                        flags_intr_revs      :30;
+
+    volatile uint32     flags_mod_started    :1,
+                        flags_got_result     :1,
+                        flags_redir_result   :1,
+                        flags_revs           :29;
+#ifdef CONFIG_SLEEP
+    uint32 hash[8];
+#endif
+    // volatile uint32     ;
+    void (*sha_irq_func)(void *args);
+    void *irq_func_data;
+};
+
+int32 hgsha_v0_attach(uint32 dev_id, struct hgsha_v0 *sha);
+
+#endif /* _hgsha256_H_ */

sdk/include/dev/spi/hgic_sdspi.h

@@ -0,0 +1,15 @@
+#ifndef _HGIC_SDSPI_H_
+#define _HGIC_SDSPI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32 hgic_sdspi_attach(uint32 dev_id, uint32 spi_dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

sdk/include/dev/spi/hgspi_v1.h

@@ -0,0 +1,57 @@
+#ifndef _HGSPI_V1_H_
+#define _HGSPI_V1_H_
+#include "hal/spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hgspi_v1 {
+    struct spi_device       dev;
+    uint32                  hw;
+    uint32                  irq_num;
+    spi_irq_hdl             irq_hdl;
+    uint32                  irq_data;
+    //struct os_mutex         os_spi_tx_lock;
+    //struct os_mutex         os_spi_rx_lock;
+    struct os_mutex         os_spi_lock;
+    struct os_semaphore     os_spi_tx_done;
+    struct os_semaphore     os_spi_rx_done;
+    uint32                  timeout;
+    uint16                  len_threshold;
+    uint16                  spi_tx_done          :1,
+                            spi_rx_done          :1,
+                            spi_irq_flag_tx_done :1,
+                            spi_irq_flag_rx_done :1,
+                            spi_tx_async         :1,
+                            spi_rx_async         :1,
+                            opened               :1,
+                            dsleep               :1;
+#ifdef CONFIG_SLEEP
+    struct {
+        uint32 con0;
+        uint32 con1;
+        uint32 baud;
+        uint32 tdmalen;
+        uint32 rdmalen;
+        uint32 tstadr;
+        uint32 rstadr;
+        uint32 slavesta;
+        uint32 ssp_dly;
+    }bp_regs;
+    uint32               bp_irq_flags;
+    spi_irq_hdl          bp_irq_hdl;
+    uint32               bp_irq_data;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+
+};
+
+int32 hgspi_v1_attach(uint32 dev_id, struct hgspi_v1 *p_spi);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGSPI_V1_H_ */

sdk/include/dev/spi/hgspi_v2.h

@@ -0,0 +1,28 @@
+#ifndef _HGSPI_V2_H
+#define _HGSPI_V2_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+struct hgspi_v2 {
+    struct spi_device   dev;
+    uint32              hw ;
+    spi_irq_hdl         irq_hdl ;
+    uint32              irq_data;
+    uint32              irq_num ;
+    uint16              opened  ;
+    uint16              spi_irq_flag_tx_done: 1,
+                        spi_irq_flag_rx_done: 1;
+};
+
+
+int32 hgspi_v2_attach(uint32 dev_id, struct hgspi_v2 *spi);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/spi/hgspi_v3.h

@@ -0,0 +1,69 @@
+#ifndef _HGSPI_V3_H_
+#define _HGSPI_V3_H_
+#include "hal/spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hgspi_v3 {
+    struct spi_device       dev;
+    uint32                  hw;
+    uint32                  irq_num;
+    spi_irq_hdl             irq_hdl;
+    uint32                  irq_data;
+    //struct os_mutex         os_spi_tx_lock;
+    //struct os_mutex         os_spi_rx_lock;
+    struct os_mutex         os_spi_lock;
+    struct os_semaphore     os_spi_tx_done;
+    struct os_semaphore     os_spi_rx_done;
+    uint32                  timeout;
+    uint16                  len_threshold;
+    uint16                  spi_tx_done          :1,
+                            spi_rx_done          :1,
+                            spi_irq_flag_tx_done :1,
+                            spi_irq_flag_rx_done :1,
+                            spi_tx_async         :1,
+                            spi_rx_async         :1,
+                            opened               :1,
+                            dsleep               :1;
+#ifdef CONFIG_SLEEP
+    struct {
+        uint32 con0;
+        uint32 con1;
+        uint32 cmd_data;
+        uint32 timecon;
+        uint32 tdmalen;
+        uint32 rdmalen;
+        uint32 tdmacnt;
+        uint32 rdmacnt;
+        uint32 tstadr;
+        uint32 rstadr;
+        uint32 sta1;
+        uint32 sta2;
+        uint32 slavesta;
+        uint32 ownadrcon;
+        uint32 rbuf;
+        uint32 timeoutcon;
+        uint32 rxtimeoutcon;
+        uint32 rstadr1;
+        uint32 vsync_tcon;
+        uint32 hsync_tcon;
+    }bp_regs;
+    
+    uint32               bp_irq_flags;
+    spi_irq_hdl          bp_irq_hdl;
+    uint32               bp_irq_data;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+
+};
+
+int32 hgspi_v3_attach(uint32 dev_id, struct hgspi_v3 *p_spi);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGSPI_V3_H_ */

sdk/include/dev/spi/hgspi_xip.h

@@ -0,0 +1,90 @@
+#ifndef _HGSPI_XIP_H_
+#define _HGSPI_XIP_H_
+#include "hal/spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum hgspi_xip_flags {
+    hgspi_xip_flags_ready,
+    hgspi_xip_flags_suspend,
+    hgspi_xip_flags_suspend_pasr,
+    hgspi_xip_flags_suspend_ulp,
+    hgspi_xip_flags_suspend_pd,
+    hgspi_xip_flags_xip,
+};
+
+struct hgspi_xip {
+    struct spi_device       dev;
+//    struct os_mutex         xip_lock;
+    
+    uint32                  hw;
+    
+    uint32                  flags;
+#ifdef CONFIG_SLEEP
+    uint32                  regs[30];
+#endif    
+};
+
+struct hgcqspi {
+    //struct qspi_device      dev;
+    void                   *hw;
+    uint32                  irq_num;
+    //qspi_irq_hdl            irq_hdl;
+    uint32                  irq_data;
+    uint32                  opened;
+    uint32                  flags;
+};
+
+
+struct hgxip_flash_custom_read
+{
+    uint8_t dummys; //最大31,内部默认有24个dummys
+    uint8_t cmd;
+    uint16_t size; 
+    uint32_t addr;
+    uint8_t *buf;
+};
+
+struct hgxip_flash_reg_opt_param
+{
+    uint8_t cmd;
+    /* write opt when pre_cmd is valid(0xFF != pre_cmd); e.g.: 0x06/0x50 */
+    uint8_t pre_cmd; 
+    uint8_t len; 
+    uint8_t *buf;
+};
+
+
+enum MSROM_FUNC
+{
+    MSROM_MEMSET,
+    MSROM_MEMCPY,
+    MSROM_MEMCMP,
+    MSROM_STRCASECMP,
+    MSROM_QSPI_CMD_BUSY_WAIT = MSROM_STRCASECMP, 
+    MSROM_STRNCASECMP,
+    MSROM_HIGHPASS_FILTER_100HZ_ASM = MSROM_STRNCASECMP,
+    MSROM_QSPI_XIP_ERASE,
+    MSROM_QSPI_XIP_READ,
+    MSROM_QSPI_XIP_WRITE,
+    MSROM_QSPI_XIP_OPT_ENTER,
+    MSROM_QSPI_XIP_OPT_EXIT,
+    MSROM_QSPI_ENTER_XIP_MODE,
+    MSROM_QSPI_EXIT_XIP_MODE,
+    MSROM_QSPI_STIG,
+    MSROM_OSPI_PSRAM_MRR,
+    MSROM_OSPI_PSRAM_MRW,
+    MSROM_OSPI_STIG,
+};
+
+int32 hgspi_xip_attach(uint32 dev_id, struct hgspi_xip *p_spi);
+uint32_t get_msrom_func(uint32_t func_code);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGSPI_V1_H_ */
+

sdk/include/dev/sysaes/hg_sysaes_v2.h

@@ -0,0 +1,23 @@
+#ifndef _HG_SYSAES_V2_H_
+#define _HG_SYSAES_V2_H_
+#include "hal/sysaes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hg_sysaes_v2 {
+    struct sysaes_dev   dev;
+    void               *hw;
+    struct os_mutex     lock;
+    struct os_semaphore done;
+    uint32              irq_num;
+    uint32              flags;
+#ifdef CONFIG_SLEEP
+    uint32              *regs;
+#endif    
+};
+
+int32 hg_sysaes_v2_attach(uint32 dev_id, struct hg_sysaes_v2 *sysaes);
+
+#endif /* _HG_SYSAES_V2_H_ */

sdk/include/dev/sysaes/hg_sysaes_v3.h

@@ -0,0 +1,23 @@
+#ifndef _HG_SYSAES_V3_H_
+#define _HG_SYSAES_V3_H_
+#include "hal/sysaes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct hg_sysaes_v3 {
+    struct sysaes_dev   dev;
+    void               *hw;
+    struct os_mutex     lock;
+    struct os_semaphore done;
+    uint32              irq_num;
+    uint32              flags;
+#ifdef CONFIG_SLEEP
+    uint32              *regs;
+#endif    
+};
+
+int32 hg_sysaes_v3_attach(uint32 dev_id, struct hg_sysaes_v3 *sysaes);
+
+#endif /* _HG_SYSAES_V3_H_ */

sdk/include/dev/timer/hgtimer_v3.h

@@ -0,0 +1,494 @@
+#ifndef _HGTIMER_V3_H_
+#define _HGTIMER_V3_H_
+#include "hal/timer_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @brief TIMER register structure
+  * @{
+  */
+struct hgtimer_hw {
+    __IO uint32_t TMR_CON;
+    __IO uint32_t TMR_EN;
+    __IO uint32_t TMR_IE;
+    __IO uint32_t TMR_CNT;
+    __IO uint32_t TMR_FLG;
+    __IO uint32_t TMR_CLR;
+    __IO uint32_t TMR_CAP1;
+    __IO uint32_t TMR_CAP2;
+    __IO uint32_t TMR_CAP3;
+    __IO uint32_t TMR_CAP4;
+    __IO uint32_t TMR_DCTL;
+    __IO uint32_t TMR_DADR;
+    __IO uint32_t TMR_DLEN;
+    __IO uint32_t TMR_DCNT;
+    __IO uint32_t TMR_IR_BCNT;
+};
+
+struct hgtimer {
+    struct timer_device     dev;
+    struct hgtimer_hw      *hw;
+    uint32                  irq_num;
+    timer_cb_hdl            cb;
+    uint32                  cb_data;
+    enum timer_type         mode;
+    uint32                  flags;
+    uint32                  opened;
+};
+
+struct hgtimer_all {
+    __IO uint32_t TMR_ALLCON;
+};
+
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMER_Register_Constants TIMER Register Constants
+  * @ingroup  TIMER_Driver
+  * @brief    TIMER register constant table definition
+  * @{
+  */
+
+/***** TIMERx CON Register *****/
+/*! Timer IR selection from TIMER0, TIMER2~7
+ */
+#define LL_TIMER_CON_IR_FIRST_LSB                 (1UL << 29)
+/*! Timer IR function logic 0 PWM polarity selection (for TIMER1 only)
+ */
+#define LL_TIMER_CON_IR_ZERO_PWMPOL               (1UL << 28)
+/*! Timer IR function logic 1 PWM polarity selection (for TIMER1 only)
+ */
+#define LL_TIMER_CON_IR_ONE_PWMPOL                (1UL << 27)
+/*! Timer IR function enable (for TIMER1 only)
+ */
+#define LL_TIMER_CON_IR_EN                        (1UL << 26)
+/*! PWM polarity selection in TIMER module
+ */
+#define LL_TIMER_CON_PWMPOL                       (1UL << 25)
+/*! The polarity of capture event 4 is selected: 0 = rising edge, 1 = falling edge.
+ */
+#define LL_TIMER_CON_CAP4POL                      (1UL << 24)
+/*! The polarity of capture event 3 is selected: 0 = rising edge, 1 = falling edge.
+ */
+#define LL_TIMER_CON_CAP3POL                      (1UL << 23)
+/*! The polarity of capture event 2 is selected: 0 = rising edge, 1 = falling edge.
+ */
+#define LL_TIMER_CON_CAP2POL                      (1UL << 22)
+/*! The polarity of capture event 1 is selected: 0 = rising edge, 1 = falling edge.
+ */
+#define LL_TIMER_CON_CAP1POL                      (1UL << 21)
+/*! When the capture event 4 occurs, the value of the CNT is automatically cleared.
+ */
+#define LL_TIMER_CON_CTRRST4                      (1UL << 20)
+/*! When the capture event 3 occurs, the value of the CNT is automatically cleared.
+ */
+#define LL_TIMER_CON_CTRRST3                      (1UL << 19)
+/*! When the capture event 2 occurs, the value of the CNT is automatically cleared.
+ */
+#define LL_TIMER_CON_CTRRST2                      (1UL << 18)
+/*! When the capture event 1 occurs, the value of the CNT is automatically cleared.
+ */
+#define LL_TIMER_CON_CTRRST1                      (1UL << 17)
+/*! The number of the Capture register:
+ *  00 : Capture data store in CAP1
+ *  01 : Capture data store in CAP1 CAP2
+ *  10 : Capture data store in CAP1 CAP2 CAP3
+ *  11 : Capture data store in CAP1 CAP2 CAP3 CAP4
+ */
+#define LL_TIMER_CON_CAP_CNT(n)                   (((n)&0x3) << 15)
+/*! Capture selection:
+ *  00 : GPIO
+ *  01 : GPIO OR
+ *  10 : compare0 output
+ *  11 : compare1 output
+ */
+#define LL_TIMER_CON_CAP_SEL(n)                   (((n)&0x3) << 13)
+/*! Output sync signal selection:
+ *  00 : CNT value = PRD value
+ *  01 : CNT value = CMP value
+ *  10 : Output SYNCI value to SYNCO
+ *  11 : PWM output is assigned to SYNCO
+ */
+#define LL_TIMER_CON_SYNCO_SEL(n)                 (((n)&0x3) << 11)
+/*! Synci polarity inversion:
+ *  1 : Invert
+ *  0 : not reversed
+ */
+#define LL_TIMER_CON_SYNCI_POL                    (1UL << 10)
+/*! Synci function selection
+ *  00 : disable
+ *  01 : kick start
+ *  10 : reset
+ *  11 : gating
+ */
+#define LL_TIMER_CON_SLAVE_MODE(n)                (((n)&0x3) << 8)
+/*! Timer prescaler settings:
+ *  000 : 0 frequency division
+ *  001 : 2 frequency division
+ *  010 : 4 frequency division
+ *  011 : 8 frequency division
+ *  100 : 16 frequency division
+ *  101 : 32 frequency division
+ *  110 : 64 frequency division
+ *  111 : 128 frequency division
+ */
+#define LL_TIMER_CON_PSC(n)                       (((n)&0x7) << 5)
+/*! Timer counter source select bits:
+ *  001 : Internal high speed RC
+ *  010 : Internal low speed RC
+ *  011 : External crystal oscillator divided by 2 clocks
+ *  100 : timer inc pin rising
+ *  101 : timer inc pin falling
+ *  110 : timer inc pin rising and falling
+ *  Others : system clock
+ */
+#define LL_TIMER_CON_INC_SRC_SEL(n)               (((n)&0x7) << 2)
+/*! Timer mode select bits:
+ *  00 : timer counter mode
+ *  01 : timer pwm mode
+ *  10 : timer capture mode
+ *  Others : reservation
+ */
+#define LL_TIMER_CON_MODE_SEL(n)                  (((n)&0x3) << 0)
+
+
+/***** TIMERx EN Register *****/
+/*! TMR enable signal, active high.
+ */
+#define LL_TIMER_EN_TMREN                         (1UL << 0)
+
+
+/***** TIMERx IE Register *****/
+/*! Timer IR TX word done interrupt enable (for TIMER1 only)
+ */
+#define LL_TIMER_IE_IR_TX_WORD_DONE_IE            (1UL << 11)
+/*! Timer IR TX done interrupt enable (for TIMER1 only)
+ */
+#define LL_TIMER_IE_IR_TX_DONE_IE                 (1UL << 10)
+/*! Dma buffer full interrupt enable.
+ */
+#define LL_TIMER_IE_DMA_FL_IE                     (1UL << 9)
+/*! Dma buffer half full interrupt enable.
+ */
+#define LL_TIMER_IE_DMA_HF_IE                     (1UL << 8)
+/*! The slave mode trigger mode or reset mode interrupt enable.
+ */
+#define LL_TIMER_IE_SLAVE_IE                      (1UL << 7)
+/*! When the CNT value is equal to the CMP value, the interrupt is enabled and is valid only in pwm mode.
+ */
+#define LL_TIMER_IE_CMP_IE                        (1UL << 6)
+/*! When the CNT value is equal to the PRD value, the interrupt is enabled and is valid only in the counter mode/PWM mode.
+ */
+#define LL_TIMER_IE_PRD_IE                        (1UL << 5)
+/*! When the CNT value overflows (16'hffff), the interrupt is enabled.
+ */
+#define LL_TIMER_IE_OVF_IE                        (1UL << 4)
+/*! When the capture event 4 occurs, the interrupt is enabled.
+ */
+#define LL_TIMER_IE_CAP4_IE                       (1UL << 3)
+/*! When the capture event 3 occurs, the interrupt is enabled.
+ */
+#define LL_TIMER_IE_CAP3_IE                       (1UL << 2)
+/*! When the capture event 2 occurs, the interrupt is enabled.
+ */
+#define LL_TIMER_IE_CAP2_IE                       (1UL << 1)
+/*! When the capture event 1 occurs, the interrupt is enabled.
+ */
+#define LL_TIMER_IE_CAP1_IE                       (1UL << 0)
+
+
+/***** TIMERx CNT Register *****/
+/*! Count register.
+ */
+#define LL_TIMER_CNT(n)                           (((n)&0xFFFFFFFF) << 0)
+
+
+/***** TIMERx FLG Register *****/
+/*! Timer IR TX word done interrupt flag (for TIMER1 only)
+ */
+#define LL_TIMER_IE_IR_TX_WORD_DONE_FLG           (1UL << 11)
+/*! Timer IR TX done interrupt flag (for TIMER1 only)
+ */
+#define LL_TIMER_IE_IR_TX_DONE_FLG                (1UL << 10)
+/*! Dma buffer full sign.
+ */
+#define LL_TIMER_IE_DMA_FL_FLG                    (1UL << 9)
+/*! Dma buffer half full sign.
+ */
+#define LL_TIMER_IE_DMA_HF_FLG                    (1UL << 8)
+/*! The slave mode flag (reset or trigger only).
+ */
+#define LL_TIMER_IE_SLAVE_FLG                     (1UL << 7)
+/*! The CNT value is equal to the CMP value flag and is valid only in pwm mode.
+ */
+#define LL_TIMER_IE_CMP_FLG                       (1UL << 6)
+/*! The CNT value is equal to the PRD value flag and is valid only in counter mode/PWM mode.
+ */
+#define LL_TIMER_IE_PRD_FLG                       (1UL << 5)
+/*! CNT value overflow (16'hffff) flag.
+ */
+#define LL_TIMER_IE_OVF_FLG                       (1UL << 4)
+/*! Capture event 4 occurs.
+ */
+#define LL_TIMER_IE_CAP4_FLG                      (1UL << 3)
+/*! Capture event 3 occurs.
+ */
+#define LL_TIMER_IE_CAP3_FLG                      (1UL << 2)
+/*! Capture event 2 occurs.
+ */
+#define LL_TIMER_IE_CAP2_FLG                      (1UL << 1)
+/*! Capture event 1 occurs.
+ */
+#define LL_TIMER_IE_CAP1_FLG                      (1UL << 0)
+
+
+/***** TIMERx CLR Register *****/
+/*! Timer IR TX word done interrupt clear (for TIMER1 only)
+ */
+#define LL_TIMER_IE_IR_TX_WORD_DONE_CLR           (1UL << 11)
+/*! Timer IR TX done interrupt clear (for TIMER1 only)
+ */
+#define LL_TIMER_IE_IR_TX_DONE_CLR                (1UL << 10)
+/*! Dma buffer full sign clear.
+ */
+#define LL_TIMER_IE_DMA_FL_CLR                    (1UL << 9)
+/*! Dma buffer half full sign clear.
+ */
+#define LL_TIMER_IE_DMA_HF_CLR                    (1UL << 8)
+/*! The slave mode flag (reset or trigger only) clear.
+ */
+#define LL_TIMER_IE_SLAVE_CLR                     (1UL << 7)
+/*! The CNT value is equal to the CMP value flag clear.
+ */
+#define LL_TIMER_IE_CMP_CLR                       (1UL << 6)
+/*! The CNT value is equal to the PRD value flag clear.
+ */
+#define LL_TIMER_IE_PRD_CLR                       (1UL << 5)
+/*! The CNT value overflow (16'hffff) flag is cleared.
+ */
+#define LL_TIMER_IE_OVF_CLR                       (1UL << 4)
+/*! Capture event 4 occurs flag clear.
+ */
+#define LL_TIMER_IE_CAP4_CLR                      (1UL << 3)
+/*! Capture event 3 occurs flag clear.
+ */
+#define LL_TIMER_IE_CAP3_CLR                      (1UL << 2)
+/*! Capture event 2 occurs flag clear.
+ */
+#define LL_TIMER_IE_CAP2_CLR                      (1UL << 1)
+/*! Capture event 1 occurs flag clear.
+ */
+#define LL_TIMER_IE_CAP1_CLR                      (1UL << 0)
+
+
+/***** TIMERx CAP1/PR Register *****/
+/*! Capture mode        : capture register 1
+ *  Timing mode/PWM mode: Count period register
+ */
+#define LL_TIMER_CMP1_PR(n)                       (((n)&0xFFFFFFFF) << 0)
+
+
+/***** TIMERx CAP2/CMP Register *****/
+/*! Capture mode        : capture register 2
+ *  Timing mode/PWM mode: compare register
+ */
+#define LL_TIMER_CMP2_CMP(n)                      (((n)&0xFFFFFFFF) << 0)
+
+
+/***** TIMERx CAP3/PR_SD Register *****/
+/*! Capture mode        : capture register 3
+ *  Timing mode/PWM mode: counting period shadow register
+ */
+#define LL_TIMER_CMP3_PR_SD(n)                    (((n)&0xFFFFFFFF) << 0)
+
+
+/***** TIMERx CAP4/CMP_SD Register *****/
+/*! Capture mode        : capture register 4
+ *  Timing mode/PWM mode: Compare shadow registers
+ */
+#define LL_TIMER_CMP4_CMP_SD(n)                   (((n)&0xFFFFFFFF) << 0)
+
+
+/***** TIMERx DCCTL Register *****/
+/*! Dma mode selection
+ *  0 : Single mode, after the specified dma length is completed, disable TMR.
+ *  1 : Loop mode, after the dma length is specified, restart from the start address.
+ */
+#define LL_TIMER_DMA_LPBK                         (1UL << 1)
+/*! Dma enabled.
+ */
+#define LL_TIMER_DMA_EN                           (1UL << 0)
+
+
+/***** TIMERx DADR Register *****/
+/*! Dma starting address.
+ */
+#define LL_TIMER_DADR_STADR(n)                    (((n)&0xFFFF) << 0)
+
+
+/***** TIMERx DLEN Register *****/
+/*! Dma buffer length (32bit), if the buffer is n, the configuration is n-1;
+ */
+#define LL_TIMER_DLEN_LEN(n)                      (((n)&0xFFFF) << 0)
+
+
+/***** TIMERx DCNT Register *****/
+/*! The number of dma data is valid.
+ */
+#define LL_TIMER_DCNT_CNT(n)                      (((n)&0xFFFF) << 0)
+
+
+/***** TIMER ALLCON Register *****/
+/*! The timer sync count value is cleared.
+ */
+#define LL_TIMER_ALLCON_TMR5_SYNC                 (1UL << 13)
+/*! The timer3 sync count value is cleared.
+ */
+#define LL_TIMER_ALLCON_TMR3_SYNC                 (1UL << 11)
+/*! The timer2 sync count value is cleared.
+ */
+#define LL_TIMER_ALLCON_TMR2_SYNC                 (1UL << 10)
+/*! The timer1 sync count value is cleared.
+ */
+#define LL_TIMER_ALLCON_TMR1_SYNC                 (1UL << 9)
+/*! The timer0 sync count value is cleared.
+ */
+#define LL_TIMER_ALLCON_TMR0_SYNC                 (1UL << 8)
+/*! Timer5 starts counting.
+ */
+#define LL_TIMER_ALLCON_TMR5_KICK                 (1UL << 5)
+/*! Timer3 starts counting.
+ */
+#define LL_TIMER_ALLCON_TMR3_KICK                 (1UL << 3)
+/*! Timer2 starts counting.
+ */
+#define LL_TIMER_ALLCON_TMR2_KICK                 (1UL << 2)
+/*! Timer1 starts counting.
+ */
+#define LL_TIMER_ALLCON_TMR1_KICK                 (1UL << 1)
+/*! Timer0 starts counting.
+ */
+#define LL_TIMER_ALLCON_TMR0_KICK                 (1UL << 0)
+/*! Configure the trigger path for the sync count of TIMER.
+ */
+#define LL_TIMER_ALLCON_SYNC_COUNT_ALL(n)         (((n)&0x3F) << 8)
+/*! Configure the synchronous trigger path of TIMER.
+ */
+#define LL_TIMER_ALLCON_KICK_ALL(n)               (((n)&0x3F) << 0)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup TIMER_Exported_Constants TIMER Exported Constants
+  * @ingroup  TIMER_Driver
+  * @brief    TIMER external constant definition
+  * @{
+  */
+
+/**
+  * @brief Enumeration constant for low layer TIMER Prescaler for timer
+  */
+enum hgtimer_psc {
+    /*! Timer clock source 0 prescaler
+     */
+    HGTIMER_PSC_0 = 0,
+    /*! Timer clock source 2 prescaler
+     */
+    HGTIMER_PSC_2,
+    /*! Timer clock source 4 prescaler
+     */
+    HGTIMER_PSC_4,
+    /*! Timer clock source 8 prescaler
+     */
+    HGTIMER_PSC_8,
+    /*! Timer clock source 16 prescaler
+     */
+    HGTIMER_PSC_16,
+    /*! Timer clock source 32 prescaler
+     */
+    HGTIMER_PSC_32,
+    /*! Timer clock source 64 prescaler
+     */
+    HGTIMER_PSC_64,
+    /*! Timer clock source 128 prescaler
+     */
+    HGTIMER_PSC_128,
+};
+
+/**
+  * @brief Enumeration constant for low layer TIMER clock source
+  */
+enum hgtimer_src_sel {
+    /*! Select the internal high speed RC clock.
+     */
+    HGTIMER_SOURCE_INTER_HIGH_SPEED_RC = 0x1,
+    /*! Select the internal low speed RC clock.
+     */
+    HGTIMER_SOURCE_INTER_LOW_SPEED_RC,
+    /*! Select the external crystal and divide by 2.
+     */
+    HGTIMER_SOURCE_EXTER_CRYSTAL_DIV_2,
+    /*! Select the pin input from the outside and on the rising edge.
+     */
+    HGTIMER_SOURCE_INC_PIN_RISING,
+    /*! Select the pin input from the outside and on the falling edge.
+     */
+    HGTIMER_SOURCE_INC_PIN_FALLING,
+    /*! Select the pin input from the outside and on both the rising edge and the falling edge.
+     */
+    HGTIMER_SOURCE_INC_PIN_RISING_FALLING,
+    /*! Select the system clock.
+     */
+    HGTIMER_SOURCE_SYS_CLK,
+};
+
+/**
+  * @brief Enumeration constant for low layer TIMER the pattern of the timer
+  */
+enum hgtimer_mode {
+    /*! Timer mode selection: counter mode
+     */
+    HGTIMER_MODE_COUNTER,
+    /*! Timer mode selection: PWM mode
+     */
+    HGTIMER_MODE_PWM,
+    /*! Timer mode selection: capture mode
+     */
+    HGTIMER_MODE_CAPTURE,
+};
+
+/**
+  * @brief Enum constants, Mode selection in slave mode in TIMER.
+  */
+typedef enum {
+    /*! Disable.
+     */
+    HGTIMER_SLAVE_MODE_DISABLE = 0,
+    /*! Select the trigger mode.
+     */
+    HGTIMER_SLAVE_MODE_KICK_START,
+    /*! Select the reset mode.
+     */
+    HGTIMER_SLAVE_MODE_RESET,
+    /*! Select the gate mode.
+     */
+    HGTIMER_SLAVE_MODE_GATING,
+} TYEP_ENUM_LL_TIMER_SLAVE_MODE;
+
+/**
+  * @}
+  */
+
+int32 hgtimer_attach(uint32 dev_id, struct hgtimer *timer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HGTIMER_V3_H_ */

sdk/include/dev/timer/hgtimer_v4.h

@@ -0,0 +1,114 @@
+#ifndef _HGTIMER_V4_H
+#define _HGTIMER_V4_H
+#include "hal/timer_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*-----timer lower layer: counter mode-----*/
+#define HGTIMER_V4_TYPE_ONCE       BIT(0)
+#define HGTIMER_V4_TYPE_PERIODIC   BIT(1)
+#define HGTIMER_V4_TYPE_COUNTER    BIT(2)
+
+
+/*----timer lower layer: PWM function cmd----*/
+#define HGTIMER_V4_PWM_FUNC_CMD_INIT                       			HGPWM_V0_FUNC_CMD_INIT
+#define HGTIMER_V4_PWM_FUNC_CMD_DEINIT                     			HGPWM_V0_FUNC_CMD_DEINIT
+#define HGTIMER_V4_PWM_FUNC_CMD_START                      			HGPWM_V0_FUNC_CMD_START
+#define HGTIMER_V4_PWM_FUNC_CMD_STOP                       			HGPWM_V0_FUNC_CMD_STOP
+/* IOCTL CMD */                                        
+#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY      			HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
+#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY      			HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
+#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PRESCALER        			HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
+#define HGTIMER_V4_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY   HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
+/* IRQ_FLAG */                                         
+#define HGTIMER_V4_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE        			HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
+#define HGTIMER_V4_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD        		 	HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
+                                                       
+#define HGTIMER_V4_PWM_FUNC_CMD_RELEASE_IRQ                			HGPWM_V0_FUNC_CMD_RELEASE_IRQ
+
+#define HGTIMER_V4_PWM_FUNC_CMD_SUSPEND                    			HGPWM_V0_FUNC_CMD_SUSPEND
+#define HGTIMER_V4_PWM_FUNC_CMD_RESUME                     			HGPWM_V0_FUNC_CMD_RESUME
+
+
+
+
+
+
+/*----timer lower layer: cap function cmd----*/
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_INIT                   HGCAPTURE_V0_FUNC_CMD_INIT
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_DEINIT                 HGCAPTURE_V0_FUNC_CMD_DEINIT
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_START                  HGCAPTURE_V0_FUNC_CMD_START
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_STOP                   HGCAPTURE_V0_FUNC_CMD_STOP
+/* IOCTL CMD */                                        
+
+/* IRQ_FLAG */                                         
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE    HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW   HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW
+                                                       
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_RELEASE_IRQ            HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ
+
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_SUSPEND                HGCAPTURE_V0_FUNC_CMD_SUSPEND
+#define HGTIMER_V4_CAPTURE_FUNC_CMD_RESUME                 HGCAPTURE_V0_FUNC_CMD_RESUME 
+
+
+
+
+struct hgtimer_v4 {
+    struct timer_device   dev;
+    uint32                hw;
+    timer_cb_hdl          _counter_irq_hdl;
+    pwm_irq_hdl           _pwm_irq_hdl;
+    capture_irq_hdl       _capture_irq_hdl;
+    uint32                irq_data;
+    uint32                irq_num;
+    uint16                type;
+    uint16                counter_once_en  :1,
+                          counter_period_en:1,
+                          counter_en       :1,
+                          pwm_en           :1,
+                          cap_en           :1,
+                          ir_en            :1,
+                          opened           :1,
+                          dsleep           :1;
+#ifdef CONFIG_SLEEP
+    struct {
+        uint32 tmr_con;
+        uint32 tmr_en;
+        uint32 tmr_ie;
+        uint32 tmr_cap1;
+        uint32 tmr_cap2;
+        uint32 tmr_cap3;
+        uint32 tmr_cap4;
+        /* The following registers only for timer1 & timer2 */
+        uint32 tmr_dctl;
+        uint32 tmr_dadr;
+        uint32 tmr_dlen;
+        uint32 tmr_dcnt;
+        uint32 tmr_ir_bcnt;
+    }bp_regs;
+    uint32               bp_irq_flags;
+    timer_cb_hdl         bp_irq_hdl_timer;
+    pwm_irq_hdl          bp_irq_hdl_pwm;
+    capture_irq_hdl      bp_irq_hdl_capture;
+    uint32               bp_irq_data_timer;
+    uint32               bp_irq_data_pwm;
+    uint32               bp_irq_data_capture;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+
+};
+
+
+
+int32 hgtimer_v4_attach(uint32 dev_id, struct hgtimer_v4 *timer);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/dev/timer/hgtimer_v5.h

@@ -0,0 +1,84 @@
+#ifndef _HGTIMER_V5_H
+#define _HGTIMER_V5_H
+#include "hal/timer_device.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*-----timer lower layer: counter mode-----*/
+#define HGTIMER_V5_TYPE_ONCE       BIT(0)
+#define HGTIMER_V5_TYPE_PERIODIC   BIT(1)
+#define HGTIMER_V5_TYPE_COUNTER    BIT(2)
+
+
+/*----timer lower layer: PWM function cmd----*/
+#define HGTIMER_V5_PWM_FUNC_CMD_INIT                        		HGPWM_V0_FUNC_CMD_INIT
+#define HGTIMER_V5_PWM_FUNC_CMD_DEINIT                      		HGPWM_V0_FUNC_CMD_DEINIT
+#define HGTIMER_V5_PWM_FUNC_CMD_START                       		HGPWM_V0_FUNC_CMD_START
+#define HGTIMER_V5_PWM_FUNC_CMD_STOP                        		HGPWM_V0_FUNC_CMD_STOP
+/* IOCTL CMD */                                        
+#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY       		HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
+#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY       		HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
+#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM    		HGPWM_V0_FUNC_CMD_IOCTL_SET_SINGLE_INCREAM
+#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE  		HGPWM_V0_FUNC_CMD_IOCTL_SET_INCREAM_DECREASE
+#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PRESCALER        			HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
+#define HGTIMER_V5_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY   HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
+
+
+/* IRQ_FLAG */                                         
+#define HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE         		HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
+#define HGTIMER_V5_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD          		HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
+                                                       
+#define HGTIMER_V5_PWM_FUNC_CMD_RELEASE_IRQ                 		HGPWM_V0_FUNC_CMD_RELEASE_IRQ
+
+#define HGTIMER_V5_PWM_FUNC_CMD_SUSPEND                     		HGPWM_V0_FUNC_CMD_SUSPEND
+#define HGTIMER_V5_PWM_FUNC_CMD_RESUME                      		HGPWM_V0_FUNC_CMD_RESUME
+
+
+
+
+/*----timer lower layer: cap function cmd----*/
+//#define HGTIMER_V5_CAPTURE_FUNC_CMD_INIT                   BIT(30) | 1
+//#define HGTIMER_V5_CAPTURE_FUNC_CMD_DEINIT                 BIT(30) | 2
+//#define HGTIMER_V5_CAPTURE_FUNC_CMD_START                  BIT(30) | 3
+//#define HGTIMER_V5_CAPTURE_FUNC_CMD_STOP                   BIT(30) | 4
+///* IOCTL CMD */                                        
+//
+///* IRQ_FLAG */                                         
+//#define HGTIMER_V5_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE    BIT(30) | 7
+//#define HGTIMER_V5_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW   BIT(30) | 8
+//                                                       
+//#define HGTIMER_V5_CAPTURE_FUNC_CMD_RELEASE_IRQ            BIT(30) | 9
+
+
+struct hgtimer_v5 {
+    struct timer_device   dev;
+    uint32                hw;
+    timer_cb_hdl          _counter_irq_hdl;
+    pwm_irq_hdl           _pwm_irq_hdl;
+    //capture_irq_hdl       _capture_irq_hdl;
+    uint32                irq_data;
+    uint32                irq_num;
+    uint16                type;
+    uint16                counter_once_en  :1,
+                          counter_period_en:1,
+                          counter_en       :1,
+                          pwm_en           :1,
+                          cap_en           :1,
+                          ir_en            :1,
+                          opened           :1;
+};
+
+
+
+int32 hgtimer_v5_attach(uint32 dev_id, struct hgtimer_v5 *timer);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/dev/timer/hgtimer_v6.h

@@ -0,0 +1,82 @@
+#ifndef _HGTIMER_V6_H
+#define _HGTIMER_V6_H
+#include "hal/timer_device.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+/*-----timer lower layer: counter mode-----*/
+#define HGTIMER_V6_TYPE_ONCE       BIT(0)
+#define HGTIMER_V6_TYPE_PERIODIC   BIT(1)
+#define HGTIMER_V6_TYPE_COUNTER    BIT(2)
+
+
+/*----timer lower layer: PWM function cmd----*/
+#define HGTIMER_V6_PWM_FUNC_CMD_INIT                   				HGPWM_V0_FUNC_CMD_INIT
+#define HGTIMER_V6_PWM_FUNC_CMD_DEINIT                 				HGPWM_V0_FUNC_CMD_DEINIT
+#define HGTIMER_V6_PWM_FUNC_CMD_START                  				HGPWM_V0_FUNC_CMD_START
+#define HGTIMER_V6_PWM_FUNC_CMD_STOP                   				HGPWM_V0_FUNC_CMD_STOP
+/* IOCTL CMD */                                        
+#define HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY  				HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
+#define HGTIMER_V6_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY  				HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
+#define HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PRESCALER        			HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
+#define HGTIMER_V6_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY   HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
+
+/* IRQ_FLAG */                                         
+#define HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE    				HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
+#define HGTIMER_V6_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD     				HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
+                                                       
+#define HGTIMER_V6_PWM_FUNC_CMD_RELEASE_IRQ            				HGPWM_V0_FUNC_CMD_RELEASE_IRQ
+
+#define HGTIMER_V6_PWM_FUNC_CMD_SUSPEND                				HGPWM_V0_FUNC_CMD_SUSPEND
+#define HGTIMER_V6_PWM_FUNC_CMD_RESUME                 				HGPWM_V0_FUNC_CMD_RESUME
+
+
+
+/*----timer lower layer: cap function cmd----*/
+//#define HGTIMER_V6_CAPTURE_FUNC_CMD_INIT                   BIT(30) | 1
+//#define HGTIMER_V6_CAPTURE_FUNC_CMD_DEINIT                 BIT(30) | 2
+//#define HGTIMER_V6_CAPTURE_FUNC_CMD_START                  BIT(30) | 3
+//#define HGTIMER_V6_CAPTURE_FUNC_CMD_STOP                   BIT(30) | 4
+///* IOCTL CMD */                                        
+//
+///* IRQ_FLAG */                                         
+//#define HGTIMER_V6_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE    BIT(30) | 7
+//#define HGTIMER_V6_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW   BIT(30) | 8
+//                                                       
+//#define HGTIMER_V6_CAPTURE_FUNC_CMD_RELEASE_IRQ            BIT(30) | 9
+
+
+struct hgtimer_v6 {
+    struct timer_device   dev;
+    uint32                hw_comm;
+    uint32                hw_suptmrx;
+    timer_cb_hdl          _counter_irq_hdl;
+    pwm_irq_hdl           _pwm_irq_hdl;
+    //capture_irq_hdl     _capture_irq_hdl;
+    uint32                irq_data;
+    uint32                irq_num;
+    uint16                type;
+    uint16                counter_once_en  :1,
+                          counter_period_en:1,
+                          counter_en       :1,
+                          pwm_en           :1,
+                          cap_en           :1,
+                          ir_en            :1,
+                          opened           :1;
+};
+
+
+
+int32 hgtimer_v6_attach(uint32 dev_id, struct hgtimer_v6 *timer);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/dev/timer/hgtimer_v7.h

@@ -0,0 +1,106 @@
+#ifndef _HGTIMER_V7_H
+#define _HGTIMER_V7_H
+#include "hal/timer_device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*-----timer lower layer: counter mode-----*/
+#define HGTIMER_V7_TYPE_ONCE       BIT(0)
+#define HGTIMER_V7_TYPE_PERIODIC   BIT(1)
+#define HGTIMER_V7_TYPE_COUNTER    BIT(2)
+
+
+/*----timer lower layer: PWM function cmd----*/
+#define HGTIMER_V7_PWM_FUNC_CMD_INIT                   				HGPWM_V0_FUNC_CMD_INIT
+#define HGTIMER_V7_PWM_FUNC_CMD_DEINIT                 				HGPWM_V0_FUNC_CMD_DEINIT
+#define HGTIMER_V7_PWM_FUNC_CMD_START                  				HGPWM_V0_FUNC_CMD_START
+#define HGTIMER_V7_PWM_FUNC_CMD_STOP                   				HGPWM_V0_FUNC_CMD_STOP
+/* IOCTL CMD */                                        
+#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY  				HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY
+#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_GET_PERIOD_DUTY  				HGPWM_V0_FUNC_CMD_IOCTL_GET_PERIOD_DUTY
+#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PRESCALER        			HGPWM_V0_FUNC_CMD_IOCTL_SET_PRESCALER
+#define HGTIMER_V7_PWM_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY   HGPWM_V0_FUNC_CMD_IOCTL_SET_PERIOD_DUTY_IMMEDIATELY
+
+/* IRQ_FLAG */                                         
+#define HGTIMER_V7_PWM_FUNC_CMD_REQUEST_IRQ_COMPARE    				HGPWM_V0_FUNC_CMD_REQUEST_IRQ_COMPARE
+#define HGTIMER_V7_PWM_FUNC_CMD_REQUEST_IRQ_PERIOD     				HGPWM_V0_FUNC_CMD_REQUEST_IRQ_PERIOD
+	                                                       
+#define HGTIMER_V7_PWM_FUNC_CMD_RELEASE_IRQ            				HGPWM_V0_FUNC_CMD_RELEASE_IRQ
+
+#define HGTIMER_V7_PWM_FUNC_CMD_SUSPEND                				HGPWM_V0_FUNC_CMD_SUSPEND
+#define HGTIMER_V7_PWM_FUNC_CMD_RESUME                 				HGPWM_V0_FUNC_CMD_RESUME
+
+
+
+
+
+
+/*----timer lower layer: cap function cmd----*/
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_INIT                   HGCAPTURE_V0_FUNC_CMD_INIT
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_DEINIT                 HGCAPTURE_V0_FUNC_CMD_DEINIT
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_START                  HGCAPTURE_V0_FUNC_CMD_START
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_STOP                   HGCAPTURE_V0_FUNC_CMD_STOP
+/* IOCTL CMD */                                        
+
+/* IRQ_FLAG */                                         
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_REQUEST_IRQ_CAPTURE    HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_CAPTURE
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_REQUEST_IRQ_OVERFLOW   HGCAPTURE_V0_FUNC_CMD_REQUEST_IRQ_OVERFLOW
+                                                       
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_RELEASE_IRQ            HGCAPTURE_V0_FUNC_CMD_RELEASE_IRQ
+
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_SUSPEND                HGCAPTURE_V0_FUNC_CMD_SUSPEND
+#define HGTIMER_V7_CAPTURE_FUNC_CMD_RESUME                 HGCAPTURE_V0_FUNC_CMD_RESUME 
+
+
+
+
+struct hgtimer_v7 {
+    struct timer_device   dev;
+    uint32                hw;
+    timer_cb_hdl          _counter_irq_hdl;
+    pwm_irq_hdl           _pwm_irq_hdl;
+    capture_irq_hdl       _capture_irq_hdl;
+    uint32                irq_data;
+    uint32                irq_num;
+    uint16                type;
+    uint16                counter_once_en  :1,
+                          counter_period_en:1,
+                          counter_en       :1,
+                          pwm_en           :1,
+                          cap_en           :1,
+                          ir_en            :1,
+                          opened           :1,
+                          dsleep           :1;
+#ifdef CONFIG_SLEEP
+    struct {
+        uint32 tmr_ctl;
+        uint32 tmr_cnt;
+        uint32 tmr_pr;
+        uint32 tmr_pwm;
+    }bp_regs;
+    uint32               bp_irq_flags;
+    timer_cb_hdl         bp_irq_hdl_timer;
+    pwm_irq_hdl          bp_irq_hdl_pwm;
+    capture_irq_hdl      bp_irq_hdl_capture;
+    uint32               bp_irq_data_timer;
+    uint32               bp_irq_data_pwm;
+    uint32               bp_irq_data_capture;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+
+};
+
+
+
+int32 hgtimer_v7_attach(uint32 dev_id, struct hgtimer_v7 *timer);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/dev/tk/hg_touchKey.h

@@ -0,0 +1,99 @@
+#ifndef __HG_TOUCHKEY_H
+#define __HG_TOUCHKEY_H
+enum tk_ioctl_cmd
+{
+	//硬件寄存器配置
+	TK_IOCTL_CSRST_SET,
+	TK_IOCTL_CMPEN_SET,
+	TK_IOCTL_CMPRB_SET,
+	TK_IOCTL_RES_SET,
+	TK_IOCTL_CURR_SET,
+	TK_IOCTL_ANA_TEN_SET,
+	TK_IOCTL_VOLT_REF_SET,
+	TK_IOCTL_PSR_CNT_SET,
+	TK_IOCTL_PRE_CHARGE_TIME,
+	TK_IOCTL_PRE_DISCHARGE_TIME,
+	TK_IOCTL_CONV_TIME,
+	TK_IOCTL_CHANNLE_MODE,
+	TK_IOCTL_CHARGE_FRE_DIV,
+	TK_IOCTL_CHARGE_FRE0_DIV,
+	TK_IOCTL_CHARGE_FRE1_DIV,
+	TK_IOCTL_CHARGE_FRE2_DIV,
+	TK_IOCTL_CHARGE_FRE3_DIV,
+	TK_IOCTL_SHIELD_SET,
+	TK_IOCTL_SSC_BW,
+	TK_IOCTL_SSC_TYPE_SEL,
+	TK_IOCTL_AUTO_SCAN_EN,
+	TK_IOCTL_ADDR_SET,
+	TK_IOCTL_KICK,
+
+	//算法参数配置
+	TK_IOCTL_ADJUST_TIME,
+	TK_IOCTL_LONG_KEY_TIME,
+	TK_IOCTL_ADJUST_LINE,
+	TK_IOCTL_ADJUST_DIFF_VALU,
+	TK_IOCTL_USE_NUM,
+	TK_IOCTL_WATER_MODE,
+	TK_IOCTL_NM_NUM,
+	TK_IOCTL_NM_LEAVE_CNT,
+	TK_IOCTL_TP_EN,
+	TK_IOCTL_NOISE_VALUE,
+	TK_IOCTL_NM_CM_CNT,
+	TK_IOCTL_NM_CM_VALUE,
+
+	//系统级别的配置(类似信号量,timer等等)
+	TK_SCAN_SEM_HANDL,
+	TK_TIMER_HANDL,
+};
+
+
+
+enum tk_irq_flag
+{
+	TK_SG_CONV_FLAG 	= BIT(0),
+	TK_CH_DONE_FLAG 	= BIT(1),
+	TK_SCAN_DONE_FLAG 	= BIT(2),
+	TK_DMA_FLAG 		= BIT(3),
+	TK_DMA_ERR_FLAG 	= BIT(4),
+};
+typedef int32 (*tk_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param1, uint32 param2);
+
+struct tk_device {
+    struct dev_obj dev;
+    int32(*open)(struct tk_device *tk);
+    int32(*close)(struct tk_device *tk);
+    int32(*ioctl)(struct tk_device *tk, uint32 cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct tk_device *tk, enum tk_irq_flag irq_flag, tk_irq_hdl irq_hdl, uint32 data);
+	int32(*release_irq)(struct tk_device *tk, enum tk_irq_flag irq_flag);
+};
+
+//tk算法私有结构体
+struct hgtk_algorithm
+{
+	uint16 __tk_adjust_time;
+	uint16 __tk_valid_time;
+	uint16 __tk_adjust_line;
+	uint16 __tk_adjust_diff_valu; 
+	uint16 __tk_use_num;
+	uint16 __tk_water_mode;
+	uint16 __tk_nm_num;
+	uint16 __tk_nm_leave_cnt;
+	uint16 __tk_tp_en;
+	uint16 __tk_noise_value;
+	uint16 __tk_nm_cm_cnt;
+	uint16 __tk_nm_cm_value;
+};
+
+struct hgtk_device {
+    struct tk_device     dev     ;
+    uint32               hw      ;
+    tk_irq_hdl           irq_hdl ;
+    uint32               irq_data;
+    uint32               irq_num ;
+    uint32               opened  ;
+	void*				 timer;
+	void*				 sem;
+	struct hgtk_algorithm	tk_pri;
+};
+
+#endif

sdk/include/dev/tk/hg_touchkey_v2.h

@@ -0,0 +1,123 @@
+#ifndef _HGTOUCHKEY_V2_H
+#define _HGTOUCHKEY_V2_H
+#include "hal/tk.h"
+#include "osal/work.h"
+//#include "../driver/tk/hg_touchkey_v2_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef union _u_16 {
+    uint16 w;
+    struct {
+        uint8 h;
+        uint8 l;
+    } b;
+} TYPE_U16;
+
+typedef union _s_16 {
+    int16 w;
+    struct {
+        uint8 h;
+        uint8 l;
+    } b;
+} TYPE_S16;
+
+typedef struct _DW {
+    TYPE_S16 MSW;
+    TYPE_U16 LSW;
+} TYPE_DW;
+
+typedef union _u_32 {
+    uint32 w;
+    struct {
+        uint8 h_32;
+        uint8 h_24;
+        uint8 l_16;
+        uint8 l_8;
+    } b;
+} TYPE_u32;
+
+typedef union _u_32_bit {
+    uint32 w;
+    struct {
+        uint16 count;
+        uint16 scan_done_pend : 1,
+               data_normal_flag : 1,
+               baseline_int_flag :1,
+               cal_finsh_flag : 1,
+               adjust_done_peng : 1,
+               reserved : 11;
+    } b;
+} TYPE_U32_BIT;
+
+typedef enum {
+    TK_INIT = 0,
+    ADJUST_DONE,
+    DATA_INIT_DONE,
+    SCAN_DONE,
+    RE_ADJUST_DONE,
+} TYPE_ENUM_STA;
+
+typedef struct {
+    int16 b[3];               // 分子多项式的系数Numerator
+    int16 a[2];               // 分母多项式的系数Denominator
+    int16 fixed_point_num;    // 移位bit数
+} TYPE_BIQUAD_FILTER;
+
+struct hgtk_algor{
+    uint8                    __tk_long_key_flag;
+    uint8                    __tk_ch_inc_flag;
+    uint8                    __tk_mult_confirm_cnt;
+    uint8                    __tk_noise_confirm_cnt;
+    uint8                    __tk_next;
+    uint8                    __tk_cm_cnt;
+    uint8                    __tk_muli_key_cnt;
+    uint8                    __tk_mult_noise_cnt;
+    int16                    __tk_data_temp;
+    uint16                   __tk_ms_cnt;
+    uint32                   __tk_ch_en;
+    uint32                   __tk_key_debug_flag;
+    uint32                   __tk_key_flag;
+    uint32                   __tk_key_flag_temp;
+    uint32                   __tk_key_data;
+
+    TYPE_DW                  MUL_RES_1 ; // 4byte
+    TYPE_DW                  MUL_RES_2 ;
+    TYPE_DW                  MUL_RES_3 ;
+    TYPE_u32                 UNION_ADDR;
+    TYPE_BIQUAD_FILTER       iir_param;
+    TYPE_ENUM_STA            __tk_run_sta;
+    TYPE_U32_BIT             __tk_flag;
+};
+
+
+struct hgtouchkey_v2 {
+    struct tk_device     dev;
+    uint32               hw;
+    uint32               alg;
+    tk_irq_hdl         	 irq_hdl;
+    uint32               irq_data;
+    uint32               irq_num;
+    uint32               opened:1, dsleep:1, printf_flag:1;
+    uint32               tk_config;
+    struct os_work       tk_kick_work;
+    struct os_work       tk_scan_work;
+    struct hgtk_algor    tk_algori;
+
+#ifdef CONFIG_SLEEP
+    uint32               *bp_regs;
+    uint32               bp_irq_flags;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+};
+
+int32 hgtouchkey_v2_attach(uint32 dev_id, struct hgtouchkey_v2 *touchkey);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/tk/tk_simplify_algorithm.h

@@ -0,0 +1,52 @@
+/**
+  ******************************************************************************
+  * @file    tk_simplify_algorithm.h
+  * @author  TAIXIN-IC Application Team
+  * @version V1.0.0
+  * @date    01-05-2021
+  * @brief   This file contains all the GPIO LL firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * 用户不允许修改
+  *
+  *
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __LIB_TK_ALGORITHM_H
+#define __LIB_TK_ALGORITHM_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "dev/tk/hg_touchkey_v2.h"
+/* Includes ------------------------------------------------------------------*/
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+// 用户不允许修改
+extern void                     __tk_lib_init(struct hgtouchkey_v2 *tk);
+extern int32                     __tk_scan(struct os_work *work);
+extern int32                     __tk_ms_handler(struct os_work *work);
+
+#define __CPU_NOP()  {__NOP(); __NOP(); __NOP(); __NOP();}
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __LIB_TK_ALGORITHM_H__
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/*************************** (C) COPYRIGHT 2021 TAIXIN-IC ***** END OF FILE ****/

sdk/include/dev/uart/hguart_v2.h

@@ -0,0 +1,48 @@
+#ifndef _HGUART_V2_H
+#define _HGUART_V2_H
+#include "hal/uart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define __PSRAM_ADDR_START (0x18800000)
+#define __PSRAM_ADDR_END   (0x18800000 + (8*1024*1024))
+
+struct hguart_v2 {
+    struct uart_device   dev;
+    uint32 hw;
+    uart_irq_hdl         irq_hdl;
+    uint32               irq_data;
+    uint16               irq_num;
+    uint16               opened:1, dsleep:1, use_dma:1;
+    uint32 flag;
+#ifdef CONFIG_SLEEP
+    struct {
+        uint32 con;
+        uint32 baud;
+        uint32 tstadr;
+        uint32 rstadr;
+        uint32 tdmalen;
+        uint32 rdmalen;
+        uint32 dmacon;
+        uint32 rs485_con;
+        uint32 rs485_det;
+        uint32 rs485_tat;
+        uint32 tocon;
+    }bp_regs;
+    uint32               bp_irq_flags;
+    uart_irq_hdl         bp_irq_hdl;
+    uint32               bp_irq_data;
+#endif
+};
+
+
+int32 hguart_v2_attach(uint32 dev_id, struct hguart_v2 *uart);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/dev/uart/hguart_v3.h

@@ -0,0 +1,29 @@
+#ifndef _HGUART_V3_H
+#define _HGUART_V3_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @brief Simple uart operating handle structure
+  * @{
+  */
+struct hguart_v3 {
+    struct uart_device   dev     ;
+    uint32               hw      ;
+    uart_irq_hdl         irq_hdl ;
+    uint32               irq_data;
+    uint16               irq_num ;
+    uint16               opened  ;
+};
+
+
+int32 hguart_v3_attach(uint32 dev_id, struct hguart_v3 *uart);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/uart/hguart_v4.h

@@ -0,0 +1,57 @@
+#ifndef _HGUART_V4_H
+#define _HGUART_V4_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @brief Simple uart operating handle structure
+  * @{
+  */
+struct hguart_v4 {
+  struct uart_device    dev;
+  uint32                hw;
+  uart_irq_hdl          irq_hdl;
+  uint32                irq_data;
+  uint32 				        tx_total_byte;
+  uint32 				        tx_cur_byte;
+  uint8				         *p_tx_buf;
+	struct os_semaphore   sema_tx;
+	struct os_mutex       mutex_tx;
+	struct os_mutex       mutex_rx;
+  uint16                irq_num;
+  uint16                comm_irq_num;
+  uint16                opened    :1,
+                        use_dma   :1,
+                        irq_dma_tx:1,
+                        irq_dma_rx:1,
+                        debug_uart:1,
+                        rs485_set :1,
+                        dsleep    :1;
+#ifdef CONFIG_SLEEP
+    struct {
+      uint32_t con;
+      uint32_t baud;
+      uint32_t tocon;
+      uint32_t dmaadr;
+      uint32_t dmalen;
+      uint32_t dmacon;
+    }bp_regs;
+    uint32               bp_irq_flags;
+    uart_irq_hdl         bp_irq_hdl;
+    uint32               bp_irq_data;
+    struct os_mutex      bp_suspend_lock;
+    struct os_mutex      bp_resume_lock;
+#endif
+};
+
+
+int32 hguart_v4_attach(uint32 dev_id, struct hguart_v4 *uart);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/usb/hgusb11_base.h

@@ -0,0 +1,267 @@
+/*****************************************************************************
+* Module    : usb
+* File      : usb.c
+* Author    :
+* Function  : USB驱动的一些公用模块
+*****************************************************************************/
+#ifndef USB_H
+#define USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//typedef int8 bool;
+
+#define MAX_EP                  2      //最大的EP号
+
+//in IC, in latest FPGA
+#define USB_FIX_BUG_0                    0      //=0,       =1
+#define USB_FIX_BUG_1                    0      //=1,       =1 
+#define USB_FIX_BUG_2                    0      //=0,       =1 
+#define USB_FIX_BUG_3                    0      //=0,       =1 
+#define USB_FIX_BUG_4                    0      //=0,       =1 
+
+#define UCFG2_CNT                       0x2000
+//USB SIE REG(common)
+#define M_FADDR               0x00
+#define M_POWER               0x01
+#define M_INTRTX1             0x02
+#define M_INTRTX2             0x03
+#define M_INTRRX1             0x04
+#define M_INTRRX2             0x05
+#define M_INTRUSB             0x06
+#define M_INTRTX1E            0x07
+#define M_INTRTX2E            0x08
+#define M_INTRRX1E            0x09
+#define M_INTRRX2E            0x0A
+#define M_INTRUSBE            0x0B
+#define M_FRAMENUM1           0x0C
+#define M_FRAMENUM2           0x0D
+#define M_INDEX               0x0E
+#define M_DEVCTL              0x0F
+//USB SIE REG(host & slave)
+#define M_TXMAXP              0x10
+#define M_CSR0                0x11
+#define M_TXCSR1              0x11
+#define M_TXCSR2              0x12
+#define M_RXMAXP              0x13
+#define M_RXCSR1              0x14
+#define M_RXCSR2              0x15
+#define M_COUNT0              0x16
+#define M_RXCOUNT1            0x16
+#define M_RXCOUNT2            0x17
+#define M_TXTYPE              0x18
+#define M_TXINTERVAL          0x19
+#define M_RXTYPE              0x1A
+#define M_RXINTERVAL          0x1B
+
+#define M_FIFOSIZE            0x1F
+
+
+#define M_FIFO0               0x20  //FIFOS for endpoint0
+#define M_FIFO1               0x24  //FIFOS for endpoint1
+#define M_FIFO2               0x28  //FIFOS for endpoint2
+
+/* Interrupt register bit */
+#define M_INTR_SUSPEND          0x01
+#define M_INTR_RESUME           0x02
+#define M_INTR_RESET            0x04
+#define M_INTR_SOF              0x08
+#define M_INTR_CONNECT          0x10
+#define M_INTR_DIS_CONNECT      0x20
+#define M_INTR_SESS_REQ         0x40
+#define M_INTR_VBUS_ERR         0x80
+
+///USB DMA1_CTL/DMA2_CTL
+#define UDC_BUS_ERR            (1<<15)
+#define UDC_MAXPKT_8BYTE(n)    (((n)&0x7F)<<8)
+#define UDC_EP(n)              (((n)&0xF)<<4)
+#define UDC_IE                 (1<<3)
+#define UDC_MODE(n)            (((n)&0x1)<<2)
+#define UDC_DIR_RX             ((0)<<1)
+#define UDC_DIR_TX             ((1)<<1)
+#define UDC_EN                 ((1)<<0)
+
+///UCFG1
+#define DMA4_MASK               (1<<22)
+#define DMA3_MASK               (1<<21)
+#define DMA2_MASK               (1<<20)
+#define DMA1_MASK               (1<<19)
+#define VBUS_Error_MASK         (1<<18)
+#define Sess_Req_MASK           (1<<17)
+#define Discon_MASK             (1<<16)
+#define Conn_MASK               (1<<15)
+#define Reset_MASK              (1<<14)
+#define Resume_MASK             (1<<13)
+#define Suspend_MASK            (1<<12)
+#define EP2TX_MASK              (1<<11)
+#define EP1TX_MASK              (1<<10)
+#define EP0_MASK                (1<<9)
+#define EP2RX_MASK              (1<<8)
+#define EP1RX_MASK              (1<<7)
+#define SOF_MASK                (1<<6)
+
+#define USB_DIF                 (1<<3)
+#define USB_DIM                 (1<<2)
+#define USB_DIP                 (1<<1)
+#define USB_TM1                 (1<<0)      ///0: normal mode  1:testmode, shorter time for simulation
+
+#define USBIE_EN()              //NVIC_EnableIRQ(USB_CTL_IRQn);
+#define USBIE_DIS()             //NVIC_DisableIRQ(USB_CTL_IRQn);
+
+#define USB_REG_CRITICAL_ENTER()  //osMutexWait(usb_reg_lock_id, osWaitForever);  
+#define USB_REG_CRITICAL_EXIT()  //osMutexRelease(usb_reg_lock_id);
+
+//写USB SIE寄存器
+#define write_usb_reg(reg_addr, reg_data)   do {p_dev->usb_hw->SIE##reg_addr = reg_data;} while(0)
+//void write_usb_reg_index(uint8_t index, uint32_t reg_addr, uint8_t reg_data);
+#define write_usb_reg_index(index, reg_addr, reg_data)\
+        do {\
+            USB_REG_CRITICAL_ENTER();\
+            p_dev->usb_hw->SIEM_INDEX = index;\
+            *((volatile uint8_t *)((uint32_t)&p_dev->usb_hw->SIEM_FADDR + reg_addr)) = reg_data;\
+            USB_REG_CRITICAL_EXIT();\
+        } while(0)
+
+
+//读USB SIE寄存器
+#define read_usb_reg(reg_addr)              (p_dev->usb_hw->SIE##reg_addr)
+//uint8_t read_usb_reg_index(uint8_t index, uint32_t reg_addr);
+#define read_usb_reg_index(index, reg_addr, reg_data)\
+        do {\
+            USB_REG_CRITICAL_ENTER();\
+            p_dev->usb_hw->SIEM_INDEX = index;\
+            reg_data = *((volatile uint8_t *)((uint32_t)&p_dev->usb_hw->SIEM_FADDR + reg_addr));\
+            USB_REG_CRITICAL_EXIT();\
+        } while(0)
+
+
+
+
+//USB当前状态机
+enum {
+    USB_DEFAULT_STATE,
+    USB_ADDRESS_STATE,
+    USB_CONFIG_STATE
+};
+
+//EP0状态机
+enum {
+    IDLE_STATE,
+    TRANSER_OVER_STATE,
+    TRANSFERING_STATE,
+    RECEIVING_STATE
+};
+
+//接收者
+enum {
+    REQUEST_TO_DEVICE,
+    REQUEST_TO_INTERFACE,
+    REQUEST_TO_ENDPOINT
+};
+
+//设备描述符
+enum {
+    DEVICE_DESCRIPTOR = 1,
+    CONFIGURATION_DESCRIPTOR,
+    STRING_DESCRIPTOR,
+    INTERFACE_DESCRIPTOR,
+    ENDPOINT_DESCRIPTOR,
+    DEVICE_QUALIFIER_DESCRIPTOR,
+//    OTHER_SPEED_CONFIG_DESCRIPTOR,  USB 1.1没有该选项
+
+    HID_REPORT = 0x22,
+};
+
+//Feature Selector
+enum {
+    ENDPOINT_STALL,
+    REMOTE_WAKEUP,
+    TEST_MODE
+};
+
+//检测模式
+enum {
+    USB_CHECK_HOST,         //尝试主机检测
+    USB_CHECK_OTG,          //尝试OTG检测，是否连接PC
+    USB_STABLE_HOST,        //已成功检测为USB主机
+    USB_STABLE_DEVICE,      //已成功检测为USB设备
+};
+
+//返回值
+enum {
+    USB_CONNECTED_NONE,     //未连接
+    USB_CONNECTED_PC,       //连接PC，当Device
+    USB_CONNECTED_DEVICE,    //外接U盘，当Host
+};
+
+//USB控制结构体
+struct hgusb11_dev_ctrl {
+    uint8_t error;            //USB通信错误
+
+    struct {
+        uint16_t vid;              //VID
+        uint16_t pid;              //PID
+        uint16_t ver;              //Version
+    } info;
+
+//EP0接收的命令
+    struct {
+        uint8_t rtype;
+        uint8_t request;
+        uint16_t value;
+        uint16_t index;
+        uint16_t length;
+    } cmd;
+
+    uint8_t reserved[2];
+};
+
+struct hgusb11_dev_chk {
+    uint8_t check_mode;
+    uint8_t check_cnt;
+    uint8_t check_delay;
+} ;
+
+
+#define     BYTE0(n)            ((uint8_t)((uint16_t)(n)))
+#define     BYTE1(n)            ((uint8_t)(((uint16_t)(n))>>8))
+#define     BYTE2(n)            ((uint8_t)(((uint16_t)(((uint32_t)(n))>>8))>>8))
+#define     BYTE3(n)            ((uint8_t)(((uint16_t)(((uint32_t)(n))>>16))>>8))
+
+#define     LOAD_U32B(p)        ((((volatile uint8_t *)(p))[0]<<24) | (((volatile uint8_t *)(p))[1]<<16) | (((volatile uint8_t *)(p))[2]<<8) | (((volatile uint8_t *)(p))[3]<<0))
+#define     LOAD_U32L(p)        ((((volatile uint8_t *)(p))[0]<<0)  | (((volatile uint8_t *)(p))[1]<<8)  | (((volatile uint8_t *)(p))[2]<<16)| (((volatile uint8_t *)(p))[3]<<24))
+#define     LOAD_U16B(p)        ((((volatile uint8_t *)(p))[0]<<8) | (((volatile uint8_t *)(p))[1]<<0))
+#define     LOAD_U16L(p)        ((((volatile uint8_t *)(p))[0]<<0) | (((volatile uint8_t *)(p))[1]<<8))
+
+#define SAVE_U32B(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE3(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE2(num); \
+                                ((volatile uint8_t *)(p))[2] = BYTE1(num); \
+                                ((volatile uint8_t *)(p))[3] = BYTE0(num); \
+                            } while(0)
+
+#define SAVE_U32L(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE0(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE1(num); \
+                                ((volatile uint8_t *)(p))[2] = BYTE2(num); \
+                                ((volatile uint8_t *)(p))[3] = BYTE3(num); \
+                            } while(0)
+
+#define SAVE_U16B(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE1(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE0(num); \
+                            } while(0)
+
+#define SAVE_U16L(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE0(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE1(num); \
+                            } while(0)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/usb/hgusb11_dev_api.h

@@ -0,0 +1,229 @@
+#ifndef USB_DEV_API_H
+#define USB_DEV_API_H
+
+/// include & define here
+#include "hal/usb_device.h"
+#include "dev/usb/hgusb11_base.h"
+#include "dev/usb/hgusb11_dev_ep0.h"
+
+#define USB_DEV_DEBUG_ERR_ENABLE           0
+#if USB_DEV_DEBUG_ERR_ENABLE
+#define USB_DEV_ERR_PRINTF(fmt, args...)               os_printf(fmt, ##args)
+#else
+#define USB_DEV_ERR_PRINTF(fmt, args...)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// extern declare functions here
+
+enum hgusb11_flags {
+    HGUSB11_FLAGS_READY,
+};
+
+struct hgusb11_hw_dma_st {
+    __IO uint32_t EP_TXSTARTADR;
+    __IO uint32_t EP_RXSTARTADR;
+    __IO uint32_t EP_TXLEN;
+    __IO uint32_t EP_RXLEN;
+} ;
+
+struct hgusb11_hw_dma_end {
+    __I  uint32_t EP_TXADR;
+    __I  uint32_t EP_RXADR;
+} ;
+
+/**
+  * @brief USB2.0
+  */
+
+struct hgusb11_dev_hw {
+    /* SIE common reg : 0x0 ~ 0xf */
+    __IO uint8_t  SIEM_FADDR;
+    __IO uint8_t  SIEM_POWER;
+    __IO uint8_t  SIEM_INTRTX1;
+    __IO uint8_t  SIEM_INTRTX2;
+    __IO uint8_t  SIEM_INTRRX1;
+    __IO uint8_t  SIEM_INTRRX2;
+    __IO uint8_t  SIEM_INTRUSB;
+    __IO uint8_t  SIEM_INTRTX1E;
+    __IO uint8_t  SIEM_INTRTX2E;
+    __IO uint8_t  SIEM_INTRRX1E;
+    __IO uint8_t  SIEM_INTRRX2E;
+    __IO uint8_t  SIEM_INTRUSBE;
+    __IO uint8_t  SIEM_FRAMENUM1;
+    __IO uint8_t  SIEM_FRAMENUM2;
+    __IO uint8_t  SIEM_INDEX;
+    __IO uint8_t  SIEM_DEVCTL;
+
+    /* SIE indexed reg : 0x10 ~ 0x1f */
+    __IO uint8_t  SIEM_TXMAXP;
+    __IO uint8_t  SIEM_TXCSR1;
+    __IO uint8_t  SIEM_TXCSR2;
+    __IO uint8_t  SIEM_RXMAXP;
+    __IO uint8_t  SIEM_RXCSR1;
+    __IO uint8_t  SIEM_RXCSR2;
+    __IO uint8_t  SIEM_RXCOUNT1;
+    __IO uint8_t  SIEM_RXCOUNT2;
+    __IO uint8_t  SIEM_TXTYPE;
+    __IO uint8_t  SIEM_TXINTERVAL;
+    __IO uint8_t  SIEM_RXTYPE;
+    __IO uint8_t  SIEM_RXINTERVAL;
+    uint8_t  SIEreserved0[3];
+    __IO uint8_t  SIEM_FIFOSIZE;
+
+    /* SIE common reg : 0x20 ~ 0x2f */
+    __IO uint8_t  SIEM_FIFO0;
+    uint8_t  SIEreserved1[3];
+    __IO uint8_t  SIEM_FIFO1;
+    uint8_t  SIEreserved2[3];
+    __IO uint8_t  SIEM_FIFO2;
+    uint8_t  SIEreserved3[3 + 4];
+
+    uint8_t  rsv0[0x200 - 0x30];
+
+    /* DMA common reg */
+    __IO uint32_t DMA_INT;         ///0x200
+    __IO uint32_t DMA1_CTL;
+    __IO uint32_t DMA1_ADDR;
+    __IO uint32_t DMA1_CNT;
+    uint32_t rsv1;
+    __IO uint32_t DMA2_CTL;
+    __IO uint32_t DMA2_ADDR;
+    __IO uint32_t DMA2_CNT;
+    uint32_t rsv2;
+    __IO uint32_t DMA3_CTL;
+    __IO uint32_t DMA3_ADDR;
+    __IO uint32_t DMA3_CNT;
+    uint32_t rsv3;
+    __IO uint32_t DMA4_CTL;
+    __IO uint32_t DMA4_ADDR;
+    __IO uint32_t DMA4_CNT;
+
+    uint32_t rsv4[0x100 / 4 - 16];
+
+    /* CPU common reg */
+    __IO uint32_t UCFG0;         ///0x300
+    __IO uint32_t UCFG1;
+    __IO uint32_t UCFG2;
+    __IO uint32_t UCFG3;
+
+
+    __IO uint32_t EP_STATUS;
+    __IO uint32_t EP_KICK;
+    __IO uint32_t EP_CTL;
+    uint32_t rsv5;
+    __IO uint32_t EP0_TXSTARTADR;
+    __IO uint32_t EP0_RXSTARTADR;
+    __IO uint32_t EP0_TXLEN;
+    uint32_t rsv6;
+    __IO uint32_t EP1_TXSTARTADR;
+    __IO uint32_t EP1_RXSTARTADR;
+    __IO uint32_t EP1_TXLEN;
+    __IO uint32_t EP1_RXLEN;
+
+    __IO uint32_t EP2_TXSTARTADR;
+    __IO uint32_t EP2_RXSTARTADR;
+    __IO uint32_t EP2_TXLEN;
+    __IO uint32_t EP2_RXLEN;
+
+    __I uint32_t  EP0_TXADR;
+    __I uint32_t  EP0_RXADR;
+
+    __I uint32_t  EP1_TXADR;
+    __I uint32_t  EP1_RXADR;
+
+    __I uint32_t  EP2_TXADR;
+    __I uint32_t  EP2_RXADR;
+
+} ;
+
+struct hgusb11_dev {
+    struct usb_device       dev;
+    struct hgusb11_dev_hw *usb_hw;
+    long                    flags;
+    usbdev_irq_hdl          irq_hdl;
+    struct os_mutex         tx_lock;
+    struct os_semaphore     tx_done;
+    uint32                  irq_num;
+    uint32                  sof_irq_num;
+    uint8                  *rx_buff;
+    uint32                  rx_len;
+    uint32                  opened;
+    uint32                  irq_data;
+    struct usb_device_cfg   cfg;
+    struct os_task          ep0_task;
+    struct os_semaphore     ep0_sema;
+
+    /* basic */
+    struct hgusb11_dev_chk     usb_chk;
+    struct hgusb11_dev_ctrl    usb_ctrl;
+    struct hgusb11_dev_info    usb_dev;
+    struct hgusb11_audio_ctrl  usb_audio_ctl;
+    uint32_t                usb_dma_int;
+    uint8_t                 dev_type;
+    uint8_t                 usb_exit ;
+    uint8_t                 usb_dev_flag ;
+    uint8_t                 usb_ep0buf[66];
+    uint8_t                 usb_ep0_rxbuf[66];
+    uint8_t                 usb_device_descriptor[18];
+    uint8_t                 usb_device_qualifier[10];
+    uint8_t                 usb_config_all_descriptor[512];
+
+    uint16_t                usb_vid;    /*  */
+    uint16_t                usb_pid;    /*  */
+};
+
+/* hgusb11_base */
+void hgusb11_switch_otg(struct hgusb11_dev *p_dev);
+void hgusb11_switch_host(struct hgusb11_dev *p_dev);
+void hgusb11_switch_stable_host(struct hgusb11_dev *p_dev);
+void hgusb11_switch_stable_device(struct hgusb11_dev *p_dev);
+void hgusb11_switch_stable_otg(struct hgusb11_dev *p_dev);
+uint8_t hgusb11_connected(struct hgusb11_dev *p_dev);
+uint8_t hgusb11_connected_do(struct hgusb11_dev *p_dev);
+void hgusb11_intr_dis(struct hgusb11_dev *p_dev);
+void hgusb11_suspend(struct hgusb11_dev *p_dev);
+void hgusb11_resume(struct hgusb11_dev *p_dev);
+void hgusb11_init_globle(struct hgusb11_dev *p_dev);
+void hgusb11_dev_remote_wakeup(struct hgusb11_dev *p_dev);
+
+
+
+/* hgusb11_dev_ep0 */
+uint8_t hgusb11_dev_init(struct hgusb11_dev *p_dev);
+void hgusb11_dev_ep0_func(struct hgusb11_dev *p_dev);
+void hgusb11_dev_intr_init_b(struct hgusb11_dev *p_dev);
+void hgusb11_dev_exit(struct hgusb11_dev *p_dev);
+void hgusb11_dev_reset(struct hgusb11_dev *p_dev);
+
+
+
+/* hgusb11_dev_api */
+int32 hgusb11_dev_attach(uint32 dev_id, struct hgusb11_dev *p_dev);
+void hgusb11_dev_irq(struct hgusb11_dev *p_dev);
+bool hgusb11_dev_ep_rx_kick(struct hgusb11_dev *p_dev, uint8_t ep, uint32_t addr, uint32_t len);
+bool hgusb11_dev_ep_tx_kick(struct hgusb11_dev *p_dev, uint8_t ep, uint32_t addr, uint32_t len);
+void hgusb11_dev_ep_set_rxrdy(struct hgusb11_dev *p_dev, uint8_t ep);
+void hgusb11_dev_ep_set_txrdy(struct hgusb11_dev *p_dev, uint8_t ep);
+void hgusb11_dev_hw_init(struct hgusb11_dev *p_dev);
+uint32_t hgusb11_dev_ep_get_rx_len(struct hgusb11_dev *p_dev, uint8_t ep);
+uint32_t hgusb11_dev_ep_get_tx_len(struct hgusb11_dev *p_dev, uint8_t ep);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /* USB_DEV_API_H */

sdk/include/dev/usb/hgusb11_dev_ep0.h

@@ -0,0 +1,66 @@
+/*****************************************************************************
+ * Module    : usb
+ * File      : usb_dev.h
+ * Author    :
+ * Function  : USB Device驱动的一些定义
+ *****************************************************************************/
+#ifndef USB_DEV_H
+#define USB_DEV_H
+
+#include "typesdef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_REQUEST_DIRECTION           (p_dev->usb_ctrl.cmd.rtype & 0x80)
+#define USB_REQUEST_TYPE                (p_dev->usb_ctrl.cmd.rtype & 0x60)
+#define USB_REQUEST_RECIPIENT           (p_dev->usb_ctrl.cmd.rtype & 0x1f)
+#define USB_REQUEST_ENDPOINT            BYTE0(p_dev->usb_ctrl.cmd.index)
+#define USB_REQUEST_FEATURE_SELECTOR    (p_dev->usb_ctrl.cmd.value)
+#define USB_REQUEST_DESCRIPTOR_TYPE     BYTE1(p_dev->usb_ctrl.cmd.value)
+#define USB_REQUEST_DESCRIPTOR_INDEX    BYTE0(p_dev->usb_ctrl.cmd.value)
+#define USB_REQUEST_LENGTH              (p_dev->usb_ctrl.cmd.length)
+
+
+struct hgusb11_dev_info {
+    uint8_t type;                        //设备类型
+    uint8_t set_addr;                    //设地址
+    uint8_t cfg_value;                   //Config Value, 用于Set Config与Get Config
+    uint8_t cur_state;                   //USB当前状态机
+    uint8_t ep0_state;                   //EP0的状态机
+    uint8_t ep0_pkt;                     //EP0包大小
+    uint8_t *ep0_ptr;                    //当前发送指针
+    uint16_t ep0_len;                    //当前发送剩余
+    uint8_t isoc_tx_interface;           //ISOC，MIC发送的接口
+    uint8_t isoc_tx_enable;              //ISOC使能
+    uint8_t isoc_tx_enable_int;          //在中断中配置ISOC使能
+
+    volatile uint8_t ep1_tx_stall;       //ep1 tx stall标志
+    volatile uint8_t ep1_rx_stall;       //ep1 rx stall标志
+    volatile uint8_t ep1_pipe_stall;     //ep1 Stall的标志
+    volatile uint8_t ep2_tx_stall;       //ep1 tx stall标志
+    volatile uint8_t ep2_rx_stall;       //ep1 rx stall标志
+    volatile uint8_t ep2_pipe_stall;     //ep1 Stall的标志
+} ;
+
+struct hgusb11_audio_ctrl {
+    uint8_t speaker_mute;
+    uint8_t mic_mute;
+    uint8_t volume;
+/*
+    uint8_t *adc_root;
+    uint8_t *adc_end;
+    uint8_t *adc_ptr;
+    int16_t adc_cnt;
+    int16_t adc_total;
+    int8_t mic_speed;
+*/
+} ;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/usb/hgusb11_dev_tbl.h

@@ -0,0 +1,37 @@
+/*****************************************************************************
+ * Module    : usb
+ * File      : usb_dev_tbl.h
+ * Author    : 
+ * Function  : USB驱动的一些常量表的申明
+ *****************************************************************************/
+#ifndef USB_DEV_TBL_H
+#define USB_DEV_TBL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+     
+    
+extern const uint8_t tbl_usb_device_descriptor[18];
+extern const uint8_t tbl_usb_config_all_descriptor_gen[9];
+extern const uint8_t tbl_usb_config_all_descriptor_wifi[23];
+extern const uint8_t tbl_usb_config_all_descriptor_mass[23];
+extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_head[19];
+extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_speaker[31];
+extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_mic[30];
+extern const uint8_t tbl_usb_config_all_descriptor_speaker_stream[52];
+extern const uint8_t tbl_usb_config_all_descriptor_mic_stream[52];
+extern const uint8_t tbl_usb_config_all_descriptor_hid[25];
+extern const uint8_t tbl_usb_hid_report_descriptor[33];
+extern const uint8_t tbl_usb_language_id[4];
+extern const uint8_t tbl_usb_str_manufacturer[16];
+extern const uint8_t tbl_usb_str_product[28];
+extern const uint8_t tbl_usb_str_serial_number[30];
+extern const uint8_t tbl_scsi_inquiry_data[36];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

sdk/include/dev/usb/hgusb20_v1_base.h

@@ -0,0 +1,179 @@
+/*****************************************************************************
+* Module    : usb
+* File      : usb.c
+* Author    :
+* Function  : USB驱动的一些公用模块
+*****************************************************************************/
+#ifndef USB20_H
+#define USB20_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+
+
+
+
+
+
+//typedef int8 bool;
+
+
+#define USBIE_EN()              //NVIC_EnableIRQ(USB_CTL_IRQn);
+#define USBIE_DIS()             //NVIC_DisableIRQ(USB_CTL_IRQn);
+
+#define USB_REG_CRITICAL_ENTER()  int32 ie = disable_irq();
+#define USB_REG_CRITICAL_EXIT()   enable_irq(ie); 
+
+
+
+
+
+
+//USB当前状态机
+enum {
+    USB_DEFAULT_STATE,
+    USB_ADDRESS_STATE,
+    USB_CONFIG_STATE
+};
+
+//EP0状态机
+enum {
+    IDLE_STATE,
+    TRANSER_OVER_STATE,
+    TRANSFERING_STATE,
+    RECEIVING_STATE,
+    RECEIV_OVER_STATE,
+};
+
+//接收者
+enum {
+    REQUEST_TO_DEVICE,
+    REQUEST_TO_INTERFACE,
+    REQUEST_TO_ENDPOINT
+};
+
+//设备描述符
+enum {
+    DEVICE_DESCRIPTOR = 1,
+    CONFIGURATION_DESCRIPTOR,
+    STRING_DESCRIPTOR,
+    INTERFACE_DESCRIPTOR,
+    ENDPOINT_DESCRIPTOR,
+    DEVICE_QUALIFIER_DESCRIPTOR,
+//    OTHER_SPEED_CONFIG_DESCRIPTOR,  USB 1.1没有该选项
+    INTERFACE_ASSOCIATION_DESCRIPTOR = 11,
+
+    HID_REPORT = 0x22,
+
+    BOS_DEVICE_DESCRIPTOR = 0xF,
+
+    WCID_DEVICE_DESCRIPTOR = 0xEE,    
+};
+
+//Feature Selector
+enum {
+    ENDPOINT_STALL,
+    REMOTE_WAKEUP,
+    TEST_MODE
+};
+
+//检测模式
+enum {
+    USB_CHECK_HOST,         //尝试主机检测
+    USB_CHECK_OTG,          //尝试OTG检测，是否连接PC
+    USB_STABLE_HOST,        //已成功检测为USB主机
+    USB_STABLE_DEVICE,      //已成功检测为USB设备
+};
+
+//返回值
+enum {
+    USB_CONNECTED_NONE,     //未连接
+    USB_CONNECTED_PC,       //连接PC，当Device
+    USB_CONNECTED_DEVICE,    //外接U盘，当Host
+};
+
+//USB控制结构体
+struct hgusb20_dev_ctrl {
+//EP0接收的命令
+    struct {
+        uint8_t rtype;
+        uint8_t request;
+        uint16_t value;
+        uint16_t index;
+        uint16_t length;
+    } cmd;
+    
+    uint8_t bus_high_speed      : 1,
+            auto_tx_null_pkt    : 1,   //ep1 tx null packet for non-potocol xfer
+            reserved_bit0       : 1,
+            error               : 1,
+            reserved_bit : 4;
+    
+    uint8_t test_mode;
+    
+    uint8_t reg_usb_csr0;
+    uint8_t set_addr;
+    
+//        struct {
+//            uint16_t vid;              //VID
+//            uint16_t pid;              //PID
+//            uint16_t ver;              //Version
+//        } info;
+};
+
+struct hgusb20_dev_chk {
+    uint8_t check_mode;
+    uint8_t check_cnt;
+    uint8_t check_delay;
+} ;
+
+
+#define     BYTE0(n)            ((uint8_t)((uint16_t)(n)))
+#define     BYTE1(n)            ((uint8_t)(((uint16_t)(n))>>8))
+#define     BYTE2(n)            ((uint8_t)(((uint16_t)(((uint32_t)(n))>>8))>>8))
+#define     BYTE3(n)            ((uint8_t)(((uint16_t)(((uint32_t)(n))>>16))>>8))
+
+#define     LOAD_U32B(p)        ((((volatile uint8_t *)(p))[0]<<24) | (((volatile uint8_t *)(p))[1]<<16) | (((volatile uint8_t *)(p))[2]<<8) | (((volatile uint8_t *)(p))[3]<<0))
+#define     LOAD_U32L(p)        ((((volatile uint8_t *)(p))[0]<<0)  | (((volatile uint8_t *)(p))[1]<<8)  | (((volatile uint8_t *)(p))[2]<<16)| (((volatile uint8_t *)(p))[3]<<24))
+#define     LOAD_U16B(p)        ((((volatile uint8_t *)(p))[0]<<8) | (((volatile uint8_t *)(p))[1]<<0))
+#define     LOAD_U16L(p)        ((((volatile uint8_t *)(p))[0]<<0) | (((volatile uint8_t *)(p))[1]<<8))
+
+#define SAVE_U32B(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE3(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE2(num); \
+                                ((volatile uint8_t *)(p))[2] = BYTE1(num); \
+                                ((volatile uint8_t *)(p))[3] = BYTE0(num); \
+                            } while(0)
+
+#define SAVE_U32L(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE0(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE1(num); \
+                                ((volatile uint8_t *)(p))[2] = BYTE2(num); \
+                                ((volatile uint8_t *)(p))[3] = BYTE3(num); \
+                            } while(0)
+
+#define SAVE_U16B(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE1(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE0(num); \
+                            } while(0)
+
+#define SAVE_U16L(p, num)   do { \
+                                ((volatile uint8_t *)(p))[0] = BYTE0(num); \
+                                ((volatile uint8_t *)(p))[1] = BYTE1(num); \
+                            } while(0)
+
+
+
+void hgusb20_write_usb_reg_index(uint32_t usb_dev_hw,uint32_t index,uint32_t reg_addr,uint32_t reg_data);
+void hgusb20_read_usb_reg_index(uint32_t usb_dev_hw,uint32_t index,uint32_t reg_addr,uint32_t *reg_data);
+uint32_t hgusb20_write_usb_reg(uint32_t usb_dev_hw,uint8_t reg_addr,uint8_t reg_data);
+uint32_t hgusb20_read_usb_reg(uint32_t usb_dev_hw,uint32_t reg_addr);
+void hgusb20_send_empty_packet(uint32_t usb_dev_hw);
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/usb/hgusb20_v1_dev_api.h

@@ -0,0 +1,657 @@
+#ifndef USB20_DEV_API_H
+#define USB20_DEV_API_H
+
+/// include & define here
+#include "sys_config.h"
+#include "hal/usb_device.h"
+#include "dev/usb/hgusb20_v1_base.h"
+#include "dev/usb/hgusb20_v1_dev_ep0.h"
+#include "osal/work.h"
+#include "osal/event.h"
+#include "lib/common/rbuffer.h"
+
+#define USB_DEV_DEBUG_ERR_ENABLE           0
+#if USB_DEV_DEBUG_ERR_ENABLE
+#define USB_DEV_ERR_PRINTF(fmt, args...)               os_printf(fmt, ##args)
+#else
+#define USB_DEV_ERR_PRINTF(fmt, args...)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* speed flags only host */
+#define HGUSB20_FLAGS_HIGH_SPEED      (0)
+#define HGUSB20_FLAGS_FULL_SPEED      (30)
+
+#define USBDMA_RX_FLAG_RXING        BIT(0)
+#define USBDMA_RX_FLAG_OVERFLOW     BIT(1)
+#define USBDMA_RX_FLAG_FIFOFULL     BIT(2)
+
+#define USBDMA_TX_FLAG_TXING        BIT(0)
+#define USBDMA_TX_FLAG_NULLPACKET   BIT(1)
+#define USBDMA_TX_FLAG_MODE1        BIT(2)
+
+typedef struct {
+    uint8 ep0_pkt;
+    uint8 max_lun;
+    uint8 bulk_rx;
+    uint8 bulk_tx;
+    uint16 time_out;
+    uint8 stall;
+    uint8 if_mass;
+    uint8 res;
+    uint16 rx_pkt_size;
+    uint16 tx_pkt_size;
+} type_usb_host;
+
+
+typedef struct {
+    uint8 offset;
+    uint8 rx_len;
+    uint16 rx_total;
+} type_ep0_ptr;
+
+struct hgusb20_os_dev {
+    struct os_task          ep0_task __attribute__((aligned(4)));
+    struct os_task          ep0_hub_task __attribute__((aligned(4)));
+    struct os_task          ep0_usb_connect_task __attribute__((aligned(4)));
+    struct os_semaphore     ep0_sema __attribute__((aligned(4)));
+    struct os_mutex         tx_lock __attribute__((aligned(4)));
+    struct os_semaphore     tx_done __attribute__((aligned(4)));
+    struct os_semaphore     hub_sema __attribute__((aligned(4)));
+    struct os_semaphore     hub_finish_sema __attribute__((aligned(4)));
+    uint32 dev_type; //device mode   1:udisk     2:uvc
+};
+
+typedef enum {
+    UDISK_DEV = 1,
+    UVC_DEV
+}USB_DEV_TYPE;
+
+
+struct hgusb20_dev {
+    struct usb_device       dev;
+    void                   *usb_hw;
+    struct hgusb20_os_dev  *usb_os_msg;
+    long                    flags;
+    usbdev_irq_hdl          irq_hdl;
+    uint8                  *rx_buff;
+    uint32                  rx_len;
+    uint32                  irq_data;
+    
+    struct usb_device_cfg  *cfg;
+    uint8                  *p_com_desc;              /* usb descriptor */
+    uint8                  *p_config_desc;              /* usb descriptor */
+    uint16                  vid;                        /* usb device VID */
+    uint16                  pid;                        /* usb device PID */
+
+    /* basic */
+    struct hgusb20_dev_chk     usb_chk;
+    struct hgusb20_dev_ctrl    usb_ctrl;
+    struct hgusb20_dev_info    usb_dev;
+    type_ep0_ptr               ep0_ptr;
+    type_usb_host              usb_host;
+    
+    volatile uint32          usb_dma_int;  /* dma intr status reg value */
+//    volatile uint32          usb_rxdma_addr;  /* rx dma start addr */
+//    volatile uint32          usb_rx_len_limit; /* rx req len */
+//    volatile uint16_t          usb_rxdma_len; /* latest packet len */
+
+    volatile uint8           usb_rxdma_flag;
+    volatile uint8           usb_txdma_flag;
+    volatile uint16_t          usb_tx_total_len;    /*  */
+
+    uint8                    ep_irq_num;
+    uint8                    dma_irq_num;
+    uint16_t                   usb_dev_flag;
+    
+    uint8                    usb_ep0_sbuf[8] __attribute__((aligned(4))); 
+    /* case : usb continue send 64byte data, 2nd data NAK */
+    uint8                    usb_ep0_rxbuf[68 + 68] __attribute__((aligned(4))); 
+
+    uint8                    usb_ep0_sta[8];
+    RBUFFER_DEF_R(rb, uint8);
+    struct os_work             ep0_work;
+    /* trx_lock[00:15] for EP_IN  */
+    /* trx_lock[15:31] for EP_OUT */
+    struct os_event            trx_lock;
+    struct os_event            trx_done;
+#ifdef CONFIG_SLEEP
+    uint32                  sys_regs[2];
+#endif
+};
+
+/* hgusb20_base */
+/** 
+  * @brief  read usb register
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : 
+  * @param  addr    : register address offset
+  * @param  data    : data return 
+  * @return         : TRUE or FLASE
+  * @note  
+  */
+bool hgusb20_read_reg(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 *data);
+/** 
+  * @brief  write usb register
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : 
+  * @param  addr    : register address offset
+  * @param  data    : data return 
+  * @return         : TRUE or FLASE
+  * @note  
+  */
+bool hgusb20_write_reg(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 data);
+
+void hgusb20_switch_otg(struct hgusb20_dev *p_dev);
+void hgusb20_switch_host(struct hgusb20_dev *p_dev);
+void hgusb20_switch_stable_host(struct hgusb20_dev *p_dev);
+void hgusb20_switch_stable_device(struct hgusb20_dev *p_dev);
+void hgusb20_switch_stable_otg(struct hgusb20_dev *p_dev);
+void hgusb20_intr_dis(struct hgusb20_dev *p_dev);
+uint8_t hgusb20_connected(struct hgusb20_dev * p_dev);
+
+uint32 hgusb20_get_rx_crc_error_cnt(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb ep rx data kick
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : [1,2]
+  * @param  addr    : data address 
+  * @param  len     : data length 
+  * @return         : TRUE or FLASE
+  * @note  use for host & device
+  */
+bool hgusb20_ep_rx_kick(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 len);
+/** 
+  * @brief  usb ep tx data kick
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : [1,2]
+  * @param  addr    : data address 
+  * @param  len     : data length 
+  * @return         : TRUE or FLASE
+  * @note  use for host & device
+  */
+bool hgusb20_ep_tx_kick(struct hgusb20_dev *p_dev, uint8 ep, uint32 addr, uint32 len);
+bool hgusb20_ep_rx_abort(struct hgusb20_dev *p_dev, uint8 ep);
+bool hgusb20_ep_tx_abort(struct hgusb20_dev *p_dev, uint8 ep);
+
+/** 
+  * @brief  usb ep get rx data length from dma 
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : [1,2]
+  * @return         : rx data length
+  * @note  use for host & device
+  */
+uint32 hgusb20_ep_get_dma_rx_len(struct hgusb20_dev *p_dev, uint8 ep);
+/** 
+  * @brief  usb ep get rx data length from sie 
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : [1,2]
+  * @return         : rx data length
+  * @note  use for host & device
+  */
+uint32 hgusb20_ep_get_sie_rx_len(struct hgusb20_dev *p_dev, uint8 ep);
+/** 
+  * @brief  usb ep get tx data length  
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : [1,2]
+  * @return         : tx data length (same with len in hgusb20_ep_tx_kick)
+  * @note  use for host & device
+  */
+uint32 hgusb20_ep_get_tx_len(struct hgusb20_dev *p_dev, uint8 ep);
+
+
+/** 
+  * @brief  check if usb device online
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  *         - TRUE    : online.
+  *         - FALSE   : not online.
+  * @note             : For USB Host
+  */
+bool hgusb20_is_device_online(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  check if usb host online
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  *         - TRUE    : online.
+  *         - FALSE   : not online.
+  * @note             : For USB Device
+  */
+bool hgusb20_is_host_online(struct hgusb20_dev *p_dev);
+int32 hgusb20_is_host_mode(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  suspend usb device .
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return          : 
+  * @note            : For USB Host
+  */
+void hgusb20_host_suspend(struct hgusb20_dev *p_dev);
+/** 
+  * @brief  resume usb device .
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return          : 
+  * @note            : For USB Host
+  */
+void hgusb20_host_resume(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb host set address(host address)
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  addr     : 
+  * @return 
+  * @note   use after usb_host_set_address(device address) cmd
+  */
+void hgusb20_set_address(struct hgusb20_dev *p_dev, uint8 addr);
+
+/** 
+  * @brief  usb host bus reset request
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note   
+  */
+uint8 hgusb20_host_reset(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  remote_wakeup usb host .
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return          : 
+  * @note            : For USB Device
+  */
+void hgusb20_dev_remote_wakeup(struct hgusb20_dev *p_dev);
+
+
+/* hgusb20_dev_api */
+/** 
+  * @brief  attach usb device
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  dev_id  : 
+  * @return         : err_code
+  * @note  
+  */
+int32 hgusb20_dev_attach(uint32 dev_id, struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  init usb to device mode .
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  *         - RET_OK  : Successfully.
+  *         - RET_ERR : Failed.
+  * @note
+  */
+uint8 hgusb20_dev_init(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  exit usb to device mode .
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  *         - RET_OK  : Successfully.
+  *         - RET_ERR : Failed.
+  * @note
+  */
+void hgusb20_dev_exit(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device ep0 tx data stage handle: 
+  *         addr = p_dev->ep0_ptr; len = p_dev->ep0_len;
+  *         1、if buf is not NULL（first packet）, update p_dev->ep0_ptr & p_dev->ep0_len
+  *         2、TX one packet 
+  *         3、data end if len != ep0_pkt
+  *         4、auto called repeat when last tx data done while (p_dev->usb_dev.ep0_state == TRANSER_OVER_STATE)
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  buf      : valid when first packet, set NULL when other packet
+  * @param  len      : valid when first packet, set 0 when other packet.
+  * @return 
+  *         - RET_OK  : Successfully.
+  *         - RET_ERR : Failed.
+  * @note             : weak function, Users can use a strong statement function replace the weak statement function.
+  */
+bool hgusb20_dev_ep0_tx(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
+/** 
+  * @brief  usb device ep0 tx one packet only 
+  */
+bool hgusb20_dev_ep0_tx_rtt(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
+bool hgusb20_dev_ep0_tx_abort(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb ep rx data stage handle
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep      : [1,2]
+  * @param  addr    : data address 
+  * @param  len     : data length 
+  * @return         : TRUE or FLASE
+  * @note  use for host & device
+  */
+bool hgusb20_dev_ep0_rx(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
+/** 
+  * @brief  usb device ep0 rx one packet only 
+  */
+bool hgusb20_dev_ep0_rx_rtt(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
+bool hgusb20_dev_ep0_rx_abort(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device clear_stall_flag
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note
+  */
+void hgusb20_dev_clear_stall_flag(struct hgusb20_dev *p_dev);
+/** 
+  * @brief  usb device tx zero-packet & rx packet to usb_ep0_rxbuf
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note
+  */
+bool hgusb20_dev_ep0_clrrx_pkt0(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device bus reset
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note
+  */
+void hgusb20_dev_reset(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device stall_ep
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  epnum    : epnum, set BIT(7) when tx endpiont.
+  * @return 
+  * @note
+  */
+void hgusb20_dev_stall_ep(struct hgusb20_dev *p_dev, uint8 epnum);
+/** 
+  * @brief  usb device clear stall_ep
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  epnum    : epnum, set BIT(7) when tx endpiont.
+  * @return 
+  * @note
+  */
+void hgusb20_dev_clear_ep(struct hgusb20_dev *p_dev, uint8 epnum);
+/** 
+  * @brief  usb device ep reset all endpiont in ep_cfg
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note
+  */
+void hgusb20_dev_bot_reset(struct hgusb20_dev *p_dev);
+/** 
+  * @brief  usb device cmd handle ：get descriptor
+  *         1、kick next rx to p_dev->usb_ep0_rxbuf
+  *         2、tx data(addr = buf, length = len)
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return         : TRUE or FLASE
+  * @note
+  */
+bool hgusb20_dev_ep0_descriptor(struct hgusb20_dev *p_dev, void *buf, uint16_t len);
+/** 
+  * @brief  usb device standard cmd handle 
+  *         1、
+  *         2、handle DATA(IN or OUT)
+  *         3、STATUS(zero-len packet)  
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  *                    these function is called by func "hgusb20_dev_ep0_standard"
+  */
+
+ uint8 hgusb20_dev_cfg_desc_prepare(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_get_descriptor(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_get_configuration(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_set_configuration(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_get_interface(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_set_interface(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_set_address(struct hgusb20_dev *p_dev, uint8_t address);
+__weak bool hgusb20_dev_ep0_get_status(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_clr_feature(struct hgusb20_dev *p_dev);
+__weak bool hgusb20_dev_ep0_set_feature(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device ep0 setup handle (standard cmd)
+  *         1、
+  *         2、handle DATA(IN or OUT)
+  *         3、STATUS(zero-len packet)
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return         : TRUE or FLASE
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  *                    the function is called by func "hgusb20_dev_ep0_request"
+  */
+__weak bool hgusb20_dev_ep0_standard(struct hgusb20_dev *p_dev);
+//__weak bool hgusb20_dev_ep0_class_reset(struct hgusb20_dev *p_dev);
+//__weak bool hgusb20_dev_ep0_class_get_lun(struct hgusb20_dev *p_dev);
+//__weak bool hgusb20_dev_ep0_audio_sample_ctrl(struct hgusb20_dev *p_dev);
+//__weak bool hgusb20_dev_ep0_audio_mute_ctrl(struct hgusb20_dev *p_dev);
+//__weak bool hgusb20_dev_ep0_audio_volume_ctrl(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device ep0 setup handle (class cmd)
+  *         1、
+  *         2、handle DATA(IN or OUT)
+  *         3、STATUS(zero-len packet)
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return         : TRUE or FLASE
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  *                    the function is called by func "hgusb20_dev_ep0_request"
+  */
+__weak bool hgusb20_dev_ep0_class(struct hgusb20_dev *p_dev);
+/** 
+  * @brief  usb device ep0 setup handle (vendor cmd)
+  *         1、
+  *         2、handle DATA(IN or OUT)
+  *         3、STATUS(zero-len packet)
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return         : TRUE or FLASE
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  *                    the function is called by func "hgusb20_dev_ep0_request"
+  */
+__weak bool hgusb20_vendor_cmd(struct hgusb20_dev *p_dev);
+/** 
+  * @brief  usb device ep0 setup handle
+  *         1、
+  *         2、handle DATA(IN or OUT)
+  *         3、STATUS(zero-len packet)
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return         : TRUE or FLASE
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  *                    
+  */
+__weak bool hgusb20_dev_ep0_request(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device config state indication
+  *         1、 p_dev->usb_dev.cur_state = USB_CONFIG_STATE;
+  *         2、p_dev->flags |= BIT(HGUSB20_FLAGS_READY);
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return         : 
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  *                    
+  */
+__weak void hgusb20_dev_state_config(struct hgusb20_dev *p_dev);
+
+///** 
+//  * @brief  usb device ep0 interrupt handle
+//  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+//  * @return 
+//  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+//  *                    !! Don't recommend  a strong statement function
+//  */
+//__weak void hgusb20_dev_ep0_func(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb device endpoint init & deinit
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_addr    : ep->ep_desc->bEndpointAddress
+  * @param  max_pkt_size    :ep->ep_desc->wMaxPacketSize
+  * @param  attributes    : ep->ep_desc->bmAttributes.
+  * @return         : 
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  */
+void hgusb20_dev_ep_init(struct hgusb20_dev *p_dev, uint8 ep_addr, uint16 max_pkt_size, uint8 attributes);
+void hgusb20_dev_ep_deinit(struct hgusb20_dev *p_dev, uint8 ep_addr);
+/** 
+  * @brief  usb device IN data kick （ tx data ）
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep       : ep_num = ep->ep_desc->bEndpointAddress & 0x7F
+  * @param  buff     : word aligned
+  * @param  len      : 
+  * @param  sync     : 1: sync(recommand)  0: async
+  * @return          : error code
+  * @note            : weak function, Users can use a strong statement function replace the weak statement function.
+  */
+int32 hgusb20_dev_write(struct usb_device *usb,  uint8 ep, uint8 *buff, uint32 len, uint8 sync);
+int32 hgusb20_dev_read(struct usb_device *p_usb_d,  uint8 ep, uint8 *buff, uint32 len, uint8 sync);
+int32 hgusb20_dev_close(struct usb_device *p_usb_d);
+
+
+
+/* hgusb20_host_api */
+
+/** 
+  * @brief  attach usb host
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  dev_id  : 
+  * @return         : err_code
+  * @note  
+  */
+int32 hgusb20_host_attach(uint32 dev_id, struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  init usb to host mode .
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  *         - RET_OK  : Successfully.
+  *         - RET_ERR : Failed.
+  * @note
+  */
+bool hgusb20_host_init(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb host ep0 cmd request
+  *         1. SETUP: send setup packet , addr = p_dev->usb_ctrl.cmd, len = 8
+  *         2. DATA : addr = p_buf, len = p_dev->usb_ctrl.cmd.length for rx/tx(p_dev->usb_ctrl.cmd.rtype & USB_DIR_IN)
+            3. STA  : if DATA tx null packet else rx null packet
+  * @param  p_dev   : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  p_buf   : data buffer.
+  * @return         : TRUE or FLASE
+  * @note   Another choice user can realize function by calling "hgusb20_host_ep0_setup" & "hgusb20_host_ep0_rx" & "hgusb20_host_ep0_tx"
+  */
+bool usb_host_ep0_request(struct hgusb20_dev *p_dev, uint8 *pBuf);
+
+/** 
+  * @brief  usb host ep0 send SETUP packet
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note
+  */
+uint32_t hgusb20_host_ep0_setup(struct hgusb20_dev *p_dev);
+
+/** 
+  * @brief  usb host ep0 send IN packet & request a data packet
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @return 
+  * @note   addr = p_dev->usb_ep0_buf, len = p_dev->ep0_ptr.rx_len
+  */
+uint32_t hgusb20_host_ep0_rx(struct hgusb20_dev *p_dev, uint8 *pBuf, bool first_pkt);
+/** 
+  * @brief  usb host ep0 send IN packet & request a data packet
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  len      : 
+  * @return 
+  * @note   addr = p_dev->usb_ep0_buf, len = p_dev->ep0_ptr.rx_len
+  */
+uint32_t hgusb20_host_ep0_tx(struct hgusb20_dev *p_dev, uint8 *pBuf, uint8 len);
+
+/** 
+  * @brief  usb host endpiont init
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_host  : ep pipe of host
+  * @param  ep_dev   : ep pipe of device
+  * @param  ep_type  : USB_ENDPOINT_XFERTYPE_MASK @ref usb_ch9.h
+  * @param  max_pkt_size : 
+  * @return 
+  * @note 
+  */
+void hgusb20_host_tx_ep_init(struct hgusb20_dev *p_dev, uint8 ep_host, uint8 ep_dev, uint8 ep_type, uint16 max_pkt_size);
+void hgusb20_host_rx_ep_init(struct hgusb20_dev *p_dev, uint8 ep_host, uint8 ep_dev, uint8 ep_type, uint16 max_pkt_size);
+
+/** 
+  * @brief  hgusb20_host_clear_data_toggle
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_num   : [1,2]
+  * @param  ep_type  : EndpointDir BIT[7]：IN = 1, OUT = 0
+  * @return          : 
+  * @note  
+  */
+void hgusb20_host_clear_data_toggle(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
+
+/** 
+  * @brief  hgusb20_host_flush_fifo
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_num   : [1,2]
+  * @param  ep_type  : EndpointDir BIT[7]：IN = 1, OUT = 0
+  * @return          : 
+  * @note  
+  */
+void hgusb20_host_flush_fifo(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
+
+/** 
+  * @brief  usb host get stall status 
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_num   : [0,2]
+  * @param  ep_type  : EndpointDir BIT[7]：IN = 1, OUT = 0
+  * @return          : TRUE or FLASE
+  * @note  
+  */
+bool hgusb20_host_is_rx_stall(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
+/** 
+  * @brief  usb host get xact error status (continous no response three times)
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_num   : [0,2]
+  * @param  ep_type  : EndpointDir BIT[7]：IN = 1, OUT = 0
+  * @return          : TRUE or FLASE
+  * @note  
+  */
+bool hgusb20_host_is_xact_err(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
+/** 
+  * @brief  usb host get nak timeout status 
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_num   : [0,2]
+  * @param  ep_type  : EndpointDir BIT[7]：IN = 1, OUT = 0
+  * @return          : TRUE or FLASE
+  * @note  
+  */
+bool hgusb20_host_is_nak_timeout(struct hgusb20_dev *p_dev, uint8 ep_num, uint8 ep_type);
+/** 
+  * @brief  usb host get rx crc status 
+  * @param  p_dev    : hgusb20_dev use @ref dev_get() function to get the handle.
+  * @param  ep_num   : [0,2]
+  * @return          : TRUE or FLASE
+  * @note  
+  */
+bool hgusb20_host_is_crc_err(struct hgusb20_dev *p_dev, uint8 ep_num);
+
+void hgusb20_host_reset_phy(struct hgusb20_dev * p_dev);
+
+int32 hgusb20_host_set_interval(struct hgusb20_dev *p_dev, uint8_t ep_host, uint8_t mode, uint32_t interval);
+void hgusb20_host_reset_ep_rxcsr(struct hgusb20_dev *p_dev, uint8 ep_num);
+void hgusb20_host_reset_ep_txcsr(struct hgusb20_dev *p_dev, uint8 ep_num);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /* USB_DEV_API_H */

sdk/include/dev/usb/hgusb20_v1_dev_ep0.h

@@ -0,0 +1,69 @@
+/*****************************************************************************
+ * Module    : usb
+ * File      : usb_dev.h
+ * Author    :
+ * Function  : USB Device驱动的一些定义
+ *****************************************************************************/
+#ifndef USB20_DEV_H
+#define USB20_DEV_H
+
+#include "typesdef.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_REQUEST_DIRECTION           (p_dev->usb_ctrl.cmd.rtype & 0x80)
+#define USB_REQUEST_TYPE                (p_dev->usb_ctrl.cmd.rtype & 0x60)
+#define USB_REQUEST_RECIPIENT           (p_dev->usb_ctrl.cmd.rtype & 0x1f)
+#define USB_REQUEST_ENDPOINT            BYTE0(p_dev->usb_ctrl.cmd.index)
+#define USB_REQUEST_TEST_INDEX          BYTE1(p_dev->usb_ctrl.cmd.index)
+#define USB_REQUEST_FEATURE_SELECTOR    (p_dev->usb_ctrl.cmd.value)
+#define USB_REQUEST_DESCRIPTOR_TYPE     BYTE1(p_dev->usb_ctrl.cmd.value)
+#define USB_REQUEST_DESCRIPTOR_INDEX    BYTE0(p_dev->usb_ctrl.cmd.value)
+#define USB_REQUEST_LENGTH              (p_dev->usb_ctrl.cmd.length)
+
+
+struct hgusb20_dev_info {
+    //uint8_t type;                        //设备类型
+    //uint8_t set_addr;                    //设地址
+    //uint8_t cfg_value;                   //Config Value, 用于Set Config与Get Config
+    uint8_t cur_state : 4,                   //USB当前状态机
+            ep0_state : 4;                   //EP0的状态机
+    uint8_t ep0_pkt;                     //EP0包大小
+    uint8_t *ep0_ptr;                    //当前发送指针
+    uint16_t ep0_len;                    //当前发送剩余
+    uint8_t *ep0_ptr_rx;                    //当前发送指针
+    uint16_t ep0_len_rx;                    //当前发送剩余
+
+    volatile uint8_t ep_tx_stall;       //ep1 tx stall标志
+    volatile uint8_t ep_rx_stall;       //ep1 rx stall标志
+    
+//    uint8_t  ep_num_rx;
+//    uint8_t  ep_num_tx;
+//    uint8_t  ep_rx_type;
+//    uint8_t  ep_tx_type;
+//    uint16_t max_pkt_rx[MAX_EP];
+//    uint16_t max_pkt_tx[MAX_EP];
+} ;
+
+struct hgusb20_audio_ctrl {
+    uint8_t speaker_mute;
+    uint8_t mic_mute;
+    uint8_t volume;
+/*
+    uint8_t *adc_root;
+    uint8_t *adc_end;
+    uint8_t *adc_ptr;
+    int16_t adc_cnt;
+    int16_t adc_total;
+    int8_t mic_speed;
+*/
+} ;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/dev/usb/hgusb_dev_tbl.h

@@ -0,0 +1,51 @@
+/*****************************************************************************
+ * Module    : usb
+ * File      : usb_dev_tbl.h
+ * Author    : 
+ * Function  : USB驱动的一些常量表的申明
+ *****************************************************************************/
+#ifndef USB_DEV_TBL_H
+#define USB_DEV_TBL_H
+
+#define WCID_VENDOR_CODE                0xA0
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+    
+extern const uint8_t tbl_usb_device_descriptor[18];
+extern const uint8_t tbl_usb_config_all_descriptor_gen[9];
+extern const uint8_t tbl_usb_config_all_descriptor_wifi[23];
+extern const uint8_t tbl_usb_config_all_descriptor_mass[23];
+extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_head[19];
+extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_speaker[31];
+extern const uint8_t tbl_usb_config_all_descriptor_audio_ctrl_mic[30];
+extern const uint8_t tbl_usb_config_all_descriptor_speaker_stream[52];
+extern const uint8_t tbl_usb_config_all_descriptor_mic_stream[52];
+extern const uint8_t tbl_usb_config_all_descriptor_hid[25];
+extern const uint8_t tbl_usb_hid_report_descriptor[33];
+extern const uint8_t tbl_usb_language_id[4];
+extern const uint8_t tbl_usb_str_manufacturer[16];
+extern const uint8_t tbl_usb_str_product[28];
+extern const uint8_t tbl_usb_str_serial_number[30];
+extern const uint8_t tbl_scsi_inquiry_data[36];
+
+/* bcdUSB = 2.0 */
+extern const uint8_t tbl_winusb_device_descriptor[18];
+extern const uint8_t tbl_winusb_compatible_id_feature_descriptor[40];
+extern const uint8_t tbl_winncm_compatible_id_feature_descriptor[40];
+extern const uint8_t tbl_rndis_compatible_id_feature_descriptor[40];
+extern const uint8_t tbl_winusb_device_interface_guids[142];
+extern const uint8_t tbl_net_device_interface_guids[142];
+extern const uint8_t tbl_winncm_class_request_get_ntb_params[28];
+extern const uint8_t tbl_winusb20_wcid_descriptor_set[162];
+/* bcdUSB >= 2.01 , best 2.1 */
+extern const uint8_t tbl_winusb20_wcidbos[33];
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

sdk/include/dev/usb/uvc_host.h

@@ -0,0 +1,619 @@
+#ifndef _UVC_HOST_H
+#define _UVC_HOST_H
+
+#include "typesdef.h"
+#include "list.h"
+
+typedef  enum  
+{
+	UVC_DESCRIPTOR_UNDEFINED=0,
+	UVC_HEADER,
+	UVC_INPUT_TERMINAL,
+	UVC_OUTPUT_TERMINAL,
+	UVC_SELECTOR_UNIT,
+	UVC_PROCESSING_UNIT,
+	UVC_EXTENSION_UNIT,
+	UVC_ENCODING_UNIT
+}VC_Subtype;
+
+typedef  enum  
+{
+	VS_UNDEFINED=0,
+	VS_INPUT_HEADER,
+	VS_OUTPUT_HEADER,
+	VS_STILL_IMAGE_FRAME,
+	VS_FORMAT_UNCOMPRESSED,
+	VS_FRAME_UNCOMPRESSED,
+	VS_FORMAT_MJPEG,
+	VS_FRAME_MJPEG,
+	Reserved,
+	Reserved1,
+	VS_FORMAT_MPEG2TS,
+	Reserved2,
+	VS_FORMAT_DV,
+	VS_COLORFORMAT,
+	Reserved3,
+	Reserved4,
+	VS_FORMAT_FRAME_BASED,
+	VS_FRAME_FRAME_BASED,
+	VS_FORMAT_STREAM_BASED,
+	VS_FORMAT_H264,
+	VS_FRAME_H264,
+	VS_FORMAT_H264_SIMULCAST
+}VS_Subtype;
+
+// Standard Configuration Descriptor
+typedef struct
+{
+    uint8  length;                // Size of descriptor in uint8
+    uint8  type;                  // Configuration
+    uint16 t_length;              // Total length
+    uint8  num_intf;              // Number of interface
+    uint8  cv;                    // bConfigurationValue
+    uint8  index;                 // iConfiguration
+    uint8  attr;                  // Configuration Characteristic
+    uint8  max_power;             // Power config
+} SCFG_DESC, *P_SCFG_DESC;
+
+
+
+// Standard Interface Descriptor
+typedef struct
+{
+    uint8 length;
+    uint8 type;
+    uint8 num;
+    uint8 alt_tring;
+    uint8 end_points;
+    uint8 iclass;
+    uint8 sub;
+    uint8 proto;
+    uint8 index;
+} SINTF_DESC, *P_INTF_DESC;
+
+// Standard Device Descriptor
+typedef struct
+{
+    uint8  length;
+    uint8  descriptor_type;
+    uint16 bcd_usb;
+    uint8  device_class;
+    uint8  device_subclass;
+    uint8  device_protocol;
+    uint8  maxpacket_size0;
+    uint16 id_vendor;
+    uint16 id_product;
+    uint16 bcd_device;
+    uint8  manufacturer;
+    uint8  product;
+    uint8  serial_number;
+    uint8  num_configurations;
+} SDEV_DESC, *P_DEV_DESC;
+
+// Standard EndPoint Descriptor
+typedef struct
+{
+    uint8  length;
+    uint8  type;
+    uint8  ep_addr;
+    uint8  attr;
+    uint16 pay_load;               // low-speed this must be 0x08
+    uint8  interval;
+} SEP_DESC, *P_EP_DESC;
+
+struct VC_PROCESS{
+	uint8  bLength;
+	uint8  bDescriptorType;
+	uint8  bDescriptorSubtype;
+	uint8  bUnitID;
+	uint8  bSourceID;
+	uint16 wMaxMultiplier;
+	uint8 bControlSize;
+	uint32 bmControls;
+	uint8 iProcessing;
+}__attribute__((packed));
+
+typedef struct{
+	uint8	bLength;                           
+	uint8	bDescriptorType;                   
+	uint8	bDescriptorSubtype;                
+	uint8	bFrameIndex;                   
+	uint8	bmCapabilities;                   
+	uint16	wWidth;                           
+	uint16	wHeight;      
+
+}VS_FRAME;
+
+typedef struct{
+	uint8	bLength;                           
+	uint8	bDescriptorType;                   
+	uint8	bDescriptorSubtype;                
+	uint8	bFrameIndex;   
+	uint8 	bNumFrameDescriptors;
+}VS_FORMAT;
+
+typedef struct{
+	uint8	bLength;                           
+	uint8	bDescriptorType;                   
+	uint8	bDescriptorSubtype;                
+	uint8	bNumFormats;                     
+}VS_HEAD;
+
+#define INTERFACE_Type                   	0x24
+#define STRAME_O_CONTORL             		0x04
+#define ENDPOINT_DESC             		    0x05
+
+#define VS_FAME_TYPE_MAXNUM    			    20
+#define VS_FORMAT_TYPE_MAXNUM 			    2
+
+#define __INTFS_STACK__		32
+#define IS_UVC_JPEG   						1   
+
+#define USB_DEV_UVC_CLASS 	0xef 
+#define USB_DEV_HUB_CLASS	0X09
+
+
+#define UVC_SET_REQ				0x21
+#define UVC_GET_REQ				0xA1
+#define UVC_SET_CUR				0x01
+#define UVC_GET_CUR				0x81
+#define UVC_GET_MIN				0x82
+#define UVC_GET_MAX				0x83
+#define UVC_GET_RES				0x84
+#define UVC_GET_LEN				0x85
+#define UVC_GET_INFO			    0x86
+#define UVC_GET_DEF				0x87
+#define UVC_CLASS    0x0e
+#define UAC_CLASS    0x01
+#define UVC_VGA 	 1
+#define UVC_720P     2
+
+
+typedef struct{
+	uint8 DesLen;
+	uint8 DescriptorType;
+	uint8 Subtype;
+	uint8 control_endpoint;
+	VS_HEAD	    vs_head;
+	VS_FRAME   vs_frame[VS_FAME_TYPE_MAXNUM];
+	VS_FORMAT vs_format[VS_FORMAT_TYPE_MAXNUM];
+	uint8 vs_frame_num;
+	uint8 vs_format_num;
+	uint32 intfs_count;
+	uint32 edpt_count;
+	SINTF_DESC intfs[__INTFS_STACK__];
+	SEP_DESC edpt[__INTFS_STACK__]; 
+	
+	struct VC_PROCESS  vc_process;
+	uint8 control_intfs;
+}UVC_DES;
+
+typedef struct{
+	uint8  ep;
+	uint8  eptpye;
+	uint16 len; 
+}EP_DES;
+
+     
+typedef struct
+{
+	uint8 ctyp;
+	
+	uint8 cv;
+	uint8 epctl;
+	uint8 ctl_intfs;
+	uint8 ctl_altset;
+	uint8 ctl_pload;
+	uint8 ctl_ttyp;
+	uint8 ctl_interval;
+	
+	uint8 epstrm;
+	uint8 strm_intfs;
+	uint8 strm_altset;
+	uint16 strm_pload;
+	uint8 strm_ttyp;
+	uint8 strm_interval;
+}UVCDEV;
+
+typedef struct{
+	uint8 ctl_intfs;
+	uint32 process_ctl;
+	uint8 process_unitID;
+}UVC_PROCESS;
+
+typedef struct {
+	uint8 ctl_val;
+	int16 info;
+	int16 max;
+	int16 min;
+	uint16 res;
+	int16 cur;
+}UVC_PROC_REQ;
+
+typedef struct{
+	UVC_PROC_REQ brightness;
+	UVC_PROC_REQ contrast;
+	UVC_PROC_REQ hue;
+	UVC_PROC_REQ saturation;
+	UVC_PROC_REQ sharpness;
+	UVC_PROC_REQ gamma;
+	UVC_PROC_REQ white_bal_temp;
+	UVC_PROC_REQ white_bal_comp;
+	UVC_PROC_REQ backlight_comp;
+	UVC_PROC_REQ gain;
+	UVC_PROC_REQ power_line_fre;
+	UVC_PROC_REQ hue_auto;
+	UVC_PROC_REQ white_bal_temp_auto;
+	UVC_PROC_REQ white_bal_comp_auto;
+	UVC_PROC_REQ digital_mult;
+	UVC_PROC_REQ digital_mult_limit;
+	UVC_PROC_REQ ana_video_stan;
+	UVC_PROC_REQ ana_lock_sta;
+	UVC_PROC_REQ contrast_auto;
+}UVC_PROCESS_INFO;
+
+typedef enum {
+	BRIGHTNESS,
+	CONTRAST,
+	HUE,
+	SATURATION,
+	SHARPNESS,
+	GAMMA,
+	WHITE_BAL_TEMP,
+	WHITE_BAL_COMP,
+	BACKLIGHT_COMP,
+	GAIN,
+	POWER_LINE_FRE,
+	HUE_AUTO,
+	WHITE_BAL_TEMP_AUTO,
+	WHITE_BAL_COMP_AUTO,
+	DIGITAL_MULT,
+	DIGITAL_MULT_LIMIT,
+	ANA_VIDEO_STAN,
+	ANA_LOCK_STA,
+	AONTRAST_AUTO
+}UVC_PROCESS_ENUM;
+
+typedef struct{
+	VS_FRAME   vs_frame;
+	VS_FORMAT vs_format;
+}UVC_SLEST;
+
+struct VIDEO_COMMIT
+{
+	uint16 bmhint;
+	uint8 bFormatIndex;
+	uint8 bFrameIndex;
+	uint32 dwFrameInterval;
+	uint16 wKeyFrameRate;
+	uint16 wPFrameRate;
+	uint16 wCompQuality;
+	uint16 wCompWindowSize;
+	uint16 wDelay;
+	uint32 dwMaxVideoFrameSize;
+	uint32 dwMaxPayloadTSize;
+}__attribute__((packed));
+
+
+typedef struct {
+	struct list_head list;
+	uint8 *cpbuff;     //当前写入数据的地址
+	uint8 uvc_head[16];//one pack head data
+	uint8  frame_end;   //frame结束标志，表示USB获取数据结束   0：进行中  1：正常结束    2：异常结束
+	uint32 tgl;        
+	uint32 sta;
+	uint32 state;		//frame状态，0：空闲       	1：正在填充 			 2:可用      3:应用正在使用   
+	uint32 frame_len;  //帧长度
+	uint32 data_len;//one packe data len 
+	uint32 head_len;//one packe head len
+	uint32 re_space;//当前所写的buff剩余空间
+	uint32 frame_counter;
+}UVC_MANAGE;
+
+
+typedef struct {
+	struct list_head list;			//BLANK块节点互连
+	uint32 frame_counter;				//此数据块代表的frame号
+	uint32 blank_len;					//blank可使用的数据长度，最后一个数据块非满外，其他都满
+	uint32 re_space;					//当前blank剩下多少空间可填
+	uint8  blank_loop;                 //blank计数，每一帧都从0开始增加，便于后面重组
+	uint8  *buf_ptr;					//数据块指针
+	uint8  busy;						//blank块状态，0：空闲    1：正在填充或者发送    		2:可用      
+}UVC_BLANK;
+
+typedef struct{
+	uint8 addr;
+	uint8 int_endpoint;
+	uint8 port_num;
+	uint8 connect_port;
+}HUB_manage;
+
+
+enum usb_host_io_cmd {
+    USB_HOST_IO_CMD_RESET,	   //usb复位
+    USB_HOST_IO_CMD_SET_CUR,
+    USB_HOST_IO_CMD_GET_CUR,
+    USB_HOST_IO_CMD_SET_IDX,   //1:VGA, 2:720
+};
+
+struct uvc_user_arg
+{
+	void *usb_dev;
+	uint32_t state;	//0:可以创建任务   1:正在运行 2:等待任务删除
+	uint32_t uvc_format;	
+};
+
+
+/****************uac****************/
+typedef enum
+{
+	AC_UNDEFINED=0,
+	AC_HEADER_DES,
+	AC_INPUT_DES,
+	AC_OUTPUT_DES,
+	AC_MIXER_DES,
+	AC_SELECTOR_DES,
+	AC_FEATURE_DES
+}AC_Subtype;
+
+typedef enum
+{
+	AS_UNDEFINED=0,
+	AS_General_Des,
+	AS_Format_Des
+}AS_Subtype;
+
+typedef enum
+{
+	USB_Undefined = 0x0100,
+	USB_streaming = 0x0101,
+	USB_vendor_specific = 0x01FF,
+	Input_Undefined = 0x0200,
+	Microphone = 0x0201,
+	Desktop_microphone = 0x0202,
+	Output_Undefined = 0x0300,
+	Speaker = 0x0301,
+	Headphones = 0x0302
+}AC_Terminal_Types;
+
+typedef struct{
+    uint8  bLength;
+    uint8  bDescriptorType;
+    uint8  bDescriptorSubtype;
+    uint8  bTerminalID;
+    uint16 wTerminalType;
+    uint8  bAssocTerminal;
+    uint8  bNrChannels;
+    uint16 wChannelConfig;
+    uint8  iChannelNames;
+    uint8  iTerminal;
+}AC_INPUT;
+
+typedef struct{
+	uint8 bLength;
+	uint8 bDescriptorType;
+    uint8 bDescriptorSubtype;
+	uint8 bUnitID;
+	uint8 bSourceID;
+	uint8 bControlSize;
+	uint8 bmaControls[2];
+}AC_FEATURE;
+
+typedef struct{
+    uint8  bLength;
+    uint8  bDescriptorType;
+    uint8  bDescriptorSubtype;
+    uint8  bTerminalID;
+    uint16 wTerminalType;
+    uint8  bAssocTerminal;
+    uint8  bSourceID;
+    uint8  iTerminal;	
+}AC_OUTPUT;
+
+typedef struct{
+    uint8  bLength;
+    uint8  bDescriptorType;
+    uint8  bInterfaceNumber;
+    uint8  bAlternateSetting;
+    uint8  bNumEndpoints;
+    uint8  bInterfaceClass;
+    uint8  bInterfaceSubClass;
+    uint8  bInterfaceProtocol;
+    uint8  iInterface;	
+}AS_INTERFACE;
+
+typedef struct{
+    uint8  bLength;
+    uint8  bDescriptorType;
+    uint8  bDescriptorSubtype;
+    uint8  bTerminalLink;
+    uint8  bDelay;
+    uint16 wFormatTag;	
+}AS_GENERAL;
+
+typedef struct{
+    uint8  bLength;
+    uint8  bDescriptorType;
+    uint8  bDescriptorSubtype;
+    uint8  bFormatType;
+    uint8  bNrChannels;
+    uint8  bSubframeSize;
+    uint8  bBitResolution;
+    uint8  bSamFreqType;
+    uint32 tSamFreq[4];
+}AS_FORMAT;
+
+typedef struct{
+    uint8  bLength;
+    uint8  bDescriptorType;
+    uint8  bEndpointAddress;
+    uint8  bmAttributes;
+    uint16 wMaxPacketSize;
+    uint8  bInterval;
+    uint8  bRefresh;
+    uint8  bSynchAddress;	
+}AS_ENDPOINT;
+
+#define AS_GENERAL_TYPE_MAXNUM    			10
+#define AS_FORMAT_TYPE_MAXNUM 			    10
+
+typedef struct{
+	uint8 DesLen;
+	uint8 DescriptorType;
+	uint8 Subtype;
+	uint8 control_endpoint;
+	uint8 control_interface;
+	AC_INPUT ac_input[3];
+	AC_OUTPUT ac_output[3];
+	AC_FEATURE ac_feature[3];
+	AS_INTERFACE as_interface[4];
+	AS_GENERAL as_general[AS_GENERAL_TYPE_MAXNUM];
+	AS_FORMAT as_format[AS_FORMAT_TYPE_MAXNUM];
+	AS_ENDPOINT as_endpoint[10];
+	uint8 ac_input_num;
+	uint8 ac_feature_num;
+	uint8 ac_output_num;
+	uint8 as_interface_num;
+	uint8 as_general_num;
+	uint8 as_format_num;
+	uint8 as_endpoint_num;
+}UAC_DES;
+
+typedef struct{	
+	uint16 spk_type;
+	uint8 spk_strm_intfs;
+	uint8 spk_strm_altset[4];
+	uint16 spk_fmttag[4];
+	uint8 spk_fmttype[4];
+	uint8 spk_nrchl[4];
+	uint8 spk_fmsize[4];
+	uint8 spk_bitres[4];
+	uint8 spk_samfretype[4];
+	uint8 spk_samfre[4][4];
+	uint8 spk_epstrm[4];
+	uint8 spk_eptype[4];
+	uint16 spk_strm_pload[4];
+	uint8 spk_feaunitID;
+	uint8 spk_feaunit_ctl[2];
+	int16 spk_max_vol;
+	int16 spk_min_vol;
+	
+	uint16 mic_type;
+	uint8 mic_strm_intfs;
+	uint8 mic_strm_altset[4];
+	uint16 mic_fmttag[4];
+	uint16 mic_fmttype[4];
+	uint8 mic_nrchl[4];
+	uint8 mic_fmsize[4];
+	uint8 mic_bitres[4];
+	uint8 mic_samfretype[4];
+	uint8 mic_samfre[4][4];
+	uint8 mic_epstrm[4];
+	uint8 mic_eptype[4];
+	uint16 mic_strm_pload[4];
+	uint8 mic_feaunitID;
+	uint8 mic_feaunit_ctl[2];
+	int16 mic_max_vol;
+	int16 mic_min_vol;
+
+	uint8 ctl_intfs;
+}UACDEV;
+
+typedef struct{
+	uint8 strm_intfs;
+	uint8 strm_altset;	
+	uint8 epstrm;
+	uint8 eptype;
+	uint16 strm_pload;
+}MICDEV;
+
+typedef struct{
+	uint8 strm_intfs;
+	uint8 strm_altset;	
+	uint8 epstrm;
+	uint8 eptype;
+	uint16 strm_pload;
+}SPKDEV;
+
+typedef struct{
+	struct list_head list;
+	uint8 *data_addr;     //当前写入数据的地址
+	uint32 data_len;
+	uint32 respace_len;
+	uint32 offset;
+	uint8 sta;
+}UAC_MANAGE;
+
+/**********uac************/
+
+#define HUB_STATU_CONNECT (BIT(1))
+#define HUB_STATU_RESTEND (BIT(1))
+/**hub clear feature **/
+#define PORT_CONNECT 0x10
+#define PORT_ENABLE 0X01
+#define CLEAR_PORT_REST 0x14
+/**hub set feature **/
+#define	PORT_POWER 0X08
+#define PORT_REST 0x04
+
+#define UVC_EP              2
+#define HUB_EP              1
+#define UAC_EP              3
+#define UVC2_EP             1
+
+
+#define ISO_HEAD            0
+#define BULK_HEAD           12
+#define UVC_HEAD            BULK_HEAD
+
+
+#define UVC_HOST_NUM        2
+
+void uvc_room_init(void *p_dev);
+void usb_dma_irq(void * dev, uint8_t* uvc_rx_buff, uint8_t uvc_head_res, uint8_t ep_type);
+
+//void usb_host_irq(typedef_usb_t *usb_sw);
+
+void uvc_user();
+
+void uvc_room_init_mjpeg();
+void uvc_room_deinit_mjpeg();
+void uvc_room_init_h264();
+void uvc_room_deinit_h264(void);
+void uvc_reset_dev(uint8_t en);
+void uvc_reset_dev_mjpeg(uint8_t en);
+void uvc_reset_dev_h264(uint8_t en);
+
+void uvc_sema_init();
+void uvc_sema_down(int32 tmo_ms);
+void uvc_sema_up();
+
+
+void uvc_app_user_init();
+void force_reset_uvc_frame();
+
+UVC_MANAGE* get_uvc_message_gloal();
+uint32 get_uvc_frame_len();
+uint8* get_uvc_buf();
+uint8 free_uvc_blank(UVC_BLANK* uvc_b);
+UVC_BLANK* get_uvc_blank();
+
+extern void del_usbmic_frame(UAC_MANAGE *uac_manage);
+extern UAC_MANAGE *get_usbmic_frame(void);
+extern uint32 get_uac_frame_datalen(UAC_MANAGE *uac_manage);
+extern uint8 *get_uac_frame_data(UAC_MANAGE *uac_manage);
+extern void set_uac_frame_datalen(UAC_MANAGE *uac_manage, uint32 len);
+extern UAC_MANAGE *get_usbspk_new_frame(uint8 grab);
+extern void put_usbspk_frame_to_use(UAC_MANAGE *uac_manage);
+extern void set_uac_frame_sta(UAC_MANAGE *uac_manage, uint8 sta);
+extern void usbspk_room_init(uint32_t empty_buf_len);
+extern void usbmic_room_init(void);
+extern void usbmic_dma_irq(void *dev, uint8_t* mic_rx_buff);
+extern void usbspk_dma_irq(void *dev);
+extern void uac_stop(void);
+extern void uac_start(void *dev, uint8_t* mic_rx_buff);
+extern int uvc_ep_bulk_or_isoc();
+extern void force_reset_usbmic_frame();
+extern void force_reset_usbspk_frame();
+
+#endif

sdk/include/dev/vpp/hgvpp.h

@@ -0,0 +1,36 @@
+#ifndef HG_VPP_H
+#define HG_VPP_H
+#include "tx_platform.h"
+#include "list.h"
+#include "dev.h"
+#include "hal/vpp.h"
+
+typedef enum {
+	HSIE_ISR = 0,
+	VSIE_ISR,
+	SCIE_ISR,	
+	LOVIE_ISR,	
+	IPF_OV_ISR,
+	MDPIE_ISR,
+	ITP_OV_ISR,
+	ITP_DONE_ISR,
+	VPP_IRQ_NUM,
+}VPP_IRQ_E;
+ 
+
+struct hgvpp {
+    struct vpp_device   dev;
+    //struct hgdvp_hw     *hw;
+	uint32              hw;
+    vpp_irq_hdl         irq_hdl;
+    uint32              irq_data;
+    uint32              irq_num;
+    uint32              opened:1, use_dma:1, dsleep:1;
+	uint32 *cfg_backup;
+};
+
+
+int32 hgvpp_attach(uint32 dev_id, struct hgvpp *vpp);
+
+#endif
+

sdk/include/dev/wifi/fmac_dev.h

@@ -0,0 +1,31 @@
+#ifndef _FMAC_DEV_H_
+#define _FMAC_DEV_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int32 hgic_fmac_attach(uint32 dev_id, int32 bus_type, const char *fw_data, uint8 reset_io);
+
+int32 fmac_dev_open(struct netdev *ndev);
+int32 fmac_dev_close(struct netdev *ndev);
+int32 fmac_dev_set_work_mode(struct netdev *ndev, char *mode);
+int32 fmac_dev_get_work_mode(struct netdev *ndev, char *buff);//buff size >= 12
+int32 fmac_dev_set_ssid(struct netdev *ndev, char *ssid);
+int32 fmac_dev_get_ssid(struct netdev *ndev, char *buff);//buff size >= 32
+int32 fmac_dev_set_key_mgmt(struct netdev *ndev, char *key_mgmt);
+int32 fmac_dev_get_key_mgmt(struct netdev *ndev, char *buff);//buff size >= 12
+int32 fmac_dev_set_wpa_psk(struct netdev *ndev, char *psk);
+int32 fmac_dev_get_wpa_psk(struct netdev *ndev, char *buff);//buff size >= 64
+int32 fmac_dev_set_bss_bw(struct netdev *ndev, uint8 bss_bw);
+int32 fmac_dev_set_chan_list(struct netdev *ndev, uint16 *chan_list, uint32 count);
+int32 fmac_dev_set_paired_stas(struct netdev *ndev, uint8 *mac_list, uint32 count);
+int32 fmac_dev_enter_sleep(struct netdev *ndev, uint16 sleep, uint32 sleep_ms);
+int32 fmac_dev_ota(struct netdev *ndev);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

sdk/include/dev/xspi/hg_xspi.h

@@ -0,0 +1,39 @@
+#ifndef _HG_XSPI_H_
+#define _HG_XSPI_H_
+#include "hal/spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum hg_xspi_flags {
+    hg_xspi_flags_ready,
+    hg_xspi_flags_suspend,
+};
+
+struct hg_xspi {
+    struct dev_obj          dev;
+    void                   *hw;
+    uint32                  irq_num;
+    //qspi_irq_hdl            irq_hdl;
+    uint32                  irq_data;
+    uint32                  opened;
+    uint32                  flags;
+#ifdef CONFIG_SLEEP
+    uint32                  sys_regs[6];
+    uint32                  ospi_regs[256/4];
+#endif    
+};
+extern struct hg_xspi xspi;
+
+
+
+int32 hg_xspi_attach(uint32 dev_id, struct hg_xspi *p_spi);
+void hg_xspi_sample_offset(uint32 ospi_base, int8 rx_offset, int8 tx_offset);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

sdk/include/dev/xspi/hg_xspi_psram.h

@@ -0,0 +1,158 @@
+/**
+  ******************************************************************************
+  * @file    Libraries/Driver/include/LL/tx_peg_ll_qspi.h
+  * @author  HUGE-IC Application Team
+  * @version V1.0.0
+  * @date    01-07-2019
+  * @brief   This file contains all the QSPI LL firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2019 HUGE-IC</center></h2>
+  *
+  *
+  *
+  ******************************************************************************
+  */ 
+  
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _HG_XSPI_PSRAM_H_
+#define _HG_XSPI_PSRAM_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+     
+/** @addtogroup TX_PEG_StdPeriph_Driver CanesVenatici Driver
+  * @{
+  */
+     
+/** @addtogroup qspi_interface_gr QSPI Driver
+  * @ingroup  TX_PEG_StdPeriph_Driver
+  * @{
+  */ 
+
+/** @addtogroup QSPI_LL_Driver QSPI LL Driver
+  * @ingroup  qspi_interface_gr
+  * @brief Mainly the driver part of the QSPI module, which includes \b QSPI \b Register 
+  * \b Constants, \b QSPI \b Exported \b Constants, \b QSPI \b Exported \b Struct, \b QSPI
+  * \b Data \b transfers \b functions, \b QSPI \b Initialization \b and \b QSPI \b Configuration 
+  * \b And \b Interrupt \b Handle \b function.
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+
+struct psram_attr {
+    uint32 read_mem_opc     : 8,
+           write_mem_opc    : 8,
+           read_reg_opc     : 8,
+           write_reg_opc    : 8;
+    
+    uint32 read_lc      : 4,
+           write_lc     : 4,
+           lc_type      : 1,
+           driver       : 2,
+           rbx_en       : 1,
+           slow_refresh_en : 1,
+           /* 0/1/2/3 for sigle\dual\quad\octal */
+           wire_mode    : 3,
+           ddr_mode     : 1,
+           reserved1    : 7;
+
+    uint32 burst_type   : 1,
+           burst_len    : 15,
+           density_mbyte: 16;
+    
+    uint8  psram_mr[8];
+    
+    /* read-only attr */
+    uint32 vid          : 5,
+           did          : 2,
+           is_good_die  : 1,
+
+           /* 0 ：1.8V, 1:3.3V */
+           voltage_range: 1,
+           refresh_range: 3,
+           /* 0 ：
+            * 1 ：half-sleep
+            * 2 ：deep sleep
+            */
+           ulp_mode     : 4,
+           
+           /* 0 ：slow, 1:fast */
+           self_refresh_speed : 1,
+           ulp_half_sleep_support : 1,
+           rbx_support  : 1,
+           reserved3    : 1,
+           voltage_gear : 4,
+           
+           reserved2    : 8;
+    
+    uint32 page_size : 16,
+           clk_mhz   : 16;
+};
+
+
+struct stig_req {
+    uint32  is_read : 1,
+            addr_len: 3,
+            data_len: 4,
+            cmd     : 8,
+            dummy   : 8,
+            reserved: 8;
+    uint32  addr;
+    void   *p_buf;
+};
+
+enum psram_type {
+    APS1604M_3SQR,
+    APS1604M_DQRA,
+    APS3208K_OKUD,
+    APS6408L_OBMx,
+    APS1604M_3SQR_TXW817_812,
+    SCKW18X128800,
+    SCKM18X032800,
+    PSRAM_TYPE_END,
+};
+
+  
+/***** DRIVER API *****/
+
+
+
+/***** LL API *****/
+
+
+  
+/***** LL API AND DRIVER API *****/
+
+uint8_t psram_init(enum psram_type pt, uint32 clk_hz,uint32 check_size);
+int psram_auto_init();
+void psram_deinit(enum psram_type pt) ;
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif 
+
+/*************************** (C) COPYRIGHT 2023 HUGE-IC ***** END OF FILE *****/

sdk/include/devid.h

@@ -0,0 +1,178 @@
+#ifndef _HUGEIC_DEV_ID_H_
+#define _HUGEIC_DEV_ID_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    HG_UART0_DEVID = 1,
+    HG_UART1_DEVID,
+    HG_UART2_DEVID,
+    HG_UART3_DEVID,
+    HG_UART4_DEVID,
+    HG_UART5_DEVID,
+    HG_UART6_DEVID,
+    HG_UART7_DEVID,
+    HG_UART8_DEVID,
+    HG_UART9_DEVID,
+    HG_USBDEV_DEVID,
+    HG_HWAES0_DEVID,
+    HG_HWAES1_DEVID,
+    HG_SPI0_DEVID,
+    HG_SPI1_DEVID,
+    HG_SPI2_DEVID,
+    HG_SPI3_DEVID,
+    HG_SPI4_DEVID,
+    HG_SPI5_DEVID,
+    HG_SPI6_DEVID,
+    HG_SPI7_DEVID,
+    HG_SPI8_DEVID,
+    HG_SPI9_DEVID,
+    HG_DMAC_DEVID,
+    HG_I2C0_DEVID,
+    HG_I2C1_DEVID,
+    HG_I2C2_DEVID,
+    HG_I2C3_DEVID,
+    HG_I2C4_DEVID,
+    HG_I2C5_DEVID,
+    HG_I2C6_DEVID,
+    HG_I2C7_DEVID,
+    HG_I2C8_DEVID,
+    HG_I2C9_DEVID,
+    HG_GPIOA_DEVID,
+    HG_GPIOB_DEVID,
+    HG_GPIOC_DEVID,
+    HG_GPIOD_DEVID,
+    HG_GPIOE_DEVID,
+    HG_WDT_DEVID,
+    HG_SDIOSLAVE_DEVID,
+    HG_TIMER0_DEVID,
+    HG_TIMER1_DEVID,
+    HG_TIMER2_DEVID,
+    HG_TIMER3_DEVID,
+    HG_TIMER4_DEVID,
+    HG_TIMER5_DEVID,
+    HG_TIMER6_DEVID,
+    HG_TIMER7_DEVID,
+    HG_TIMER8_DEVID,
+    HG_TIMER9_DEVID,
+    HG_MIPI_DEVID,
+    HG_GMAC_DEVID,
+    HG_M2MDMA_DEVID,
+    HG_FLASH0_DEVID,
+    HG_FLASH1_DEVID,
+    HG_FLASH2_DEVID,
+    HG_FLASH3_DEVID,
+    HG_CRC_DEVID,
+    HG_ETHPHY0_DEVID,
+    HG_ETHPHY1_DEVID,
+    HG_ETH_MDIOBUS0_DEVID,
+    HG_ETH_MDIOBUS1_DEVID,
+    HG_DVP_DEVID,
+    HG_LCDC_DEVID,
+    HG_JPG0_DEVID,
+    HG_JPG1_DEVID,
+    HG_VPP_DEVID,
+    HG_PRC_DEVID,
+    HG_OF_DEVID,
+    HG_SCALE1_DEVID,
+	HG_SCALE2_DEVID,
+	HG_SCALE3_DEVID,		
+    HG_QSPI_DEVID,
+    HG_XSPI_DEVID,
+    HG_SDIOHOST_DEVID,
+    HG_PDM0_DEVID,
+    HG_PDM1_DEVID,
+    HG_PDM2_DEVID,
+    HG_PDM3_DEVID,
+    HG_LED0_DEVID,
+    HG_LED1_DEVID,
+    HG_LED2_DEVID,
+    HG_LED3_DEVID,
+    HG_WIFI0_DEVID,
+    HG_WIFI1_DEVID,
+    HG_WIFI2_DEVID,
+    HG_WIFI3_DEVID,
+    HG_LED_TIMER0_DEVID,
+    HG_LED_TIMER1_DEVID,
+    HG_LED_TIMER2_DEVID,
+    HG_LED_TIMER3_DEVID,
+    HG_LED_TIMER4_DEVID,
+    HG_LED_TIMER5_DEVID,
+    HG_LED_TIMER6_DEVID,
+    HG_LED_TIMER7_DEVID,
+    HG_LED_TIMER8_DEVID,
+    HG_LED_TIMER9_DEVID,
+    HG_SUPTMR0_DEVID,
+    HG_SUPTMR1_DEVID,
+    HG_SUPTMR2_DEVID,
+    HG_SUPTMR3_DEVID,
+    HG_SUPTMR4_DEVID,
+    HG_SUPTMR5_DEVID,
+    HG_SUPTMR6_DEVID,
+    HG_SUPTMR7_DEVID,
+    HG_SUPTMR8_DEVID,
+    HG_SUPTMR9_DEVID,
+	HG_SIMTMR0_DEVID,
+    HG_SIMTMR1_DEVID,
+    HG_SIMTMR2_DEVID,
+    HG_SIMTMR3_DEVID,
+    HG_SIMTMR4_DEVID,
+    HG_SIMTMR5_DEVID,
+    HG_SIMTMR6_DEVID,
+    HG_ADC0_DEVID,
+    HG_ADC1_DEVID,
+    HG_ADC2_DEVID,
+    HG_ADC3_DEVID,
+    HG_CAPTURE0_DEVID,
+    HG_CAPTURE1_DEVID,
+    HG_CAPTURE2_DEVID,
+    HG_CAPTURE3_DEVID,
+    HG_PWM0_DEVID,
+    HG_PWM1_DEVID,
+    HG_PWM2_DEVID,
+    HG_PWM3_DEVID,
+    HG_IIS0_DEVID,
+    HG_IIS1_DEVID,
+    HG_IIS2_DEVID,
+    HG_IIS3_DEVID,
+    HG_IIS4_DEVID,
+    HG_IIS5_DEVID,
+    HG_TOUCHKEY0_DEVID,
+    HG_TOUCHKEY1_DEVID,
+    HG_TOUCHKEY2_DEVID,
+    HG_TOUCHKEY3_DEVID,
+    HG_FMAC0_DEVID,
+    HG_FMAC1_DEVID,
+    HG_FMAC2_DEVID,
+    HG_FMAC3_DEVID,
+    HG_SDSPI0_DEVID,
+    HG_SDSPI1_DEVID,
+    HG_RTC_DEVID,
+    HG_AUADC_DEVID,
+    HG_AUDAC_DEVID,
+    HG_AUHS_DEVID,
+    HG_AUALAW_DEVID,
+    HG_AUVAD_DEVID,
+    HG_AUFADE_DEVID,
+    HG_AUEQ_DEVID,
+    HG_SHA_DEVID,
+    HG_USB_HOST_CONTROLLER_DEVID,
+    HG_LTE_RNDIS_DEVID,
+    HG_USB_AT_DEVID,
+    HG_USB_DEV_CONTROLLER_DEVID,
+    HG_USB_DEV_WINUSB_DEVID,
+    HG_USB_DEV_HID_DEVID,
+    HG_USB_DEV_AUDIO_MIC_DEVID,
+    HG_USB_DEV_AUDIO_SPK_DEVID,
+    HG_USB_DEV_ECM_DEVID,
+    HG_USB_DEV_CDC_DEVID,
+    HG_USB_DEV_RNDIS_DEVID,
+} DEV_ID; /**** 只能在后面追加新增，不能在中间插入 ****/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/errno.h

@@ -0,0 +1,532 @@
+#ifndef _TXWSDK_ERRNO_H
+#define _TXWSDK_ERRNO_H
+
+#define _LINUX_ERRNO_H
+#define _LINUX_ERRNO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int errno;
+
+#ifndef MAX_ERRNO
+#define MAX_ERRNO   4095
+#endif
+
+#ifndef EPERM
+#define EPERM        1  /* Operation not permitted */
+#endif
+#ifndef ENOENT
+#define ENOENT       2  /* No such file or directory */
+#endif
+#ifndef ESRCH
+#define ESRCH        3  /* No such process */
+#endif
+#ifndef EINTR
+#define EINTR        4  /* Interrupted system call */
+#endif
+#ifndef EIO
+#define EIO          5  /* I/O error */
+#endif
+#ifndef ENXIO
+#define ENXIO        6  /* No such device or address */
+#endif
+#ifndef E2BIG
+#define E2BIG        7  /* Argument list too long */
+#endif
+#ifndef ENOEXEC
+#define ENOEXEC      8  /* Exec format error */
+#endif
+#ifndef EBADF
+#define EBADF        9  /* Bad file number */
+#endif
+#ifndef ECHILD
+#define ECHILD      10  /* No child processes */
+#endif
+#ifndef EAGAIN
+#define EAGAIN      11  /* Try again */
+#endif
+#ifndef ENOMEM
+#define ENOMEM      12  /* Out of memory */
+#endif
+#ifndef EACCES
+#define EACCES      13  /* Permission denied */
+#endif
+#ifndef EFAULT
+#define EFAULT      14  /* Bad address */
+#endif
+#ifndef ENOTBLK
+#define ENOTBLK     15  /* Block device required */
+#endif
+#ifndef EBUSY
+#define EBUSY       16  /* Device or resource busy */
+#endif
+#ifndef EEXIST
+#define EEXIST      17  /* File exists */
+#endif
+#ifndef EXDEV
+#define EXDEV       18  /* Cross-device link */
+#endif
+#ifndef ENODEV
+#define ENODEV      19  /* No such device */
+#endif
+#ifndef ENOTDIR
+#define ENOTDIR     20  /* Not a directory */
+#endif
+#ifndef EISDIR
+#define EISDIR      21  /* Is a directory */
+#endif
+#ifndef EINVAL
+#define EINVAL      22  /* Invalid argument */
+#endif
+#ifndef ENFILE
+#define ENFILE      23  /* File table overflow */
+#endif
+#ifndef EMFILE
+#define EMFILE      24  /* Too many open files */
+#endif
+#ifndef ENOTTY
+#define ENOTTY      25  /* Not a typewriter */
+#endif
+#ifndef ETXTBSY
+#define ETXTBSY     26  /* Text file busy */
+#endif
+#ifndef EFBIG
+#define EFBIG       27  /* File too large */
+#endif
+#ifndef ENOSPC
+#define ENOSPC      28  /* No space left on device */
+#endif
+#ifndef ESPIPE
+#define ESPIPE      29  /* Illegal seek */
+#endif
+#ifndef EROFS
+#define EROFS       30  /* Read-only file system */
+#endif
+#ifndef EMLINK
+#define EMLINK      31  /* Too many links */
+#endif
+#ifndef EPIPE
+#define EPIPE       32  /* Broken pipe */
+#endif
+#ifndef EDOM
+#define EDOM        33  /* Math argument out of domain of func */
+#endif
+#ifndef ERANGE
+#define ERANGE      34  /* Math result not representable */
+#endif
+
+#ifndef EDEADLK
+#define EDEADLK     35  /* Resource deadlock would occur */
+#endif
+#ifndef ENAMETOOLONG
+#define ENAMETOOLONG    36  /* File name too long */
+#endif
+#ifndef ENOLCK
+#define ENOLCK      37  /* No record locks available */
+#endif
+#ifndef ENOSYS
+#define ENOSYS      38  /* Function not implemented */
+#endif
+#ifndef ENOTEMPTY
+#define ENOTEMPTY   39  /* Directory not empty */
+#endif
+#ifndef ELOOP
+#define ELOOP       40  /* Too many symbolic links encountered */
+#endif
+#ifndef EWOULDBLOCK
+#define EWOULDBLOCK EAGAIN  /* Operation would block */
+#endif
+#ifndef ENOMSG
+#define ENOMSG      42  /* No message of desired type */
+#endif
+#ifndef EIDRM
+#define EIDRM       43  /* Identifier removed */
+#endif
+#ifndef ECHRNG
+#define ECHRNG      44  /* Channel number out of range */
+#endif
+#ifndef EL2NSYNC
+#define EL2NSYNC    45  /* Level 2 not synchronized */
+#endif
+#ifndef EL3HLT
+#define EL3HLT      46  /* Level 3 halted */
+#endif
+#ifndef EL3RST
+#define EL3RST      47  /* Level 3 reset */
+#endif
+#ifndef ELNRNG
+#define ELNRNG      48  /* Link number out of range */
+#endif
+#ifndef EUNATCH
+#define EUNATCH     49  /* Protocol driver not attached */
+#endif
+#ifndef ENOCSI
+#define ENOCSI      50  /* No CSI structure available */
+#endif
+#ifndef EL2HLT
+#define EL2HLT      51  /* Level 2 halted */
+#endif
+#ifndef EBADE
+#define EBADE       52  /* Invalid exchange */
+#endif
+#ifndef EBADR
+#define EBADR       53  /* Invalid request descriptor */
+#endif
+#ifndef EXFULL
+#define EXFULL      54  /* Exchange full */
+#endif
+#ifndef ENOANO
+#define ENOANO      55  /* No anode */
+#endif
+#ifndef EBADRQC
+#define EBADRQC     56  /* Invalid request code */
+#endif
+#ifndef EBADSLT
+#define EBADSLT     57  /* Invalid slot */
+#endif
+
+#ifndef EDEADLOCK
+#define EDEADLOCK   EDEADLK
+#endif
+
+#ifndef EBFONT
+#define EBFONT      59  /* Bad font file format */
+#endif
+#ifndef ENOSTR
+#define ENOSTR      60  /* Device not a stream */
+#endif
+#ifndef ENODATA
+#define ENODATA     61  /* No data available */
+#endif
+#ifndef ETIME
+#define ETIME       62  /* Timer expired */
+#endif
+#ifndef ENOSR
+#define ENOSR       63  /* Out of streams resources */
+#endif
+#ifndef ENONET
+#define ENONET      64  /* Machine is not on the network */
+#endif
+#ifndef ENOPKG
+#define ENOPKG      65  /* Package not installed */
+#endif
+#ifndef EREMOTE
+#define EREMOTE     66  /* Object is remote */
+#endif
+#ifndef ENOLINK
+#define ENOLINK     67  /* Link has been severed */
+#endif
+#ifndef EADV
+#define EADV        68  /* Advertise error */
+#endif
+#ifndef ESRMNT
+#define ESRMNT      69  /* Srmount error */
+#endif
+#ifndef ECOMM
+#define ECOMM       70  /* Communication error on send */
+#endif
+#ifndef EPROTO
+#define EPROTO      71  /* Protocol error */
+#endif
+#ifndef EMULTIHOP
+#define EMULTIHOP   72  /* Multihop attempted */
+#endif
+#ifndef EDOTDOT
+#define EDOTDOT     73  /* RFS specific error */
+#endif
+#ifndef EBADMSG
+#define EBADMSG     74  /* Not a data message */
+#endif
+#ifndef EOVERFLOW
+#define EOVERFLOW   75  /* Value too large for defined data type */
+#endif
+#ifndef ENOTUNIQ
+#define ENOTUNIQ    76  /* Name not unique on network */
+#endif
+#ifndef EBADFD
+#define EBADFD      77  /* File descriptor in bad state */
+#endif
+#ifndef EREMCHG
+#define EREMCHG     78  /* Remote address changed */
+#endif
+#ifndef ELIBACC
+#define ELIBACC     79  /* Can not access a needed shared library */
+#endif
+#ifndef ELIBBAD
+#define ELIBBAD     80  /* Accessing a corrupted shared library */
+#endif
+#ifndef ELIBSCN
+#define ELIBSCN     81  /* .lib section in a.out corrupted */
+#endif
+#ifndef ELIBMAX
+#define ELIBMAX     82  /* Attempting to link in too many shared libraries */
+#endif
+#ifndef ELIBEXEC
+#define ELIBEXEC    83  /* Cannot exec a shared library directly */
+#endif
+#ifndef EILSEQ
+#define EILSEQ      84  /* Illegal byte sequence */
+#endif
+#ifndef ERESTART
+#define ERESTART    85  /* Interrupted system call should be restarted */
+#endif
+#ifndef ESTRPIPE
+#define ESTRPIPE    86  /* Streams pipe error */
+#endif
+#ifndef EUSERS
+#define EUSERS      87  /* Too many users */
+#endif
+#ifndef ENOTSOCK
+#define ENOTSOCK    88  /* Socket operation on non-socket */
+#endif
+#ifndef EDESTADDRREQ
+#define EDESTADDRREQ    89  /* Destination address required */
+#endif
+#ifndef EMSGSIZE
+#define EMSGSIZE    90  /* Message too long */
+#endif
+#ifndef EPROTOTYPE
+#define EPROTOTYPE  91  /* Protocol wrong type for socket */
+#endif
+#ifndef ENOPROTOOPT
+#define ENOPROTOOPT 92  /* Protocol not available */
+#endif
+#ifndef EPROTONOSUPPORT
+#define EPROTONOSUPPORT 93  /* Protocol not supported */
+#endif
+#ifndef ESOCKTNOSUPPORT
+#define ESOCKTNOSUPPORT 94  /* Socket type not supported */
+#endif
+#ifndef EOPNOTSUPP
+#define EOPNOTSUPP  95  /* Operation not supported on transport endpoint */
+#endif
+#ifndef EPFNOSUPPORT
+#define EPFNOSUPPORT    96  /* Protocol family not supported */
+#endif
+#ifndef EAFNOSUPPORT
+#define EAFNOSUPPORT    97  /* Address family not supported by protocol */
+#endif
+#ifndef EADDRINUSE
+#define EADDRINUSE  98  /* Address already in use */
+#endif
+#ifndef EADDRNOTAVAIL
+#define EADDRNOTAVAIL   99  /* Cannot assign requested address */
+#endif
+#ifndef ENETDOWN
+#define ENETDOWN    100 /* Network is down */
+#endif
+#ifndef ENETUNREACH
+#define ENETUNREACH 101 /* Network is unreachable */
+#endif
+#ifndef ENETRESET
+#define ENETRESET   102 /* Network dropped connection because of reset */
+#endif
+#ifndef ECONNABORTED
+#define ECONNABORTED    103 /* Software caused connection abort */
+#endif
+#ifndef ECONNRESET
+#define ECONNRESET  104 /* Connection reset by peer */
+#endif
+#ifndef ENOBUFS
+#define ENOBUFS     105 /* No buffer space available */
+#endif
+#ifndef EISCONN
+#define EISCONN     106 /* Transport endpoint is already connected */
+#endif
+#ifndef ENOTCONN
+#define ENOTCONN    107 /* Transport endpoint is not connected */
+#endif
+#ifndef ESHUTDOWN
+#define ESHUTDOWN   108 /* Cannot send after transport endpoint shutdown */
+#endif
+#ifndef ETOOMANYREFS
+#define ETOOMANYREFS    109 /* Too many references: cannot splice */
+#endif
+#ifndef ETIMEDOUT
+#define ETIMEDOUT   110 /* Connection timed out */
+#endif
+#ifndef ECONNREFUSED
+#define ECONNREFUSED    111 /* Connection refused */
+#endif
+#ifndef EHOSTDOWN
+#define EHOSTDOWN   112 /* Host is down */
+#endif
+#ifndef EHOSTUNREACH
+#define EHOSTUNREACH    113 /* No route to host */
+#endif
+#ifndef EALREADY
+#define EALREADY    114 /* Operation already in progress */
+#endif
+#ifndef EINPROGRESS
+#define EINPROGRESS 115 /* Operation now in progress */
+#endif
+#ifndef ESTALE
+#define ESTALE      116 /* Stale NFS file handle */
+#endif
+#ifndef EUCLEAN
+#define EUCLEAN     117 /* Structure needs cleaning */
+#endif
+#ifndef ENOTNAM
+#define ENOTNAM     118 /* Not a XENIX named type file */
+#endif
+#ifndef ENAVAIL
+#define ENAVAIL     119 /* No XENIX semaphores available */
+#endif
+#ifndef EISNAM
+#define EISNAM      120 /* Is a named type file */
+#endif
+#ifndef EREMOTEIO
+#define EREMOTEIO   121 /* Remote I/O error */
+#endif
+#ifndef EDQUOT
+#define EDQUOT      122 /* Quota exceeded */
+#endif
+
+#ifndef ENOMEDIUM
+#define ENOMEDIUM   123 /* No medium found */
+#endif
+#ifndef EMEDIUMTYPE
+#define EMEDIUMTYPE 124 /* Wrong medium type */
+#endif
+#ifndef ECANCELED
+#define ECANCELED   125 /* Operation Canceled */
+#endif
+#ifndef ENOKEY
+#define ENOKEY      126 /* Required key not available */
+#endif
+#ifndef EKEYEXPIRED
+#define EKEYEXPIRED 127 /* Key has expired */
+#endif
+#ifndef EKEYREVOKED
+#define EKEYREVOKED 128 /* Key has been revoked */
+#endif
+#ifndef EKEYREJECTED
+#define EKEYREJECTED    129 /* Key was rejected by service */
+#endif
+
+/* for robust mutexes */
+#ifndef EOWNERDEAD
+#define EOWNERDEAD  130 /* Owner died */
+#endif
+#ifndef ENOTRECOVERABLE
+#define ENOTRECOVERABLE 131 /* State not recoverable */
+#endif
+
+#ifndef ERFKILL
+#define ERFKILL     132 /* Operation not possible due to RF-kill */
+#endif
+
+#ifndef EHWPOISON
+#define EHWPOISON   133 /* Memory page has hardware error */
+#endif
+
+#ifndef ERESTARTSYS
+#define ERESTARTSYS 512
+#endif
+#ifndef ERESTARTNOINTR
+#define ERESTARTNOINTR  513
+#endif
+#ifndef ERESTARTNOHAND
+#define ERESTARTNOHAND  514 /* restart if no handler.. */
+#endif
+#ifndef ENOIOCTLCMD
+#define ENOIOCTLCMD 515 /* No ioctl command */
+#endif
+#ifndef ERESTART_RESTARTBLOCK
+#define ERESTART_RESTARTBLOCK  516 /* restart by calling sys_restart_syscall */
+#endif
+#ifndef EPROBE_DEFER
+#define EPROBE_DEFER    517 /* Driver requests probe retry */
+#endif
+#ifndef EOPENSTALE
+#define EOPENSTALE  518 /* open found a stale dentry */
+#endif
+
+/* Defined for the NFSv3 protocol */
+#ifndef EBADHANDLE
+#define EBADHANDLE  521 /* Illegal NFS file handle */
+#endif
+#ifndef ENOTSYNC
+#define ENOTSYNC    522 /* Update synchronization mismatch */
+#endif
+#ifndef EBADCOOKIE
+#define EBADCOOKIE  523 /* Cookie is stale */
+#endif
+#ifndef ENOTSUPP
+#define ENOTSUPP    524 /* Operation is not supported */
+#endif
+#ifndef ENOTSUP
+#define ENOTSUP    ENOTSUPP
+#endif
+
+#ifndef ETOOSMALL
+#define ETOOSMALL   525 /* Buffer or request is too small */
+#endif
+#ifndef ESERVERFAULT
+#define ESERVERFAULT    526 /* An untranslatable error occurred */
+#endif
+#ifndef EBADTYPE
+#define EBADTYPE    527 /* Type not supported by server */
+#endif
+#ifndef EJUKEBOX
+#define EJUKEBOX    528 /* Request initiated, but will not complete before timeout */
+#endif
+#ifndef EIOCBQUEUED
+#define EIOCBQUEUED 529 /* iocb queued, will get completion event */
+#endif
+
+#ifndef MAX_ERRNO
+#define MAX_ERRNO   4095
+#endif
+
+#define IS_ERR_VALUE(x) ((x) >= (unsigned long)-MAX_ERRNO)
+
+static inline void   *ERR_PTR(long error)
+{
+    return (void *) error;
+}
+
+static inline long  PTR_ERR(const void *ptr)
+{
+    return (long) ptr;
+}
+
+static inline long IS_ERR(const void *ptr)
+{
+    return IS_ERR_VALUE((unsigned long)ptr);
+}
+
+static inline long  IS_ERR_OR_NULL(const void *ptr)
+{
+    return !ptr || IS_ERR_VALUE((unsigned long)ptr);
+}
+
+/**
+ * ERR_CAST - Explicitly cast an error-valued pointer to another pointer type
+ * @ptr: The pointer to cast.
+ *
+ * Explicitly cast an error-valued pointer to another pointer type in such a
+ * way as to make it clear that's what's going on.
+ */
+static inline void   *ERR_CAST(const void *ptr)
+{
+    /* cast away the const */
+    return (void *) ptr;
+}
+
+static inline int  PTR_RET(const void *ptr)
+{
+    if (IS_ERR(ptr)) {
+        return PTR_ERR(ptr);
+    } else {
+        return 0;
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/hal/adc.h

@@ -0,0 +1,196 @@
+#ifndef _HAL_ADC_H_
+#define _HAL_ADC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+  * @brief ADC ioctl_cmd type
+  */
+enum adc_ioctl_cmd {
+    RESERVE,
+};
+
+/**
+  * @brief ADC irq_flag type
+  */
+enum adc_irq_flag {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    ADC_IRQ_FLAG_SAMPLE_DONE = BIT(0),
+};
+
+
+
+/* User interrupt handle */
+typedef void (*adc_irq_hdl)(uint32 irq, uint32 channel, uint32 irq_data);
+
+
+/* ADC api for user */
+struct adc_device {
+    struct dev_obj dev;
+};
+
+
+struct adc_hal_ops{
+    struct devobj_ops ops;
+    int32(*open)(struct adc_device *adc);
+    int32(*close)(struct adc_device *adc);
+    int32(*add_channel)(struct adc_device *adc, uint32 channel);
+    int32(*delete_channel)(struct adc_device *adc, uint32 channel);
+    int32(*get_value)(struct adc_device *adc, uint32 channel, uint32 *raw_data);
+    int32(*ioctl)(struct adc_device *adc, enum adc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct adc_device *adc, enum adc_irq_flag irq_flag, adc_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct adc_device *adc, enum adc_irq_flag irq_flag);
+};
+
+/* ADC API functions */
+
+
+
+/**
+ * @brief adc_open
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_open(struct adc_device *adc);
+
+/**
+ * @brief adc_close
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_close(struct adc_device *adc);
+
+/**
+ * @brief adc_add_channel
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_add_channel(struct adc_device *adc, uint32 channel);
+
+/**
+ * @brief adc_delete_channel
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_delete_channel(struct adc_device *adc, uint32 channel);
+
+/**
+ * @brief adc_get_value
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_get_value(struct adc_device *adc, uint32 channel, uint32 *raw_data);
+
+
+/**
+ * @brief adc_ioctl
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_ioctl(struct adc_device *adc, enum adc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief adc_request_irq
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_request_irq(struct adc_device *adc, enum adc_irq_flag irq_flag, adc_irq_hdl irq_hdl, uint32 irq_data);
+
+/**
+ * @brief adc_release_irq
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param adc       The address of adc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 adc_release_irq(struct adc_device *adc, enum adc_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/hal/auadc.h

@@ -0,0 +1,204 @@
+#ifndef _AUADC_H
+#define _AUADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief AUADC sample_rate type
+  */
+enum auadc_sample_rate {
+
+    AUADC_SAMPLE_RATE_8K,
+
+	AUADC_SAMPLE_RATE_11_025K,
+	
+    AUADC_SAMPLE_RATE_16K,
+
+	AUADC_SAMPLE_RATE_22_05K,
+
+	AUADC_SAMPLE_RATE_32K,
+
+    AUADC_SAMPLE_RATE_44_1K,
+
+    AUADC_SAMPLE_RATE_48K,
+};
+
+/**
+  * @brief AUADC irq_flag type
+  */
+enum auadc_irq_flag {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUADC_IRQ_FLAG_HALF = BIT(0),
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUADC_IRQ_FLAG_FULL = BIT(1),
+};
+
+/**
+  * @brief AUADC ioctl_cmd type
+  */
+enum auadc_ioctl_cmd {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUADC_IOCTL_CMD_SET_SAMPLE_RATE,
+    /*!
+     * @brief:
+     * 
+     */
+    AUADC_IOCTL_CMD_SET_SOUND_CHANNEL,
+    
+    /*!
+     * @brief: Adjust the power digital gain
+     * 
+     */
+    AUADC_IOCTL_CMD_SET_DIGITAL_GAIN,
+    
+    /*!
+     * @brief: Adjust the power analog gain
+     * 
+     */
+    AUADC_IOCTL_CMD_SET_ANALOG_GAIN, 
+};
+
+
+
+/* User interrupt handle */
+typedef void (*auadc_irq_hdl)(uint32 irq, uint32 irq_data);
+
+
+/* AUADCC api for user */
+
+struct auadc_device {
+    struct dev_obj dev;
+};
+
+
+/* AUADC api for user */
+struct auadc_hal_ops {
+    struct devobj_ops ops;
+    int32(*open)(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
+    int32(*close)(struct auadc_device *auadc);
+    int32(*read)(struct auadc_device *auadc, void* buf, uint32 bytes);
+    int32(*ioctl)(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
+};
+
+
+
+/* AUADC API functions */
+
+
+
+/**
+ * @brief auadc_open
+ *
+ *
+ * @note  .
+ *
+ * @param auadc       The address of auadc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auadc_open(struct auadc_device *auadc, enum auadc_sample_rate sample_rate);
+
+/**
+ * @brief auadc_close
+ *
+ *
+ * @note  .
+ *
+ * @param auadc       The address of auadc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auadc_close(struct auadc_device *auadc);
+
+/**
+ * @brief auadc_read
+ *
+ *
+ * @note  .
+ *
+ * @param auadc       The address of auadc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auadc_read(struct auadc_device *auadc, void* buf, uint32 bytes);
+
+/**
+ * @brief auadc_ioctl
+ *
+ *
+ * @note  .
+ *
+ * @param auadc       The address of auadc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auadc_ioctl(struct auadc_device *auadc, enum auadc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief auadc_request_irq
+ *
+ *
+ * @note  .
+ *
+ * @param auadc       The address of auadc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auadc_request_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag, auadc_irq_hdl irq_hdl, uint32 irq_data);
+
+/**
+ * @brief auadc_release_irq
+ *
+ *
+ * @note  .
+ *
+ * @param auadc       The address of auadc device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 auadc_release_irq(struct auadc_device *auadc, enum auadc_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/hal/audac.h

@@ -0,0 +1,224 @@
+#ifndef _AUDAC_H
+#define _AUDAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief AUDAC sample_rate type
+  */
+enum audac_sample_rate {
+
+    AUDAC_SAMPLE_RATE_8K,
+
+    AUDAC_SAMPLE_RATE_11_025K,
+    
+    AUDAC_SAMPLE_RATE_16K,
+
+	AUDAC_SAMPLE_RATE_22_05K,
+
+    AUDAC_SAMPLE_RATE_32K,
+
+    AUDAC_SAMPLE_RATE_44_1K,
+
+    AUDAC_SAMPLE_RATE_48K,
+	
+	AUDAC_SAMPLE_RATE_12K,
+	
+	AUDAC_SAMPLE_RATE_24K,
+};
+
+/**
+  * @brief AUDAC irq_flag type
+  */
+enum audac_irq_flag {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUDAC_IRQ_FLAG_HALF = BIT(0),
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUDAC_IRQ_FLAG_FULL = BIT(1),
+};
+
+/**
+  * @brief AUDAC ioctl_cmd type
+  */
+enum audac_ioctl_cmd {
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUDAC_IOCTL_CMD_SET_SAMPLE_RATE,
+
+    /*!
+     * @brief:
+     * 
+     */
+    AUDAC_IOCTL_CMD_SET_SOUND_CHANNEL,
+    
+    /*!
+     * @brief: Adjust the power digital gain
+     * 
+     */
+    AUDAC_IOCTL_CMD_SET_DIGITAL_GAIN,
+    
+    /*!
+     * @brief: Adjust the power analog gain
+     * 
+     */
+    AUDAC_IOCTL_CMD_SET_ANALOG_GAIN, 
+    
+    /*!
+     * @brief: Soft mute
+     * 
+     */
+    AUDAC_IOCTL_CMD_SOFT_MUTE,
+
+	
+    /*!
+     * @brief: Change sample rate
+     * @note :
+     *         1.Ensure DAC is muted by special method
+     * 		   2.You should call "audac_write" API after using this cmd
+     * 
+     */
+    AUDAC_IOCTL_CMD_CHANGE_SAMPLE_RATE, 
+	
+	AUDAC_IOCTL_CMD_GET_DIGITAL_GAIN,
+};
+
+
+
+/* User interrupt handle */
+typedef void (*audac_irq_hdl)(uint32 irq, uint32 irq_data);
+
+/* AUDAC api for user */
+
+struct audac_device {
+    struct dev_obj dev;
+};
+
+struct audac_hal_ops {
+    struct devobj_ops ops;
+    int32(*open)(struct audac_device *audac, enum audac_sample_rate sample_rate);
+    int32(*close)(struct audac_device *audac);
+    int32(*write)(struct audac_device *audac, void* buf, uint32 bytes);
+    int32(*ioctl)(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct audac_device *audac, enum audac_irq_flag irq_flag);
+};
+
+
+
+/* AUDAC API functions */
+
+
+
+/**
+ * @brief audac_open
+ *
+ *
+ * @note  .
+ *
+ * @param audac       The address of audac device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 audac_open(struct audac_device *audac, enum audac_sample_rate sample_rate);
+
+/**
+ * @brief audac_close
+ *
+ *
+ * @note  .
+ *
+ * @param audac       The address of audac device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 audac_close(struct audac_device *audac);
+
+/**
+ * @brief audac_write
+ *
+ *
+ * @note  .
+ *
+ * @param audac       The address of audac device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 audac_write(struct audac_device *audac, void* buf, uint32 bytes);
+
+/**
+ * @brief audac_ioctl
+ *
+ *
+ * @note  .
+ *
+ * @param audac       The address of audac device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 audac_ioctl(struct audac_device *audac, enum audac_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief audac_request_irq
+ *
+ *
+ * @note  .
+ *
+ * @param audac       The address of audac device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 audac_request_irq(struct audac_device *audac, enum audac_irq_flag irq_flag, audac_irq_hdl irq_hdl, uint32 irq_data);
+
+/**
+ * @brief audac_release_irq
+ *
+ *
+ * @note  .
+ *
+ * @param audac       The address of audac device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 audac_release_irq(struct audac_device *audac, enum audac_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/hal/capture.h

@@ -0,0 +1,272 @@
+#ifndef _HAL_CAPTURE_H_
+#define _HAL_CAPTURE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief CAPTURE channel type
+  */
+enum capture_channel {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_CHANNEL_0,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_CHANNEL_1,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_CHANNEL_2,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_CHANNEL_3,
+};
+
+/**
+  * @brief CAPTURE mode type
+  */
+enum capture_mode {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_MODE_RISE,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_MODE_FALL,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_MODE_ALL,
+};
+
+/**
+  * @brief CAPTURE irq_flag type
+  */
+enum capture_irq_flag {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_IRQ_FLAG_CAPTURE,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * 
+     */
+    CAPTURE_IRQ_FLAG_OVERFLOW,
+};
+
+/**
+  * @brief CAPTURE ioctl_cmd type
+  */
+enum capture_ioctl_cmd {
+    NONE,
+};
+
+
+
+/* User interrupt handle */
+typedef void (*capture_irq_hdl)(uint32 irq, uint32 irq_data);
+
+
+/* CAPTURE api for user */
+struct capture_device {
+    struct dev_obj dev;
+};
+
+struct capture_hal_ops{
+    struct devobj_ops ops;
+    int32(*init)(struct capture_device *cap, enum capture_channel channel, enum capture_mode mode);
+    int32(*deinit)(struct capture_device *cap, enum capture_channel channel);
+    int32(*start)(struct capture_device *cap, enum capture_channel channel);
+    int32(*stop)(struct capture_device *cap, enum capture_channel channel);
+    int32(*suspend)(struct capture_device *cap, enum capture_channel channel);
+    int32(*resume)(struct capture_device *cap, enum capture_channel channel);
+    int32(*ioctl)(struct capture_device *cap, enum capture_channel channel, enum capture_ioctl_cmd cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct capture_device *cap, enum capture_channel channel, enum capture_irq_flag irq_flag, capture_irq_hdl irq_hdl, uint32 data);
+    int32(*release_irq)(struct capture_device *cap, enum capture_channel channel);
+};
+
+
+/* CAPTURE API functions */
+
+
+
+/**
+ * @brief capture_init
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_init(struct capture_device *capture, enum capture_channel channel, enum capture_mode mode);
+
+/**
+ * @brief capture_deinit
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_deinit(struct capture_device *capture, enum capture_channel channel);
+
+/**
+ * @brief capture_start
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_start(struct capture_device *capture, enum capture_channel channel);
+
+/**
+ * @brief capture_stop
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_stop(struct capture_device *capture, enum capture_channel channel);
+
+/**
+ * @brief capture_suspend channel
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_suspend(struct capture_device *capture, enum capture_channel channel);
+
+/**
+ * @brief capture_resume channel
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_resume(struct capture_device *capture, enum capture_channel channel);
+
+/**
+ * @brief capture_ioctl
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_ioctl(struct capture_device *capture, enum capture_channel channel, enum capture_ioctl_cmd cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief capture_request_irq
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_request_irq(struct capture_device *capture, enum capture_channel channel, enum capture_irq_flag irq_flag, capture_irq_hdl irq_hdl, uint32 data);
+
+/**
+ * @brief capture_release_irq
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param capture       The address of capture device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 capture_release_irq(struct capture_device *capture, enum capture_channel channel);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/hal/crc.h

@@ -0,0 +1,70 @@
+#ifndef _HAL_CRC_H_
+#define _HAL_CRC_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CRC_DEV_FLAGS {
+    CRC_DEV_FLAGS_CONTINUE_CALC = BIT(0),
+};
+
+enum CRC_DEV_TYPE {
+    CRC_TYPE_CRC5_USB    = 0,
+    CRC_TYPE_CRC7_MMC,
+    CRC_TYPE_CRC8_MAXIM,
+    CRC_TYPE_CRC8,
+    CRC_TYPE_CRC16,
+    CRC_TYPE_CRC16_CCITT,
+    CRC_TYPE_CRC16_MODBUS,
+    CRC_TYPE_CRC32_WINRAR,
+    CRC_TYPE_TCPIP_CHKSUM,
+
+    CRC_TYPE_MAX,
+};
+
+/**
+ * CRC len 512KB for TXW81x； 64KB for TXW80x
+ */
+struct crc_dev_req {
+    uint16 type;
+    uint16 cookie;
+    uint8 *data;
+    uint32 len;
+    uint32 crc_last; //use when CRC_DEV_FLAGS_CONTINUE_CALC
+};
+
+struct crc_dev {
+    struct dev_obj dev;
+};
+
+struct crc_hal_ops{
+    struct devobj_ops ops;
+    int32(*calc)(struct crc_dev *dev, struct crc_dev_req *req, uint32 *crc_val, uint32 flags);
+};
+
+/** 
+  * @brief  Hold CRC .
+  * @param  dev      : crc_dev use @ref dev_get() function to get the handle.
+  * @param  req      : req(type\addr\len) for crc dev. 
+  *                      1、req crc_last must set when flags:CRC_DEV_FLAGS_CONTINUE_CALC
+  * @param  crc_val  : crc result.
+  * @param  flags    : CRC_DEV_FLAGS .
+  * @return 
+  *         - RET_OK  : Successfully.
+  *         - RET_ERR : Failed.
+  * @note
+  */
+static inline int32 crc_dev_calc(struct crc_dev *dev, struct crc_dev_req *req, uint32 *crc_val, uint32 flags)
+{
+    const struct crc_hal_ops *ops = (const struct crc_hal_ops *)dev->dev.ops;
+    return (dev && ops->calc) ? ops->calc(dev, req, crc_val, flags) : RET_ERR;
+}
+
+extern uint32 hw_crc(enum CRC_DEV_TYPE type, uint8 *data, uint32 len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

sdk/include/hal/dma.h

@@ -0,0 +1,161 @@
+#ifndef _HAL_DMA_H_
+#define _HAL_DMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * enum dma_status - DMA transaction status
+ * @DMA_SUCCESS: transaction completed successfully
+ * @DMA_IN_PROGRESS: transaction not yet processed
+ * @DMA_PAUSED: transaction is paused
+ * @DMA_ERROR: transaction failed
+ */
+enum dma_status {
+    DMA_SUCCESS,
+    DMA_IN_PROGRESS,
+    DMA_PAUSED,
+    DMA_ERROR,
+};
+
+enum dma_xfer_direct {
+    /*! xfer directiont: NONE
+     */
+    DMA_XFER_DIR_NONE,
+    
+    /*! xfer directiont: memory to memory
+     */
+    DMA_XFER_DIR_M2M,
+    
+    /*! xfer directiont: memory to device
+     */
+    DMA_XFER_DIR_M2D,
+    
+    /*! xfer directiont: device to memory
+     */
+    DMA_XFER_DIR_D2M,
+    
+    /*! xfer directiont: device to device
+     */
+    DMA_XFER_DIR_D2D,
+};
+
+enum dma_xfer_mode {
+    /*! xfer mode: source address increase
+     */
+    DMA_XFER_MODE_INCREASE,
+
+    /*! xfer mode: source address recycling
+     */
+    DMA_XFER_MODE_RECYCLE,
+
+    /*! xfer mode: source address block copy
+     */
+    DMA_XFER_MODE_BLKCPY,
+};
+    
+
+/**
+ * enum dma_slave_buswidth - defines bus with of the DMA slave
+ * device, source or target buses
+ */
+enum dma_slave_buswidth {
+    DMA_SLAVE_BUSWIDTH_1_BYTE       = 0,
+    DMA_SLAVE_BUSWIDTH_2_BYTES      = 1,
+    DMA_SLAVE_BUSWIDTH_4_BYTES      = 2,
+    DMA_SLAVE_BUSWIDTH_8_BYTES      = 3,
+    DMA_SLAVE_BUSWIDTH_UNDEFINED    = 4,
+};
+
+enum dma_irq_type {
+    DMA_IRQ_TYPE_DONE,
+    DMA_IRQ_TYPE_ERROR,
+};
+
+enum dma_endian_type{
+    DMA_ENDIAN_TYPE_NO_OVERTURN,
+    DMA_ENDIAN_TYPE_16BIT_OVERTURN,
+    DMA_ENDIAN_TYPE_32BIT_OVERTURN,
+};
+
+enum dma_ioctl_cmd{
+    DMA_IOCTL_CMD_ENDIAN,
+    DMA_IOCTL_CMD_CHECK_DMA1_STATUS,
+    DMA_IOCTL_CMD_DMA1_LOCK,
+    DMA_IOCTL_CMD_DMA1_UNLOCK,
+};
+
+struct dma_device;
+
+typedef void (*dma_irq_hdl)(struct dma_device *p_dma, uint32 ch, enum dma_irq_type irq, uint32 data);
+
+struct dma_xfer_data {
+    uint32 dest;
+    uint32 src;
+    uint32 blk_width     : 16,
+           blk_height    : 12,
+           src_addr_mode :  2,  //enum dma_xfer_mode
+           dst_addr_mode :  2;  //enum dma_xfer_mode
+    uint32 src_width     : 12,
+           dst_width     : 12,
+           src_id        : 8;	
+    uint32 dir           : 3,   //enum dma_xfer_direct
+           endian        : 2,
+           dst_id        : 8,
+           reserved      : 19;
+    uint32 element_per_width;
+    uint32 element_num;
+    uint32 irq_data;
+    dma_irq_hdl irq_hdl;
+};
+
+struct dma_blkcpy_cfg{
+    uint32 dest;
+    uint32 src;
+    uint32 blk_width  : 20,
+           blk_height : 12;
+    uint32 src_width  : 12,
+           dst_width  : 12,
+           reserved   : 8;	
+};
+
+
+struct dma_device {
+    struct dev_obj dev;
+};
+
+struct dma_hal_ops{
+    struct devobj_ops ops;
+    int32(*pause)(struct dma_device *dma, uint32 ch);
+    int32(*resume)(struct dma_device *dma, uint32 ch);
+    int32(*xfer)(struct dma_device *dma, struct dma_xfer_data *data);
+    int32(*get_status)(struct dma_device *dma, uint32 ch);
+    int32(*stop)(struct dma_device *dma, uint32 ch);
+    int32(*ioctl)(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
+};
+
+int32 dma_pause(struct dma_device *dma, uint32 ch);
+
+int32 dma_resume(struct dma_device *dma, uint32 ch);
+
+void  dma_memcpy(struct dma_device *dma, void *dst, const void *src, uint32 n);
+ 
+void  dma_memset(struct dma_device *dma, void *dst, uint8 c, uint32 n);
+ 
+void dma_blkcpy(struct dma_device *dma , struct dma_blkcpy_cfg *cfg);
+
+int32 dma_ioctl(struct dma_device *dma, uint32 cmd, int32 param1, int32 param2);
+
+int32 dma_xfer(struct dma_device *dma, struct dma_xfer_data *data);
+
+int32 dma_status(struct dma_device *dma, uint32 ch);
+
+int32 dma_stop(struct dma_device *dma, uint32 ch);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/hal/dvp.h

@@ -0,0 +1,145 @@
+#ifndef HAL_DVP_H
+#define HAL_DVP_H
+
+/* User interrupt handle */
+typedef int32(*dvp_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
+
+/**
+  * @brief UART ioctl_cmd type
+  */
+enum dvp_ioctl_cmd {
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_FORMAT,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_RGB_2_YUV,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_SIZE,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_ADR_1,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_ADR_2,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_SCEN,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_HSYNC_VAILD,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_VSYNC_VAILD,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_ONE_SAMPLE,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_DEBOUNCE,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_YCBCR_MODE,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_DIS_UV_MODE,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_FRAME_RATE,
+
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    DVP_IOCTL_CMD_SET_THRESHOLD,
+
+    DVP_IOCTL_CMD_EX_D5_D6,
+
+    DVP_IOCTL_CMD_SET_JPEG_LEN,
+
+};
+
+struct dvp_device {
+    struct dev_obj dev;
+};
+
+struct dvp_hal_ops{
+    struct devobj_ops ops;
+    int32(*init)(struct dvp_device *dvp_dev);
+	int32(*suspend)(struct dvp_device *dvp_dev);
+	int32(*resume)(struct dvp_device *dvp_dev);	
+    int32(*baudrate)(struct dvp_device *dvp_dev, uint32 baudrate);
+    int32(*open)(struct dvp_device *dvp_dev);
+    int32(*close)(struct dvp_device *dvp_dev);
+    int32(*ioctl)(struct dvp_device *dvp_dev, enum dvp_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct dvp_device *dvp_dev, uint32 irq_flag, dvp_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct dvp_device *dvp_dev, uint32 irq_flag);
+};
+
+int32 dvp_open(struct dvp_device *p_dvp);
+int32 dvp_close(struct dvp_device *p_dvp);
+int32 dvp_suspend(struct dvp_device *p_dvp);
+int32 dvp_resume(struct dvp_device *p_dvp);
+int32 dvp_init(struct dvp_device *p_dvp);
+int32 dvp_set_baudrate(struct dvp_device *p_dvp, uint32 mclk);
+int32 dvp_set_size(struct dvp_device *p_dvp, uint32 x_s, uint32 y_s, uint32 x_e, uint32 y_e);
+int32 dvp_set_addr1(struct dvp_device *p_dvp, uint32 yuv_addr);
+int32 dvp_set_addr2(struct dvp_device *p_dvp, uint32 yuv_addr);
+int32 dvp_set_rgb2yuv(struct dvp_device *p_dvp, uint8 en);
+int32 dvp_set_format(struct dvp_device *p_dvp, uint8 format);
+int32 dvp_set_half_size(struct dvp_device *p_dvp, uint8 en);
+int32 dvp_set_vsync_polarity(struct dvp_device *p_dvp, uint8 high_valid);
+int32 dvp_set_hsync_polarity(struct dvp_device *p_dvp, uint8 high_valid);
+int32 dvp_set_once_sampling(struct dvp_device *p_dvp, uint8 en);
+int32 dvp_debounce_enable(struct dvp_device *p_dvp, uint8 en, uint8 pixel);
+int32 dvp_set_ycbcr(struct dvp_device *p_dvp, uint8 mode);
+int32 dvp_unload_uv(struct dvp_device *p_dvp, uint8 en);
+int32 dvp_frame_load_precent(struct dvp_device *p_dvp, uint8 precent);
+int32 dvp_low_high_threshold(struct dvp_device *p_dvp, bool low_high);
+int32 dvp_jpeg_mode_set_len(struct dvp_device *p_dvp, uint32 len);
+int32 dvp_request_irq(struct dvp_device *p_dvp, uint32 irq_flag, dvp_irq_hdl irq_hdl, uint32 irq_data);
+int32 dvp_release_irq(struct dvp_device *p_dvp, uint32 irq_flag);
+int32 dvp_set_exchange_d5_d6(struct dvp_device *p_dvp, uint8 en);
+
+
+#endif

sdk/include/hal/gpio.h

@@ -0,0 +1,156 @@
+/**
+ * @file gpio.h
+ * @author HUGE-IC Application Team
+ * @brief GPIO HAL driver
+ * @version 1.0.0
+ * @date 2021-9-8
+ * 
+ * @copyright Copyright (c) 2021 HUGE-IC
+ */
+#ifndef _HAL_GPIO_H_
+#define _HAL_GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+  * @brief Enumeration constant for GPIO pin direction select
+  * @note : this enum must mapping to OS @PinDirection
+  */
+enum gpio_pin_direction {
+    /*! Set GPIO to input mode.
+     */
+    GPIO_DIR_INPUT,
+    
+    /*! Set GPIO to output mode.
+     */
+    GPIO_DIR_OUTPUT,
+};
+
+/**
+  * @breif : enum of GPIO pin mode
+  * @note : this enum must mapping to OS @PinMode
+  */
+enum gpio_pin_mode {
+    /*! gpio mode : push-pull & pull none
+     */
+    GPIO_PULL_NONE,
+    
+    /*! gpio mode : push-pull & pull up 
+     */
+    GPIO_PULL_UP,
+    
+    /*! gpio mode : push-pull & pull down
+     */
+    GPIO_PULL_DOWN,
+    
+    /*! gpio mode : open-drain & pull none
+     */
+    GPIO_OPENDRAIN_PULL_NONE,
+    
+    /*! gpio mode : open-drain & pull up
+     */
+    GPIO_OPENDRAIN_PULL_UP,
+
+    /*! Set the GPIO drop open-drain mode to NO.
+     */
+    GPIO_OPENDRAIN_DROP_NONE,
+    
+    /*! Set the GPIO drop open-drain mode to down mode.
+     */
+    GPIO_OPENDRAIN_DROP_DOWN,
+
+};
+
+/**
+  * @breif : Enumeration constant for GPIO pin interrupt event.
+  */
+enum gpio_irq_event {
+    /*! None interrupt event.
+     */
+    GPIO_IRQ_EVENT_NONE,
+
+    /*! Rising interrupt event.
+     */
+    GPIO_IRQ_EVENT_RISE,
+
+    /*! Falling interrupt event.
+     */
+    GPIO_IRQ_EVENT_FALL,
+
+    /*! Rising and falling interrupt event.
+     */
+    GPIO_IRQ_EVENT_ALL ,
+};
+
+
+/**
+  * @breif : enum of io control cmd
+  */
+enum gpio_ioctl_cmd {
+    /*! switch GPIO input delay on or off
+     */
+    GPIO_INPUT_DELAY_ON_OFF,
+    
+    /*! Atomic operation in GPIO direction.
+     */
+    GPIO_DIR_ATOMIC,
+    
+    /*! Atomic operation in GPIO vaule.
+     */
+    GPIO_VALUE_ATOMIC,
+    
+    /*! LOCK GPIO config exclude I/O DAT register until MCU reset or peripheral reset.
+     */
+    GPIO_LOCK,
+    
+    /*! GPIO debunce
+     */
+    GPIO_DEBUNCE,
+    
+    /*! GPIO toggle, use for output data toggle
+     */
+    GPIO_OUTPUT_TOGGLE,
+
+    /*! Set GPIO pin to general analog function
+     */
+    GPIO_GENERAL_ANALOG,
+
+    GPIO_CMD_SET_IEEN,
+};
+
+
+typedef void (*gpio_irq_hdl)(int32 id, enum gpio_irq_event event);
+
+struct gpio_device {
+    struct dev_obj dev;
+};
+
+struct gpio_hal_ops{
+    struct devobj_ops ops;
+    int32(*mode)(struct gpio_device *gpio, uint32 pin, enum gpio_pin_mode mode, enum gpio_pull_level level);
+    int32(*dir)(struct gpio_device *gpio, uint32 pin, enum gpio_pin_direction direction);
+    int32(*set)(struct gpio_device *gpio, uint32 pin, int32 val);
+    int32(*get)(struct gpio_device *gpio, int32 pin);
+    int32(*request_pin_irq)(struct gpio_device *gpio, uint32 pin, gpio_irq_hdl handler, uint32 data, enum gpio_irq_event evt);
+    int32(*release_pin_irq)(struct gpio_device *gpio, uint32 pin, enum gpio_irq_event evt);
+    int32(*ioctl)(struct gpio_device *gpio, uint32 pin, int32 cmd, int32 param1, int32 param2);    
+};
+
+int32 gpio_set_mode(uint32 pin, enum gpio_pin_mode mode, enum gpio_pull_level level);
+int32 gpio_set_dir(uint32 pin, enum gpio_pin_direction direction);
+int32 gpio_set_val(uint32 pin, int32 value);
+int32 gpio_get_val(uint32 pin);
+int32 gpio_request_pin_irq(uint32 pin, gpio_irq_hdl handler, uint32 data, enum gpio_irq_event evt);
+int32 gpio_release_pin_irq(uint32 pin, enum gpio_irq_event evt);
+int32 gpio_ioctl(uint32 pin, int32 cmd, int32 param1, int32 param2);
+
+extern struct gpio_device *gpio_get(uint32 pin);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/hal/i2c.h

@@ -0,0 +1,160 @@
+/**
+  ******************************************************************************
+  * @file    sdk/include/hal/i2c.h
+  * @author  HUGE-IC Application Team
+  * @version V1.0.0
+  * @date    01-08-2018
+  * @brief   Main program body header file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2018 HUGE-IC</center></h2>
+  *
+  *
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef _HAL_I2C_H_
+#define _HAL_I2C_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+
+/** @addtogroup Template_Project
+  * @{
+  */
+
+/**
+  * @brief Enumeration constant for IIC ioctrl cmd
+  */
+enum i2c_ioctl_cmd {
+    /*! IIC SDA output delay
+     */
+    IIC_SDA_OUTPUT_DELAY,
+
+    /*! IIC SCL strong output
+     *@note: I/O cannot be configured when the strong output is on
+     */
+    IIC_STRONG_OUTPUT,
+
+    IIC_FILTERING,
+
+    IIC_SET_DEVICE_ADDR,
+};
+
+
+/**
+  * @brief Enumeration constant for IIC mode selection
+  */
+enum i2c_mode {
+    /*! IIC selects the master mode.
+     */
+    IIC_MODE_MASTER,
+
+    /*! IIC selects the slave mode.
+     */
+    IIC_MODE_SLAVE,
+};
+
+/**
+  * @brief Enumeration constant for IIC address bit selection
+  */
+enum i2c_addr_mode {
+    /*! The IIC communication address selects the 7-bit mode.
+     */
+
+    IIC_ADDR_7BIT,
+    /*! The IIC communication address selects the 10-bit mode.
+     */
+    IIC_ADDR_10BIT,
+};
+
+enum i2c_irq_flag {
+    /*!
+     * @brief Interrupt: IIC send data completed.
+     * @Note
+     *        This interrupt is only used for IIC transmit.
+     */
+    I2C_IRQ_FLAG_TX_DONE     = BIT(0),
+
+    /*!
+     * @brief Interrupt: IIC receive data completed.
+     * @Note:
+     *        This interrupt is only used for IIC receive.
+     */
+    I2C_IRQ_FLAG_RX_DONE     = BIT(1),
+
+    /*!
+     * @brief Interrupt: IIC slave nack to IIC master
+     */
+    I2C_IRQ_FLAG_RX_NACK     = BIT(2),
+
+    /*!
+     * @brief Interrupt: IIC rececive error
+     * @Note:
+     *        IIC buf overflow means rx error
+     */
+    I2C_IRQ_FLAG_RX_ERROR    = BIT(3),
+
+    /*!
+     * @brief Interrupt: IIC detect stop
+     * @Note:
+     *       IIC has detected the stop signal on the bus
+     */
+    I2C_IRQ_FLAG_DETECT_STOP = BIT(4),
+
+
+};
+
+
+typedef void (*i2c_irq_hdl)(uint32 irq, uint32 irq_data, uint32 param);
+
+struct i2c_device {
+    struct dev_obj dev;
+};
+
+struct i2c_hal_ops{
+    struct devobj_ops ops;
+    int32(*open)(struct i2c_device *i2c, enum i2c_mode mode, enum i2c_addr_mode addr_mode, uint32 addr);
+    int32(*close)(struct i2c_device *i2c);
+    int32(*ioctl)(struct i2c_device *i2c, int32 cmd, uint32 param);
+    int32(*baudrate)(struct i2c_device *i2c, uint32 baudrate);
+    int32(*read)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 len);
+    int32(*write)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 len);
+    int32(*write_scatter)(struct i2c_device *i2c, int8 *addr, uint32 addr_len, scatter_data *data, uint32 count);
+    int32(*request_irq)(struct i2c_device *i2c, i2c_irq_hdl irqhdl, uint32 irq_data, uint32 irq_flag);
+    int32(*release_irq)(struct i2c_device *i2c, uint32 irq_flag);
+};
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HGI2C_DW_Exported_Functions
+  * @{
+  */
+
+int32 i2c_open(struct i2c_device *i2c, enum i2c_mode mode, enum i2c_addr_mode addr_mode, uint32 addr);
+int32 i2c_close(struct i2c_device *i2c);
+int32 i2c_set_baudrate(struct i2c_device *i2c, uint32 baudrate);
+int32 i2c_ioctl(struct i2c_device *i2c, uint32 cmd, uint32 param);
+int32 i2c_read(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len);
+int32 i2c_write(struct i2c_device *i2c, int8 *addr, uint32 addr_len, int8 *buf, uint32 buf_len);
+int32 i2c_write_scatter(struct i2c_device *i2c, int8 *addr, uint32 addr_len, scatter_data *data, uint32 count);
+int32 i2c_request_irq(struct i2c_device *i2c, i2c_irq_hdl handle, uint32 irq_data, uint32 irq_flag);
+int32 i2c_release_irq(struct i2c_device *i2c, uint32 irq_flag);
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/hal/i2s.h

@@ -0,0 +1,323 @@
+#ifndef _HAL_I2S_H_
+#define _HAL_I2S_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief i2s bit width per sample type
+  */
+enum i2s_sample_bits {
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s bit width per sample: 8bits
+     */
+    I2S_SAMPLE_BITS_8BITS,
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s bit width per sample: 16bits
+     */
+    I2S_SAMPLE_BITS_16BITS,
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s bit width per sample: 24bits
+     */
+    I2S_SAMPLE_BITS_24BITS,
+};
+
+/**
+  * @brief i2s sample frequency type
+  */
+enum i2s_sample_freq {
+
+    I2S_SAMPLE_FREQ_8K,
+
+
+    I2S_SAMPLE_FREQ_16K,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s sample frequency: 44.1K(WS frequency)
+     */
+    I2S_SAMPLE_FREQ_44_1K,
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s sample frequency: 48K(WS frequency)
+     */
+    I2S_SAMPLE_FREQ_48K,
+};
+
+
+/**
+  * @brief i2s channel type
+  */
+enum i2s_channel {
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s mono channel
+     */
+    I2S_CHANNEL_MONO,
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s stereo channel
+     */
+    I2S_CHANNEL_STEREO,
+};
+
+/**
+  * @brief i2s data format type
+  */
+enum i2s_data_fmt {
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S communication format I2S
+     */
+    I2S_DATA_FMT_I2S,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S communication format MSB(right justified)
+     */
+    I2S_DATA_FMT_MSB,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S communication format LSB(left justified)
+     */
+    I2S_DATA_FMT_LSB,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S communication format PCM
+     */
+    I2S_DATA_FMT_PCM,
+};
+
+/**
+  * @brief i2s mode type
+  */
+enum i2s_mode {
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S master mode setting
+     */
+    I2S_MODE_MASTER,
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S slave mode setting
+     */
+    I2S_MODE_SLAVE,
+};
+
+/**
+  * @brief spi ioctl cmd
+  *
+  */
+enum i2s_ioctl_cmd {
+    /*! Compatible version: V0
+     *@Describe:
+     * Set the polarity of WSCLK
+     *@The specific Settings:
+     * (1)left channel WSCLK level is low , right channel WSCLK level is high
+     * (2)left channel WSCLK level is high, right channel WSCLK level is low
+     */
+    I2S_IOCTL_CMD_SET_WSCLK_POL,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s bit width per sample
+     *@The specific Settings:
+     * (1)I2S_SAMPLE_BITS_8BITS
+     * (2)I2S_SAMPLE_BITS_16BITS
+     * (3)I2S_SAMPLE_BITS_24BITS
+     */
+    I2S_IOCTL_CMD_SET_SAMPLE_BITS,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s bit width per sample
+     *@The specific Settings:
+     * (1)I2S_CHANNEL_MONO
+     * (2)I2S_CHANNEL_STEREO
+     */
+    I2S_IOCTL_CMD_SET_CHANNEL,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s communication format
+     *@The specific Settings:
+     * (1)I2S_DATA_FMT_I2S
+     * (2)I2S_DATA_FMT_MSB
+     * (3)I2S_DATA_FMT_LSB
+     */
+    I2S_IOCTL_CMD_SET_DATA_FMT,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s open WSCLK & BCLK & DATA debounce
+     * (Only for i2s slave)
+     */
+    I2S_IOCTL_CMD_SET_DEBOUNCE,
+
+    /*! Compatible version: V0
+     *@Describe:
+     * i2s open duplex using iis0 & iis1
+     */
+    I2S_IOCTL_CMD_SET_DUPLEX,
+};
+
+/**
+  * @brief spi request interrupt flag
+  *
+  */
+enum i2s_irq_flag {
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S interrupt signal that transmits half of the data
+     */
+    I2S_IRQ_FLAG_HALF = BIT(0),
+    /*! Compatible version: V0
+     *@Describe:
+     * I2S interrupt signal that transmits all data
+     */
+    I2S_IRQ_FLAG_FULL = BIT(1),
+};
+
+
+/* User interrupt handle */
+typedef void (*i2s_irq_hdl)(uint32 irq, uint32 irq_data);
+
+/* I2S api for user */
+struct i2s_device {
+    struct dev_obj dev;
+};
+
+struct i2s_hal_ops{
+    struct devobj_ops ops;
+    int32(*open)(struct i2s_device *i2s, enum i2s_mode mode, enum i2s_sample_freq frequency, enum i2s_sample_bits bits);
+    int32(*close)(struct i2s_device *i2s);
+    int32(*ioctl)(struct i2s_device *i2s, uint32 cmd, uint32 param);
+    int32(*read)(struct i2s_device *i2s, void *buf, uint32 len);
+    int32(*write)(struct i2s_device *i2s, const void *buf, uint32 len);
+    int32(*write_scatter)(struct i2s_device *i2s, const scatter_data *data, uint32 count);
+    int32(*request_irq)(struct i2s_device *i2s, uint32 irq_flag, i2s_irq_hdl irqhdl, uint32 irq_data);
+    int32(*release_irq)(struct i2s_device *i2s, uint32 irq_flag);
+};
+
+
+/* I2S API functions */
+
+/**
+ * @brief i2s_open.
+ *
+ * @Compatible version: V0
+ *
+ * @note  This function must be called before any I2S driver operations.
+ *
+ * @param i2s       The address of I2S device in the RTOS.
+ * @param mode      I2S work mode setting        - see "enum i2s_mode".
+ * @param frequency I2S sample frequency setting - see "enum i2s_sample_freq".
+ * @param bits      I2S sample bits setting      - see "enum i2s_sample_bits".
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 i2s_open(struct i2s_device *i2s, enum i2s_mode mode, enum i2s_sample_freq frequency, enum i2s_sample_bits bits);
+
+/**
+ * @brief i2s_close.
+ *
+ * @Compatible version: V0
+ *
+ * @param i2s       The address of I2S device in the RTOS.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 i2s_close(struct i2s_device *i2s);
+
+/**
+ * @brief i2s_write.
+ *
+ * @Compatible version: V0
+ *
+ * @param i2s       The address of I2S device in the RTOS.
+ * @param buf       Write the start address of buf.
+ * @param len       Write length, uint: byte.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 i2s_write(struct i2s_device *i2s, const void *buf, uint32 len);
+
+int32 i2s_write_scatter(struct i2s_device *i2s, const scatter_data *data, uint32 count);
+
+/**
+ * @brief i2s_read.
+ *
+ * @Compatible version: V0
+ *
+ * @param i2s       The address of I2S device in the RTOS.
+ * @param buf       Read the start address of buf.
+ * @param len       Read length, uint: byte.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 i2s_read(struct i2s_device *i2s, void *buf, uint32 len);
+
+/**
+ * @brief i2s_ioctl.
+ *
+ * @Compatible version: V0
+ *
+ * @param i2s       The address of I2S device in the RTOS.
+ * @param cmd       Control command - see"enum i2s_ioctl_cmd".
+ * @param param     Parameters required to execute the current Control command.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 i2s_ioctl(struct i2s_device *i2s, uint32 cmd, uint32 param);
+
+/**
+ * @brief i2s_request_irq.
+ *
+ * @Compatible version: V0
+ *
+ * @param i2s       The address of I2S device in the RTOS.
+ * @param irq_flag  The type of interrupt - see"enum i2s_irq_flag".
+ * @param irqhdl    The interrupt function.
+ * @param irq_data  The parameters of the interrupt function
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 i2s_request_irq(struct i2s_device *i2s, uint32 irq_flag, i2s_irq_hdl irqhdl, uint32 irq_data);
+
+/**
+ * @brief i2s_release_irq.
+ *
+ * @Compatible version: V0
+ *
+ * @param i2s       The address of I2S device in the RTOS.
+ * @param irq_flag  The type of interrupt - see"enum i2s_irq_flag".
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 i2s_release_irq(struct i2s_device *i2s, uint32 irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

sdk/include/hal/jpeg.h

@@ -0,0 +1,79 @@
+#ifndef _HAL_JPEG_H_
+#define _HAL_JPEG_H_
+
+enum jpg_device_irq_flag {
+    JPG_IRQ_FLAG_JPG_DONE     = BIT(0),
+    JPG_IRQ_FLAG_JPG_BUF_FULL = BIT(1),
+    JPG_IRQ_FLAG_ERROR        = BIT(2),
+    JPG_IRQ_FLAG_PIXEL_DONE   = BIT(3),
+};
+
+enum jpg_ioctl_cmd {
+	JPG_IOCTL_CMD_IS_ONLINE,
+    JPG_IOCTL_CMD_SET_ADR,
+    JPG_IOCTL_CMD_SET_QT,
+    JPG_IOCTL_CMD_SET_SIZE,
+    JPG_IOCTL_CMD_SET_SRC_FROM,
+    JPG_IOCTL_CMD_UPDATE_QT,
+	JPG_IOCTL_CMD_DECODE_TAG,
+	JPG_IOCTL_CMD_OPEN_DBG,
+	JPG_IOCTL_CMD_SOFT_KICK,
+	JPG_IOCTL_CMD_HW_CHK,
+	JPG_IOCTL_CMD_IS_IDLE,
+    JPG_IOCTL_CMD_SET_INIT_FINISH,
+    JPG_IOCTL_CMD_GET_INIT_FLAG,
+};
+
+
+typedef int32(*jpg_irq_hdl)(uint32 irq_flag, uint32 irq_data, uint32 param1, uint32 param2);
+
+struct jpg_device {
+    struct dev_obj dev;
+};
+
+struct jpeg_hal_ops{
+    struct devobj_ops ops;
+    int32(*open)(struct jpg_device *jpg);
+    int32(*close)(struct jpg_device *jpg);
+	int32(*suspend)(struct jpg_device *jpg);
+	int32(*resume)(struct jpg_device *jpg);
+    int32(*init)(struct jpg_device *jpg, uint32 table_idx, uint32 qt);
+	int32(*decode)(struct jpg_device *jpg,uint32 photo);
+    int32(*ioctl)(struct jpg_device *jpg, enum jpg_ioctl_cmd cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct jpg_device *jpg, jpg_irq_hdl irq_hdl, uint32 irq_flag,  uint32 irq_data);
+    int32(*release_irq)(struct jpg_device *jpg, uint32 irq_flag);
+};
+
+#ifdef TXW80X
+#define JPG_NUM   1
+#endif
+
+#ifdef TXW81X
+#define JPG_NUM   2
+#endif
+
+int32 jpg_open(struct jpg_device *jpg);
+int32 jpg_close(struct jpg_device *jpg);
+int32 jpg_init(struct jpg_device *jpg, uint32 table_idx, uint32 qt);
+int32 jpg_updata_dqt(struct jpg_device *p_jpg, uint32 *dqtbuf);
+int32 jpg_suspend(struct jpg_device *jpg);
+int32 jpg_resume(struct jpg_device *jpg);
+int32 jpg_set_size(struct jpg_device *p_jpg, uint32 h, uint32 w);
+int32 jpg_set_addr(struct jpg_device *jpg, uint32 addr, uint32 buflen);
+int32 jpg_set_qt(struct jpg_device *jpg, uint32 qt);
+int32 jpg_open_debug(struct jpg_device *p_jpg, uint8 enable);
+int32 jpg_soft_kick(struct jpg_device *p_jpg, uint8 kick);
+int32 jpg_decode_target(struct jpg_device *p_jpg, uint8 to_scaler);
+int32 jpg_decode_photo(struct jpg_device *p_jpg, uint32 photo);
+int32 jpg_request_irq(struct jpg_device *jpg, jpg_irq_hdl irq_hdl, uint32 irq_flags,  void *irq_data);
+int32 jpg_release_irq(struct jpg_device *jpg, uint32 irq_flags);
+int32 jpg_set_data_from(struct jpg_device *p_jpg, uint8 src_from);
+int32 jpg_set_hw_check(struct jpg_device *p_jpg, uint8 enable);
+int32 jpg_is_online(struct jpg_device *p_jpg);
+int32 jpg_is_idle(struct jpg_device *p_jpg);
+int32 jpg_set_init_finish(struct jpg_device *p_jpg,uint32_t value);
+int32 jpg_get_init_flag(struct jpg_device *p_jpg);
+
+
+
+#endif

sdk/include/hal/lcdc.h

@@ -0,0 +1,580 @@
+#ifndef HAL_LCDC_H
+#define HAL_LCDC_H
+
+/* User interrupt handle */
+typedef int32(*lcdc_irq_hdl)(uint32 irq_flags, uint32 irq_data, uint32 param);
+
+/**
+  * @brief UART ioctl_cmd type
+  */
+enum lcdc_ioctl_cmd {
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_TIMEOUT_INF,
+
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_AUTO_KICK_EN,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_GAMMA_SATURATION_EN,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_GAMMA_SATURATION_VAL,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_CCM_EN,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_COLOR_MODE,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_BUS_MODE,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_INTERFACE_MODE,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_COLRARRAY,		
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_LCD_VAILD_SIZE,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_LCD_VISIBLE_SIZE,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_SIGNAL_CONFIG,		
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_MCU_SIGNAL_CONFIG,		
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_INVALID_LINE,		
+	
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_VALID_DOT,
+	
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_HLW_VLW,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_VIDEO_BIG_ENDIAN,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_VIDEO_SIZE,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_P0_ROTATE_Y_SRC_ADDR,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_P0_ROTATE_U_SRC_ADDR,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_P0_ROTATE_V_SRC_ADDR,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_P1_ROTATE_Y_SRC_ADDR,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_P1_ROTATE_U_SRC_ADDR,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_P1_ROTATE_V_SRC_ADDR,		
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_P0P1_ROTATE_START_ADDR,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_P0_UP,		
+
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_P0_P1_EN,		
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_LINE_BUF_NUM,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_LINE_BUF_Y,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_LINE_BUF_U,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_LINE_BUF_V,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_MIRROR,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_ROTATE_SET_SIZE,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_VIDEO_MODE,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_VIDEO_START_ADDR,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_VIDEO_EN,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_SIZE,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_START_ADDR,		
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_LUTDMA_ADDR,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_DMA_ADDR,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_DMA_LEN,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_FORMAT,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_ALPHA,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_ENC_HEAD,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_ENC_DIAP,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_EN,		
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_ENC_SRC_ADDR,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_OSD_ENC_DST_ADDR,
+	
+	/*! Compatible version: V2;
+	 *@ Describe:
+	 *
+	 */
+	LCDC_SET_OSD_ENC_SRC_LEN,
+
+	/*! Compatible version: V2;
+	 *@ Describe:
+	 *
+	 */
+	LCDC_GET_OSD_ENC_DST_LEN,
+
+	/*! Compatible version: V2;
+	 *@ Describe:
+	 *
+	 */
+	LCDC_SET_OSD_ENC_START,
+
+	/*! Compatible version: V2;
+	 *@ Describe:
+	 *
+	 */
+	LCDC_MCU_CPU_WRITE,
+
+
+	/*! Compatible version: V2;
+	 *@ Describe:
+	 *
+	 */
+	LCDC_MCU_CPU_READ,
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	LCDC_SET_START_RUN,	
+
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+    LCDC_SET_TE_EDGE,
+
+    /*! Compatible version: V2;
+     *@ Describe:饱和度使能
+     *
+     */
+    LCDC_SET_SATURATION_EN,
+
+    /*! Compatible version: V2;
+     *@ Describe:饱和度的值
+        0x0：0%
+        0x1：12.5%
+        0x2：25.0%
+        0x3：37.5%
+        0x4：50.0%
+        0x5：62.5%
+        0x6：75.0%
+        0x7：87.5%
+        0x8：100.0%
+        0x9：112.5%
+        0xA：125.0%
+        0xB：137.5%
+        0xC：150.0%
+        0xD：162.5%
+        0xE：175.0%
+        0xF：187.5%
+        0x10：200.0%
+     *
+     */
+    LCDC_SET_SATURATION_VALUE,
+
+    /*! Compatible version: V2;
+     *@ Describe:对比度使能
+     *
+     */
+    LCDC_SET_CONSTRAST_EN,
+    /*! Compatible version: V2;
+     *@ Describe:对比度的值
+        0x0：50%
+        0x1：53.125%
+        0x2：56.25%
+        0x3：59.375%
+        0x4：62.5%
+        0x5：65.625%
+        0x6：68.75%
+        0x7：71.875%
+        0x8：75.0%
+        0x9：78.125%
+        0xA：81.25%
+        0xB：84.375%
+        0xC：87.5%
+        0xD：90.625%
+        0xE：93.75%
+        0xF：96.875%
+        0x10：100%
+        0x11：103.125%
+        0x12：106.25%
+        0x13：109.375%
+        0x14：112.5%
+        0x15：115.625%
+        0x16：118.75%
+        0x17：121.875%
+        0x18：125%
+        0x19：128.125%
+        0x1A：131.25%
+        0x1B：134.375%
+        0x1C：137.5%
+        0x1D：140.625%
+        0x1E：143.75%
+        0x1F：146.875%
+     *
+     */
+    LCDC_SET_CONSTRAST_VALUE,
+    /*! Compatible version: V2;
+     *@ Describe:gamma的使能
+     *
+     */
+    LCDC_SET_GAMMA_EN,
+
+    /*! Compatible version: V2;
+     *@ Describe:配置GAMMA的rgb索引表
+     表大小是256byte,只支持sram地址
+     *
+     */
+    LCDC_SET_GAMMA_R,
+    LCDC_SET_GAMMA_G,
+    LCDC_SET_GAMMA_B,
+
+    LCDC_SET_CCM_COEF1,
+    LCDC_SET_CCM_COEF0,
+    LCDC_SET_CCM_COEF2,
+    LCDC_SET_CCM_COEF3,
+    LCDC_GET_CON,
+};
+
+
+enum lcdc_color_mode {
+    LCD_MODE_565 = 16,
+	LCD_MODE_666 = 18,
+	LCD_MODE_888 = 24,		
+};
+
+enum lcdc_bus_width {
+    LCD_BUS_WIDTH_6  = 6,
+	LCD_BUS_WIDTH_8  = 8,
+	LCD_BUS_WIDTH_9  = 9,
+	LCD_BUS_WIDTH_12 = 12,
+	LCD_BUS_WIDTH_16 = 16,
+	LCD_BUS_WIDTH_18 = 18,
+	LCD_BUS_WIDTH_24 = 24,
+};
+
+enum lcdc_interface_mode {
+    LCD_BUS_RGB,
+	LCD_BUS_I80,
+	LCD_BUS_I68,		
+};
+
+enum lcdc_rotate_mode {
+    LCD_ROTATE_0,
+	LCD_ROTATE_90,
+	LCD_ROTATE_180,	
+	LCD_ROTATE_270,		
+};
+
+enum lcdc_video_mode {
+    VIDEO_FROM_SCALE,
+	VIDEO_FROM_MEMORY_NO_ROTATE,
+	VIDEO_FROM_MEMORY_ROTATE,
+};
+
+enum lcdc_osd_format {
+    OSD_RGB_256,
+	OSD_RGB_565,
+	OSD_RGB_888,
+};
+
+
+struct lcdc_device {
+    struct dev_obj dev;
+};
+
+struct lcdc_hal_ops {
+	struct devobj_ops ops;
+    int32(*init)(struct lcdc_device *lcdc_dev);
+	int32(*suspend)(struct lcdc_device *lcdc_dev);
+	int32(*resume)(struct lcdc_device *lcdc_dev);		
+    int32(*baudrate)(struct lcdc_device *lcdc_dev, uint32 baudrate);
+    int32(*open)(struct lcdc_device *lcdc_dev);
+    int32(*close)(struct lcdc_device *lcdc_dev);
+    int32(*ioctl)(struct lcdc_device *lcdc_dev, enum lcdc_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct lcdc_device *lcdc_dev, uint32 irq_flag, lcdc_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct lcdc_device *lcdc_dev, uint32 irq_flag);
+};
+
+
+
+
+
+
+int32 lcdc_init(struct lcdc_device *p_lcdc);
+int32 lcdc_open(struct lcdc_device *p_lcdc);
+int32 lcdc_close(struct lcdc_device *p_lcdc);
+int32 lcdc_request_irq(struct lcdc_device *p_lcdc, uint32 irq_flags, lcdc_irq_hdl irq_hdl, uint32 irq_data);
+int32 lcdc_release_irq(struct lcdc_device *p_lcdc, uint32 irq_flags);
+int32 lcdc_set_baudrate(struct lcdc_device *p_lcdc, uint32 mclk);
+int32 lcdc_set_color_mode(struct lcdc_device *p_lcdc, enum lcdc_color_mode cm);
+int32 lcdc_set_bus_width(struct lcdc_device *p_lcdc, enum lcdc_bus_width bw);
+int32 lcdc_set_interface(struct lcdc_device *p_lcdc, enum lcdc_interface_mode im);
+int32 lcdc_set_colrarray(struct lcdc_device *p_lcdc, uint8 colrarray);
+int32 lcdc_set_lcd_vaild_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num);
+int32 lcdc_set_lcd_visible_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h,uint8 pixel_dot_num);
+int32 lcdc_signal_config(struct lcdc_device *p_lcdc, uint8 vs_en,uint8 hs_en,uint8 de_en,uint8 vs_inv,uint8 hs_inv,uint8 de_inv,uint8 clk_inv);
+int32 lcdc_mcu_signal_config(struct lcdc_device *p_lcdc, uint8 value);
+int32 lcdc_set_invalid_line(struct lcdc_device *p_lcdc, uint8 invalid_line);
+int32 lcdc_set_valid_dot(struct lcdc_device *p_lcdc, uint32 w_start,uint32 h_start);
+int32 lcdc_set_hlw_vlw(struct lcdc_device *p_lcdc, uint32 hlw,uint32 vlw);
+int32 lcdc_set_bigendian(struct lcdc_device *p_lcdc, uint8 en);
+int32 lcdc_set_video_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h);
+int32 lcdc_set_p0_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
+int32 lcdc_set_p0_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
+int32 lcdc_set_p0_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
+int32 lcdc_set_p1_rotate_y_src_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
+int32 lcdc_set_p1_rotate_u_src_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
+int32 lcdc_set_p1_rotate_v_src_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
+int32 lcdc_set_rotate_p0_up(struct lcdc_device *p_lcdc, uint8 en);
+int32 lcdc_set_rotate_p0p1_start_location(struct lcdc_device *p_lcdc, uint32 x0,uint32 y0,uint32 x1,uint32 y1);
+int32 lcdc_set_rotate_linebuf_num(struct lcdc_device *p_lcdc, uint32 linebuf);
+int32 lcdc_set_rotate_linebuf_y_addr(struct lcdc_device *p_lcdc, uint32 yaddr);
+int32 lcdc_set_rotate_linebuf_u_addr(struct lcdc_device *p_lcdc, uint32 uaddr);
+int32 lcdc_set_rotate_linebuf_v_addr(struct lcdc_device *p_lcdc, uint32 vaddr);
+int32 lcdc_set_rotate_mirror(struct lcdc_device *p_lcdc, uint8 mirror,enum lcdc_rotate_mode rotate);
+int32 lcdc_set_rotate_p0p1_size(struct lcdc_device *p_lcdc, uint32 w0,uint32 h0,uint32 w1,uint32 h1);
+int32 lcdc_set_video_data_from(struct lcdc_device *p_lcdc, enum lcdc_video_mode vm);
+int32 lcdc_set_video_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y);
+int32 lcdc_set_video_en(struct lcdc_device *p_lcdc, uint8 en);
+int32 lcdc_set_osd_size(struct lcdc_device *p_lcdc, uint32 w,uint32 h);
+int32 lcdc_set_osd_start_location(struct lcdc_device *p_lcdc, uint32 x,uint32 y);
+int32 lcdc_set_osd_dma_addr(struct lcdc_device *p_lcdc, uint32 addr);
+int32 lcdc_set_osd_lut_addr(struct lcdc_device *p_lcdc, uint32 addr);
+int32 lcdc_set_osd_dma_len(struct lcdc_device *p_lcdc, uint32 len);
+int32 lcdc_set_osd_format(struct lcdc_device *p_lcdc, enum lcdc_osd_format osd_format);
+int32 lcdc_set_osd_alpha(struct lcdc_device *p_lcdc, uint32 alpha);
+int32 lcdc_set_osd_enc_head(struct lcdc_device *p_lcdc, uint32 head, uint32 head_tran);
+int32 lcdc_set_osd_enc_diap(struct lcdc_device *p_lcdc, uint32 diap, uint32 diap_tran);
+int32 lcdc_set_osd_en(struct lcdc_device *p_lcdc, uint8 en);
+int32 lcdc_set_osd_enc_src_addr(struct lcdc_device *p_lcdc, uint32 addr);
+int32 lcdc_set_osd_enc_dst_addr(struct lcdc_device *p_lcdc, uint32 addr);
+int32 lcdc_set_p0p1_enable(struct lcdc_device *p_lcdc, uint8 p0_en,uint8 p1_en);
+
+int32 lcdc_set_osd_enc_src_len(struct lcdc_device *p_lcdc, uint32 len);
+int32 lcdc_get_osd_enc_dst_len(struct lcdc_device *p_lcdc);
+int32 lcdc_osd_enc_start_run(struct lcdc_device *p_lcdc,uint8_t en);
+int32 lcdc_set_start_run(struct lcdc_device *p_lcdc);
+int32 lcdc_video_enable_gamma_saturation(struct lcdc_device *p_lcdc, uint8 gamma,uint8 saturation);
+int32 lcdc_video_gamma_saturation_val(struct lcdc_device *p_lcdc, uint32 gamma,uint32 saturation);
+int32 lcdc_video_enable_ccm(struct lcdc_device *p_lcdc, uint8 ccm);
+int32 lcdc_mcu_write_reg(struct lcdc_device *p_lcdc,uint8 data);
+int32 lcdc_mcu_write_data(struct lcdc_device *p_lcdc,uint8 data);
+int32 lcdc_video_enable_auto_ks(struct lcdc_device *p_lcdc, uint8 enable);
+int32 lcdc_set_timeout_info(struct lcdc_device *p_lcdc, uint8 enable,uint8 timeout);
+int32 lcdc_mcu_read_data(struct lcdc_device *p_lcdc,uint8 *read_buf,uint8 cmd,uint8 len);
+
+int32 lcdc_set_te_edge(struct lcdc_device *p_lcdc,uint8 edge);
+int32 lcdc_video_enable_saturation(struct lcdc_device *p_lcdc, uint8 en);
+int32 lcdc_video_set_saturation_val(struct lcdc_device *p_lcdc, uint8 val);
+int32 lcdc_video_enable_constarast(struct lcdc_device *p_lcdc, uint8 en);
+int32 lcdc_video_set_constarast_val(struct lcdc_device *p_lcdc, uint8 val);
+int32 lcdc_video_enable_gamma(struct lcdc_device *p_lcdc, uint8 en);
+int32 lcdc_video_set_gamma_R(struct lcdc_device *p_lcdc, uint32 addr);
+int32 lcdc_video_set_gamma_G(struct lcdc_device *p_lcdc, uint32 addr);
+int32 lcdc_video_set_gamma_B(struct lcdc_device *p_lcdc, uint32 addr);
+int32 lcdc_video_set_CCM_COEF0(struct lcdc_device *p_lcdc, uint32 matrix);
+int32 lcdc_video_set_CCM_COEF1(struct lcdc_device *p_lcdc, uint32 matrix);
+int32 lcdc_video_set_CCM_COEF2(struct lcdc_device *p_lcdc, uint32 matrix);
+int32 lcdc_video_set_CCM_COEF3(struct lcdc_device *p_lcdc, uint32 offset);
+int32 lcdc_get_con(struct lcdc_device *p_lcdc);
+#endif
+

sdk/include/hal/led.h

@@ -0,0 +1,350 @@
+#ifndef _HAL_LED_H_
+#define _HAL_LED_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief LED work_mode type
+  */
+enum led_work_mode {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Work mode for common anode digital tube
+     */
+    LED_WORK_MODE_COMMON_ANODE,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Work mode for common cathode digital tube
+     */
+    LED_WORK_MODE_COMMON_CATHODE,
+};
+
+/**
+  * @brief LED seg_cnt type
+  */
+enum led_seg_cnt {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 1 piece
+     */
+    LED_SEG_CNT_1,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 2 piece
+     */
+    LED_SEG_CNT_2,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 3 piece
+     */
+    LED_SEG_CNT_3,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 4 piece
+     */
+    LED_SEG_CNT_4,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 5 piece
+     */
+    LED_SEG_CNT_5,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 6 piece
+     */
+    LED_SEG_CNT_6,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 7 piece
+     */
+    LED_SEG_CNT_7,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 8 piece
+     */
+    LED_SEG_CNT_8,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 9 piece
+     */
+    LED_SEG_CNT_9,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 10 piece
+     */
+    LED_SEG_CNT_10,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 11 piece
+     */
+    LED_SEG_CNT_11,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of segument: 12 piece
+     */
+    LED_SEG_CNT_12,
+};
+
+/**
+  * @brief LED com_cnt type
+  */
+enum led_com_cnt {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 1 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_1,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 2 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_2,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 3 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_3,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 4 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_4,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 5 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_5,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 6 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_6,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 7 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_7,
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Amount of com: 8 piece
+     *@ Note:
+     * It is also position for "led_open" function's parameter
+     */
+    LED_COM_CNT_8,
+};
+
+/**
+  * @brief LED irq_flag type
+  */
+enum led_irq_flag {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * emmm...
+     */
+    LED_IRQ_FLAG_INT = BIT(0),
+};
+
+/**
+  * @brief LED ioctl_cmd type
+  */
+enum led_ioctl_cmd {
+
+    /*! Compatible version: V0;
+     *@ Describe:
+     * Set scan frequency and set the length of time
+     */
+    LED_IOCTL_CMD_SET_SCAN_FREQ,
+};
+
+
+
+/* User interrupt handle */
+typedef void (*led_irq_hdl)(uint32 irq, uint32 irq_data);
+
+/* LED api for user */
+struct led_device {
+    struct dev_obj dev;
+};
+
+struct led_hal_ops{
+    struct devobj_ops ops;
+    int32(*open)(struct led_device *led, enum led_work_mode work_mode, enum led_seg_cnt seg_cnt, enum led_com_cnt com_cnt);
+    int32(*on)(struct led_device *led, uint32 num, enum led_com_cnt pos);
+    int32(*off)(struct led_device *led, enum led_com_cnt pos);
+    int32(*close)(struct led_device *led);
+    int32(*ioctl)(struct led_device *led, enum led_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+    int32(*request_irq)(struct led_device *led, enum led_irq_flag irq_flag, led_irq_hdl irq_hdl, uint32 irq_data);
+    int32(*release_irq)(struct led_device *led, enum led_irq_flag irq_flag);
+};
+
+
+/* LED API functions */
+
+
+
+/**
+ * @brief led_open
+ *
+ * @Compatible version: V0;
+ *
+ * @note  This function must be called before any led driver operations.
+ *
+ * @param led       The address of led device in the RTOS.
+ * @param work_mode The tube.work mode setting   - see "enum led_work_mode".
+ * @param seg_cnt   The tube's segmument amounts - see "enum led_seg_cnt".
+ * @param com_cnt   The tube's com amounts       - see "enum led_com_cnt".
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 led_open(struct led_device *led, enum led_work_mode work_mode, enum led_seg_cnt seg_cnt, enum led_com_cnt com_cnt);
+
+/**
+ * @brief led_on
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param led       The address of led device in the RTOS.
+ * @param num       What does the user want to display the numbers, must be 0~9.
+ * @param pos       Where does the user want to display the numbers - see "enum led_com_cnt".
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 led_on(struct led_device *led, uint32 num, enum led_com_cnt pos);
+
+/**
+ * @brief led_off
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param led       The address of led device in the RTOS.
+ * @param num       What does the user want to display the numbers, must be 0~9.
+ * @param pos       Where does the user want to display the numbers - see "enum led_com_cnt".
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 led_off(struct led_device *led, enum led_com_cnt pos);
+
+
+/**
+ * @brief led_close
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param led       The address of led device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 led_close(struct led_device *led);
+
+/**
+ * @brief led_ioctl
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param led       The address of led device in the RTOS.
+ * @param ioctl_cmd The ioctl command - - see "enum led_ioctl_cmd".
+ * @param param1    The parameter to function.
+ * @param param2    The parameter to function.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 led_ioctl(struct led_device *led, enum led_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+
+/**
+ * @brief led_request_irq
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param led       The address of led device in the RTOS.
+ * @param irq_flag  The type of interrupt - see"enum led_irq_flag".
+ * @param irqhdl    The interrupt function.
+ * @param irq_data  The parameter of the interrupt function
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 led_request_irq(struct led_device *led, enum led_irq_flag irq_flag, led_irq_hdl irq_hdl, uint32 irq_data);
+
+/**
+ * @brief led_release_irq
+ *
+ * @Compatible version: V0;
+ *
+ * @note  .
+ *
+ * @param led       The address of led device in the RTOS.
+ * @param .
+ * @param .
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 led_release_irq(struct led_device *led, enum led_irq_flag irq_flag);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

sdk/include/hal/netdev.h

@@ -0,0 +1,82 @@
+#ifndef _HAL_NETDEVICE_H_
+#define _HAL_NETDEVICE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum netdev_events {
+    NETDEV_EVT_LINK_STATUS_CHANGE,
+};
+
+enum netdev_link_status {
+    LINK_DOWN,
+    LINK_OK,
+};
+
+enum netdev_phy_event {
+    NETDEV_PHY_EVENT_LINK_CHANGED,
+};
+
+enum netdev_ioctl_cmd {
+    NETDEV_IOCTL_GET_ADDR,
+    NETDEV_IOCTL_SET_ADDR,
+    NETDEV_IOCTL_GET_LINK_STATUS,
+    NETDEV_IOCTL_GET_LINK_SPEED,
+    NETDEV_IOCTL_FORCE_LINK,
+    NETDEV_IOCTL_SET_FILTER_MAC,
+    NETDEV_IOCTL_SET_WIFI_MODE,
+    NETDEV_IOCTL_HOOK_INPUTDATA,
+    NETDEV_IOCTL_ENABLE_WIFIBRIDGE,
+    NETDEV_IOCTL_ENABLE_ICMPMNTR,
+    NETDEV_IOCTL_CLEAR_ROUTETBL,
+};
+
+struct netdev;
+
+typedef void (*netdev_input_cb)(struct netdev *ndev, uint8 *data, uint32 size, void *priv);
+typedef void (*netdev_event_cb)(struct netdev *ndev, uint32 event, uint32 param);
+
+struct netdev {
+    struct dev_obj dev;
+    void  *stack_data;
+    uint64 rx_bytes, tx_bytes;
+};
+
+struct netdev_hal_ops {
+    struct devobj_ops ops;
+    int32(*open)(struct netdev *ndev, netdev_input_cb input_cb, netdev_event_cb evt_cb, void *priv);
+    int32(*close)(struct netdev *ndev);
+    int32(*ioctl)(struct netdev *ndev, uint32 cmd, uint32 param1, uint32 param2);
+    int32(*send_data)(struct netdev *ndev, uint8 *p_data, uint32 size);
+    int32(*send_scatter_data)(struct netdev *ndev, scatter_data *data, uint32 count);
+    void (*phy_event)(void *phydev, uint32 event, uint32 param1, uint32 param2);
+    void (*mdio_write)(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr, uint16 data);
+    int32(*mdio_read)(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr);
+};
+
+int32 netdev_open(struct netdev *ndev, netdev_input_cb input_cb, netdev_event_cb evt_cb, void *priv);
+int32 netdev_close(struct netdev *ndev);
+int32 netdev_send_data(struct netdev *ndev, uint8 *p_data, uint32 size);
+int32 netdev_send_scatter_data(struct netdev *ndev, scatter_data *p_data, uint32 count);
+int32 netdev_ioctl(struct netdev *ndev, uint32 cmd, uint32 param1, uint32 param2);
+void netdev_mdio_write(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr, uint16 data);
+int32 netdev_mdio_read(struct netdev *ndev, uint16 phy_addr, uint16 reg_addr);
+
+#define netdev_link_speed(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_GET_LINK_SPEED, 0, 0)
+#define netdev_link_status(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_GET_LINK_STATUS, 0, 0)
+#define netdev_set_macaddr(ndev, addr) netdev_ioctl(ndev, NETDEV_IOCTL_SET_ADDR, (uint32)addr, 0)
+#define netdev_get_macaddr(ndev, addr) netdev_ioctl(ndev, NETDEV_IOCTL_GET_ADDR, (uint32)addr, 0)
+#define netdev_force_link(ndev, link_speed, duplex_flag) netdev_ioctl(ndev, NETDEV_IOCTL_FORCE_LINK, link_speed, duplex_flag)
+#define netdev_set_filter_mac(ndev, mac_table, size) netdev_ioctl(ndev, NETDEV_IOCTL_SET_FILTER_MAC, (uint32)mac_table, (uint32)size)
+#define netdev_set_wifi_mode(ndev, mode) netdev_ioctl(ndev, NETDEV_IOCTL_SET_WIFI_MODE, mode, 0)
+#define netdev_hook_inputdata(ndev, data, len) netdev_ioctl(ndev, NETDEV_IOCTL_HOOK_INPUTDATA, data, len)
+#define netdev_set_wifi_bridge(ndev, en) netdev_ioctl(ndev, NETDEV_IOCTL_ENABLE_WIFIBRIDGE, en, 0)
+#define netdev_clear_routetbl(ndev) netdev_ioctl(ndev, NETDEV_IOCTL_CLEAR_ROUTETBL, 0, 0)
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+

sdk/include/hal/of.h

@@ -0,0 +1,48 @@
+#ifndef HAL_OF_H
+#define HAL_OF_H
+
+enum of_instr_mode {
+    CUSADA8_INIT_ZERO,
+	CUSADA8_INIT_ACC,
+	CUHADD8_AVG,		
+};
+
+enum of_ioctl_cmd {
+    /*! Compatible version: V2;
+     *@ Describe:
+     *
+     */
+	OF_INSTR_MODE,
+
+	CAL_PIXEL_NUM,
+
+	CAL_ROW_NUM,
+
+	SET_ROW_SIZE,
+
+	SET_OF_ADDR,
+
+	GET_CAL_ACC,
+};
+
+struct of_device {
+    struct dev_obj dev;
+};
+
+struct of_hal_ops {
+	struct devobj_ops ops;
+	int32(*init)(struct of_device *of_dev);
+    int32(*ioctl)(struct of_device *of_dev, enum of_ioctl_cmd ioctl_cmd, uint32 param1, uint32 param2);
+};
+
+
+int32 of_init(struct of_device *p_of);
+int32 of_set_instr_mode(struct of_device *p_of,enum of_instr_mode instr_format);
+int32 of_set_pixel_num(struct of_device *p_of,uint32 pixel_num);
+int32 of_set_row_num(struct of_device *p_of,uint32 row_num);
+int32 of_set_row_size(struct of_device *p_of,uint32 row_size);
+int32 of_set_addr(struct of_device *p_of,uint32 addr0,uint32 addr1);
+int32 of_get_acc(struct of_device *p_of);
+
+
+#endif

sdk/include/hal/pdm.h

@@ -0,0 +1,198 @@
+#ifndef _HAL_PDM_H_
+#define _HAL_PDM_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief pdm sample frequency type
+  */
+enum pdm_sample_freq {
+    /*! Compatible version: V0
+     *@Describe:
+     * pdm sample frequency: 8K
+     */
+    PDM_SAMPLE_FREQ_8K,
+    /*! Compatible version: V0
+     *@Describe:
+     * pdm sample frequency: 16K
+     */
+    PDM_SAMPLE_FREQ_16K,
+    /*! Compatible version: V0
+     *@Describe:
+     * pdm sample frequency: 32K
+     */
+    PDM_SAMPLE_FREQ_32K,
+    /*! Compatible version: V0
+     *@Describe:
+     * pdm sample frequency: 48K
+     */
+    PDM_SAMPLE_FREQ_48K,
+};
+
+/**
+  * @brief pdm channel of working mode type
+  */
+enum pdm_channel {
+    /*! Compatible version: V0
+     *@Describe:
+     * channel of working mode: left channel
+     */
+    PDM_CHANNEL_LEFT,
+    /*! Compatible version: V0
+     *@Describe:
+     * channel of working mode: right channel
+     */
+    PDM_CHANNEL_RIGHT,
+    /*! Compatible version: V0
+     *@Describe:
+     * channel of working mode: stereo channel
+     */
+    PDM_CHANNEL_STEREO,
+};
+
+/**
+  * @brief pdm interrupt type
+  */
+enum pdm_irq_flag {
+    /*! Compatible version: V0
+     *@Describe:
+     * pdm module receive data half of buf len
+     */
+    PDM_IRQ_FLAG_DMA_HF = BIT(0),
+    /*! Compatible version: V0
+     *@Describe:
+     * pdm module receive data full of buf len
+     */
+    PDM_IRQ_FLAG_DMA_OV = BIT(1),
+};
+
+/**
+  * @brief pdm ioctl cmd
+  */
+enum pdm_ioctl_cmd {
+    /*! Compatible version: V0
+     *@Describe:
+     * Left and right channels interchange
+     */
+    PDM_IOCTL_CMD_LR_CHANNEL_INTERCHANGE,
+};
+
+
+/* User interrupt handle */
+typedef void (*pdm_irq_hdl)(uint32 irq, uint32 irq_data);
+
+/* PDM api for user */
+struct pdm_device {
+    struct dev_obj dev;
+};
+
+struct pdm_hal_ops{
+    struct devobj_ops ops;
+    int32 (*open       )(struct pdm_device *pdm, enum pdm_sample_freq freq, enum pdm_channel channel);
+    int32 (*read       )(struct pdm_device *pdm, void *buf, uint32 len);
+    int32 (*close      )(struct pdm_device *pdm);
+    int32 (*request_irq)(struct pdm_device *pdm, enum pdm_irq_flag, pdm_irq_hdl irq_hdl, uint32 data);
+    int32 (*release_irq)(struct pdm_device *pdm, enum pdm_irq_flag irq_flag);
+    int32 (*ioctl      )(struct pdm_device *pdm, enum pdm_ioctl_cmd cmd, uint32 param);
+};
+
+/*  PDM API functions */
+
+/**
+ * @brief pdm_open
+ *
+ * @Compatible version: V0
+ *
+ * @note  This function must be called before any pdm driver operations.
+ *
+ * @param pdm       The address of pdm device in the RTOS.
+ * @param freq      PDM sample frequency setting        - see "enum pdm_sample_freq".
+ * @param channel   PDM channel of working mode setting - see "enum pdm_channel".
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 pdm_open(struct pdm_device *pdm, enum pdm_sample_freq freq, enum pdm_channel channel);
+
+/**
+ * @brief pdm_read
+ *
+ * @Compatible version: V0
+ *
+ * @note Turn PDM module on.
+ *
+ * @param pdm       The address of pdm device in the RTOS.
+ * @param buf       The pointer of receive buf.
+ * @param channel   PDM module receive length.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 pdm_read(struct pdm_device *pdm, void *buf, uint32 len);
+
+/**
+ * @brief pdm_close
+ *
+ * @Compatible version: V0
+ *
+ * @note Turn PDM module off.
+ *
+ * @param pdm       The address of pdm device in the RTOS.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 pdm_close(struct pdm_device *pdm);
+
+/**
+ * @brief pdm_request_irq.
+ *
+ * @Compatible version: V0
+ *
+ * @param pdm       The address of PDM device in the RTOS.
+ * @param irq_flag  The type of interrupt - see"enum pdm_irq_flag".
+ * @param irqhdl    The interrupt function.
+ * @param irq_data  The parameters of the interrupt function
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 pdm_request_irq(struct pdm_device *pdm, enum pdm_irq_flag flag, pdm_irq_hdl irq_hdl, uint32 data);
+
+/**
+ * @brief pdm_release_irq.
+ *
+ * @Compatible version: V0
+ *
+ * @param pdm       The address of PDM device in the RTOS.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 pdm_release_irq(struct pdm_device *pdm, enum pdm_irq_flag irq_flag);
+
+/**
+ * @brief pdm_ioctl.
+ *
+ * @Compatible version: V0
+ *
+ * @param pdm       The address of PDM device in the RTOS.
+ * @param cmd       Control command - see"enum pdm_ioctl_cmd".
+ * @param param     Parameters required to execute the current Control command.
+ *
+ * @return
+ *     - RET_OK              Success
+ *     - RET_ERR             Fail
+ */
+int32 pdm_ioctl(struct pdm_device *pdm, enum pdm_ioctl_cmd cmd, uint32 param);
+
+#ifdef __cplusplus
+}
+#endif
+#endif