easylinux/OpenTXW81X
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

pure sdk for main

Browse Source
This commit is contained in:
divadiow
2025-08-27 09:51:58 +01:00
parent f0d033f1c9
commit 0571416e7c
3283 changed files with 1577720 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sdk/chip/txw81x/TXW81X_FLASH_ALGORITHM.elf
BIN
View File
Binary file not shown.
sdk/chip/txw81x/TXW81X_FLASH_ALGORITHM.init
+10
View File
@@ -0,0 +1,10 @@
# watchdog close : WDT->WDTKEY
set *(unsigned int *)0x40015004=0xdddd
set $psr=0x80000000
# sysctrl writable : SYSCTRL->SYS_KEY
set *(unsigned int *)0x40020000=0x3fac87e4
#reset peripherals
set *(unsigned int *)0x40020004=0x00000200
set *(unsigned int *)0x40020008=0x00000000
set *(unsigned int *)0x40020008=0x80000000
sdk/chip/txw81x/isr.c
+314
View File
@@ -0,0 +1,314 @@
/******************************************************************************
* @file isr.c
* @brief source file for the interrupt server route
* @version V1.0
* @date 02. June 2017
******************************************************************************/
#include "sys_config.h"
//#include <drv_common.h>
#include <csi_config.h>
#include "soc.h"
#ifndef CONFIG_KERNEL_NONE
#include <csi_kernel.h>
#endif
#include "typesdef.h"
#include "errno.h"
#include "osal/irq.h"
#include "osal/string.h"
extern void ck_usart_irqhandler(int32_t idx);
extern void dw_timer_irqhandler(int32_t idx);
extern void dw_gpio_irqhandler(int32_t idx);
extern void systick_handler(void);
extern void xPortSysTickHandler(void);
extern void OSTimeTick(void);
static struct sys_hwirq sys_irqs[IRQ_NUM];
#if defined(CONFIG_SUPPORT_TSPEND) || defined(CONFIG_KERNEL_NONE)
#define ATTRIBUTE_ISR __attribute__((isr))
#else
#define ATTRIBUTE_ISR
#endif
#define readl(addr) ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
#if defined(CONFIG_KERNEL_RHINO)
#define SYSTICK_HANDLER systick_handler
#elif defined(CONFIG_KERNEL_FREERTOS)
#define SYSTICK_HANDLER xPortSysTickHandler
#elif defined(CONFIG_KERNEL_UCOS)
#define SYSTICK_HANDLER OSTimeTick
#endif
#if !defined(CONFIG_KERNEL_FREERTOS) && !defined(CONFIG_KERNEL_NONE)
#define CSI_INTRPT_ENTER() csi_kernel_intrpt_enter()
#define CSI_INTRPT_EXIT() csi_kernel_intrpt_exit()
#else
#define CSI_INTRPT_ENTER()
#define CSI_INTRPT_EXIT()
#endif
#ifdef SYS_IRQ_STAT
#define SYS_IRQ_STATE_ST(irqn) uint32 _t1_, _t2_; _t1_ = csi_coret_get_value();
#define SYS_IRQ_STATE_END(irqn) do{ \
_t2_ = csi_coret_get_value();\
_t1_ = ((_t1_>_t2_)?(_t1_-_t2_):(csi_coret_get_load()-_t2_+_t1_));\
sys_irqs[irqn].tot_cycle += _t1_;\
sys_irqs[irqn].trig_cnt++;\
if (_t1_ > sys_irqs[irqn].max_cycle) {\
sys_irqs[irqn].max_cycle = _t1_;\
}\
}while(0)
#else
#define SYS_IRQ_STATE_ST(irqn)
#define SYS_IRQ_STATE_END(irqn)
#endif
#define SYSTEM_IRQ_HANDLE_FUNC(func_name,irqn)\
ATTRIBUTE_ISR void func_name(void)\
{\
SYS_IRQ_STATE_ST(irqn);\
CSI_INTRPT_ENTER();\
if (sys_irqs[irqn].handle) {\
sys_irqs[irqn].handle(sys_irqs[irqn].data);\
}\
CSI_INTRPT_EXIT();\
SYS_IRQ_STATE_END(irqn);\
}
int32 request_irq(uint32 irq_num, irq_handle handle, void *data)
{
if (irq_num < IRQ_NUM) {
sys_irqs[irq_num].data = data;
sys_irqs[irq_num].handle = handle;
return RET_OK;
} else {
return -EINVAL;
}
}
int32 release_irq(uint32 irq_num)
{
if (irq_num < IRQ_NUM) {
irq_disable(irq_num);
sys_irqs[irq_num].handle = NULL;
sys_irqs[irq_num].data = NULL;
return RET_OK;
} else {
return -EINVAL;
}
}
uint32 irq_status(void)
{
uint32 tot_time = 0;
#ifdef SYS_IRQ_STAT
int i;
uint32_t v1, v2, v3;
os_printf("SYS IRQ:\r\n");
for (i = 0; i < IRQ_NUM; i++) {
if (sys_irqs[i].trig_cnt) {
v1 = sys_irqs[i].trig_cnt;
v2 = sys_irqs[i].tot_cycle/(sys_get_sysclk()/1000000);//us
v3 = sys_irqs[i].max_cycle/(sys_get_sysclk()/1000000);//us
tot_time += v2; //us
sys_irqs[i].trig_cnt = 0;
sys_irqs[i].tot_cycle = 0;
sys_irqs[i].max_cycle = 0;
os_printf(" IRQ%-2d: trig:%-8d tot_time:%-8dus max:%-8dus\r\n", i, v1, v2, v3);
}
}
#endif
return tot_time;
}
ATTRIBUTE_ISR void CORET_IRQHandler(void)
{
SYS_IRQ_STATE_ST(CORET_IRQn);
CSI_INTRPT_ENTER();
readl(0xE000E010);
SYSTICK_HANDLER();
CSI_INTRPT_EXIT();
SYS_IRQ_STATE_END(CORET_IRQn);
}
#define AES_INTERUPT_ON_OFF ((*(unsigned int *)0x40012040) & BIT(3))
#define AES_INETRUPT_PENDING ((*(unsigned int *)0x40012044))
#define SHA_INTERUPT_ON_OFF (((*(unsigned int *)0x40014008) & BIT(0)))
#define SHA_INTERUPT_PENDING ((*(unsigned int *)0x4001400C))
ATTRIBUTE_ISR void SYSAES_IRQHandler(void)
{
SYS_IRQ_STATE_ST(SHA_VIRTUAL_IRQn);
CSI_INTRPT_ENTER();
if (sys_irqs[SPACC_PKA_IRQn].handle && AES_INTERUPT_ON_OFF && AES_INETRUPT_PENDING ) {
sys_irqs[SPACC_PKA_IRQn].handle(sys_irqs[SPACC_PKA_IRQn].data);
}
if (sys_irqs[SHA_VIRTUAL_IRQn].handle && SHA_INTERUPT_ON_OFF && SHA_INTERUPT_PENDING ) {
sys_irqs[SHA_VIRTUAL_IRQn].handle(sys_irqs[SHA_VIRTUAL_IRQn].data);
}
CSI_INTRPT_EXIT();
SYS_IRQ_STATE_END(SHA_VIRTUAL_IRQn);
}
#define UART4_IE_ENABLE ((*(unsigned int *)0x40004b70) & 0x80000383)
#define UART5_IE_ENABLE ((*(unsigned int *)0x40004b90) & 0x80000383)
ATTRIBUTE_ISR void UART45_IRQHandler(void)
{
CSI_INTRPT_ENTER();
if (sys_irqs[UART4_IRQn].handle && UART4_IE_ENABLE ) {
sys_irqs[UART4_IRQn].handle(sys_irqs[UART4_IRQn].data);
}
if (sys_irqs[UART5_IRQn].handle && UART5_IE_ENABLE ) {
sys_irqs[UART5_IRQn].handle(sys_irqs[UART5_IRQn].data);
}
CSI_INTRPT_EXIT();
}
#define GPIOA_IE_ENABLE ((*(unsigned int *)0x40020A3C) & 0x0000FFFF)
#define GPIOB_IE_ENABLE ((*(unsigned int *)0x40020B3C) & 0x0000FFFF)
#define GPIOC_IE_ENABLE ((*(unsigned int *)0x40020C3C) & 0x0000FFFF)
#define GPIOE_IE_ENABLE ((*(unsigned int *)0x40020E3C) & 0x0000FFFF)
ATTRIBUTE_ISR void GPIO_IRQHandler(void)
{
CSI_INTRPT_ENTER();
if (sys_irqs[GPIOA_IRQn].handle && GPIOA_IE_ENABLE ) {
sys_irqs[GPIOA_IRQn].handle(sys_irqs[GPIOA_IRQn].data);
}
if (sys_irqs[GPIOB_IRQn].handle && GPIOB_IE_ENABLE ) {
sys_irqs[GPIOB_IRQn].handle(sys_irqs[GPIOB_IRQn].data);
}
if (sys_irqs[GPIOC_IRQn].handle && GPIOC_IE_ENABLE ) {
sys_irqs[GPIOC_IRQn].handle(sys_irqs[GPIOC_IRQn].data);
}
if (sys_irqs[GPIOE_IRQn].handle && GPIOE_IE_ENABLE ) {
sys_irqs[GPIOE_IRQn].handle(sys_irqs[GPIOE_IRQn].data);
}
CSI_INTRPT_EXIT();
}
#define AUDIO_VAD_IRQ_ENABLE ((*(unsigned int *)0x40008028) & 0x00001FC0)
#define AUDIO_HS_IRQ_ENABLE ((*(unsigned int *)0x40008028) & 0x00018000)
#define AUDIO_ALAW_IRQ_ENABLE ((*(unsigned int *)0x40008028) & 0x00006000)
ATTRIBUTE_ISR void AUDIO_VAD_HS_ALAW_IRQHandler(void)
{
CSI_INTRPT_ENTER();
if (sys_irqs[AUVAD_IRQn].handle && AUDIO_VAD_IRQ_ENABLE ) {
sys_irqs[AUVAD_IRQn].handle(sys_irqs[AUVAD_IRQn].data);
}
if (sys_irqs[AUHS_IRQn].handle && AUDIO_HS_IRQ_ENABLE ) {
sys_irqs[AUHS_IRQn].handle(sys_irqs[AUHS_IRQn].data);
}
if (sys_irqs[AUALAW_IRQn].handle && AUDIO_ALAW_IRQ_ENABLE ) {
sys_irqs[AUALAW_IRQn].handle(sys_irqs[AUALAW_IRQn].data);
}
CSI_INTRPT_EXIT();
}
//0
SYSTEM_IRQ_HANDLE_FUNC(USB20DMA_IRQHandler, USB20DMA_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(USB20MC_IRQHandler, USB20MC_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(UART0_IRQHandler, UART0_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(UART1_IRQHandler, UART1_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(LCD_IRQHandler, LCD_IRQn)
//5
SYSTEM_IRQ_HANDLE_FUNC(QSPI_IRQHandler, QSPI_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SPI0_IRQHandler, SPI0_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SPI1_IRQHandler, SPI1_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SPI2_IRQHandler, SPI2_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(OSPI_IRQHandler, OSPI_IRQn)
//10
SYSTEM_IRQ_HANDLE_FUNC(TIM0_IRQHandler, TIM0_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(TIM1_IRQHandler, TIM1_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(TIM2_IRQHandler, TIM2_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(TIM3_IRQHandler, TIM3_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SCALE1_IRQHandler, SCALE1_IRQn)
//15
//SYSTEM_IRQ_HANDLE_FUNC(AUDIO_VAD_HS_ALAW_IRQHandler, AUDIO_SUBSYS0_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(AUDIO_ADC_IRQHandler, AUDIO_SUBSYS1_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(AUDIO_DAC_IRQHandler, AUDIO_SUBSYS2_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SDIO_IRQHandler, SDIO_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SDIO_RST_IRQHandler, SDIO_RST_IRQn)
//20
SYSTEM_IRQ_HANDLE_FUNC(SDHOST_IRQHandler, SDHOST_IRQn)
__ram SYSTEM_IRQ_HANDLE_FUNC(LMAC_IRQHandler, LMAC_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(GMAC_IRQHandler, GMAC_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(M2M0_IRQHandler, M2M0_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(M2M1_IRQHandler, M2M1_IRQn)
//25
//SYSTEM_IRQ_HANDLE_FUNC(CORET_IRQHandler, CORET_IRQn)
//SYSTEM_IRQ_HANDLE_FUNC(SYSAES_IRQHandler, SPACC_PKA_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(CRC_IRQHandler, CRC_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(ADKEY_IRQHandler, ADKEY01_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(PD_TMR_IRQHandler, PD_TMR_IRQn)
//30
SYSTEM_IRQ_HANDLE_FUNC(WKPND_IRQHandler, WKPND_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(PDWKPND_IRQHandler, PDWKPND_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(LVD_IRQHandler, LVD_IRQn)
//SYSTEM_IRQ_HANDLE_FUNC(WDT_IRQHandler, WDT_IRQn)
ATTRIBUTE_ISR void WDT_IRQHandler()
{
//喂狗并清除中断pending
*(volatile unsigned int *)(0x40015000 + 0x4) = 0xAAAA;
if (sys_irqs[WDT_IRQn].handle ) {
sys_irqs[WDT_IRQn].handle(sys_irqs[WDT_IRQn].data);
}
}
SYSTEM_IRQ_HANDLE_FUNC(SYS_ERR_IRQHandler, SYS_ERR_IRQn)
//35
SYSTEM_IRQ_HANDLE_FUNC(IIS0_IRQHandler, IIS0_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(IIS1_IRQHandler, IIS1_IRQn)
//SYSTEM_IRQ_HANDLE_FUNC(GPIO_IRQHandler, GPIOABCE_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(DVP_IRQHandler, DVP_IRQn)
//RES: default_handler
//40
SYSTEM_IRQ_HANDLE_FUNC(JPG_IRQHandler, MJPEG01_IRQn)
//RES: default_handler
SYSTEM_IRQ_HANDLE_FUNC(VPP_IRQHandler, VPP_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(PRC_IRQHandler, PRC_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(STMR_IRQHandler, STMR012345_IRQn)
//45
SYSTEM_IRQ_HANDLE_FUNC(PDM_IRQHandler, PDM_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(LED_TMR_IRQHandler, LED_TMR_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SCALE2_IRQHandler, SCALE2_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(GFSK_IRQHandler, GFSK_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(CMP_IRQHandler, CMPOUT01_IRQn)
//50
//SYSTEM_IRQ_HANDLE_FUNC(UART45_IRQHandler, UART45_IRQn)
SYSTEM_IRQ_HANDLE_FUNC(SCALE3_IRQHandler, SCALE3_IRQn)
//RES: default_handler
//RES: default_handler
//RES: default_handler
//50
//RES: default_handler
//RES: default_handler
//RES: default_handler
SYSTEM_IRQ_HANDLE_FUNC(USB20PHY_RTC_IRQHandler, USB20PHY_RTC_IRQn)
sdk/chip/txw81x/loader_compress.bin
BIN
View File
Binary file not shown.
sdk/chip/txw81x/pin_function.c
+1192
View File
File diff suppressed because it is too large Load Diff
sdk/chip/txw81x/system.c
+304
View File
@@ -0,0 +1,304 @@
#include "sys_config.h"
#include "typesdef.h"
#ifdef CSKY_OS
#include "csi_config.h"
#include "soc.h"
#include "csi_core.h"
#include "csi_kernel.h"
#endif
#ifdef OHOS
#include "los_task.h"
#endif
#include "txw81x/ticker.h"
#include "osal/irq.h"
#include "osal/string.h"
#include "osal/semaphore.h"
#include "osal/task.h"
#include "osal/work.h"
#include "devid.h"
#include "lib/heap/sysheap.h"
#include "lib/lmac/lmac.h"
#include "lib/common/sysevt.h"
#include "lib/common/common.h"
#include "dev/xspi/hg_xspi_psram.h"
#include "psram_cfg.h"
#ifdef CONFIG_SLEEP
#include "lib/common/dsleepdata.h"
#endif
extern int main(void);
extern int dev_init(void);
extern void device_init(void);
extern void set_psram_status(uint8_t res);
extern uint8_t get_psram_status();
extern int32_t g_top_irqstack;
extern uint32_t __heap_start;
extern uint32_t __heap_end;
extern uint32_t __psram_heap_start;
extern uint32_t __psram_heap_end;
extern struct os_workqueue main_wkq;
extern uint32 *sysvar_mgr;
extern uint8_t assert_holdup;
const uint32 g_DEFAULT_SYS_CLK = DEFAULT_SYS_CLK;
const uint32 g_SYS_CACHE_ENABLE = SYS_CACHE_ENABLE;
uint32 srampool_start = 0;
uint32 srampool_end = 0;
uint32 psrampool_start = 0;
uint32 psrampool_end = 0;
uint32 __sp_save[3];
#ifndef SYS_FACTORY_PARAM_SIZE
#define SYS_FACTORY_PARAM_SIZE 4
#endif
const uint16_t __used sys_factory_param[SYS_FACTORY_PARAM_SIZE / 2] __at_section("SYS_PARAM") = {SYS_FACTORY_PARAM_SIZE};
//为了不同工程,所以这里写一个空函数,即使没有save_boot_loader_addr也不会编译出错
__init __weak void save_boot_loader_addr() {};
__SYS_INIT void cache_open(void)
{
sysctrl_cache_en();
csi_cache_reset_profile();
csi_cache_set_range(0, (uint32_t) & (__Vectors), CACHE_CRCR_8M, 0x1);
#if defined(PSRAM_HEAP)
csi_cache_set_range(1, PSRAM_BASE, CACHE_CRCR_16M, 0x1);
#endif
csi_cache_enable_profile();
csi_dcache_enable();
}
__SYS_INIT __weak void system_clock_init(void)
{
if (!sysctrl_cmu_sysclk_set(DEFAULT_SYS_CLK, 1)) {
while (1);
}
}
void irq_enable(uint32 irq)
{
NVIC_EnableIRQ(irq);
}
void irq_disable(uint32 irq)
{
NVIC_DisableIRQ(irq);
}
uint32 disable_irq(void)
{
return __disable_irq();
}
void enable_irq(uint32 flag)
{
if(!flag) __enable_irq();
}
int32 hg_qspi_flash_xip_mode(void *hw1, uint32 xip_en) {
return RET_OK;
}
/**
* @retval : wp_en_last
*/
int32 hg_qspi_flash_protect(void *hw1, uint32 wp_en) {
int32 wp_en_last = 0;
return wp_en_last;
}
/** @param
* pack = 0x0C : P25Q16SH, DC = CR1[2]
* 0x1C : GD25Q16E, DC = SR2[4]
* 0xFF : auto detect for TWX817-824
* @retval
* RET_ERR or last hs status
*/
int32 hg_qspi_flash_hs_enable(void *hw1, uint32 pack) {
int32 hs_en_last = 0;
return hs_en_last;
}
__SYS_INIT void SystemInit(void)
{
srampool_start = (uint32)&__heap_start;
srampool_end = (uint32)&__heap_end;
psrampool_start = (uint32)&__psram_heap_start;
psrampool_end = (uint32)&__psram_heap_end;
extern uint32 g_intstackbase;
*((int *)((uint32)&g_intstackbase)) = 0xDEADBEEF;
__set_VBR((uint32_t) & (__Vectors));
SYSCTRL_REG_OPT_INIT();
#if SYS_CACHE_ENABLE
cache_open();
#endif
sys_reset_detect();
sys_reset_pending_clr();
sysctrl_efuse_pwron_init();
// if (sysctrl_get_softreset_pending()) {
// sysctrl_clr_softreset_pending();
// pmu_set_direct_run_pengding2();
// } else {
// pmu_clr_direct_run_pengding2();
// }
pmu_boot_direct_run_dis();
SET_SKIP_PSRAM_SIGN(0);
pmu_clr_deadcode_pending();
mcu_watchdog_feed();
mcu_watchdog_timeout_level(4);
// sysctrl_err_resp_disable();
sysctrl_cmu_init();
#ifndef FPGA_SUPPORT
system_clock_init();
#endif
void hg_xspi_sample_offset(uint32 ospi_base, int8 rx_offset, int8 tx_offset);
hg_xspi_sample_offset((uint32)HG_OSPI_BASE, -2, 0);
pmu_vdd_core_set(3);
#if defined(CONFIG_SEPARATE_IRQ_SP) && !defined(CONFIG_KERNEL_NONE)
/* 801 not supported */
__set_Int_SP((uint32_t)&g_top_irqstack);
__set_CHR(__get_CHR() | CHR_ISE_Msk);
VIC->TSPR = 0xFF;
#endif
/* Clear active and pending IRQ */
csi_vic_disable_all_irq();
csi_vic_clear_all_pending_irq();
csi_vic_clear_all_active();
/* All peripheral interrupt priority is set to lowest */
for (uint32 i = 0; i < IRQ_NUM; i++) {
csi_vic_set_prio(i, 7);
}
#ifdef CONFIG_KERNEL_NONE
__enable_excp_irq();
#endif
csi_coret_config(system_clock_get() / OS_SYSTICK_HZ, CORET_IRQn); //1ms
#ifndef CONFIG_KERNEL_NONE
csi_vic_enable_irq(CORET_IRQn);
#endif
request_irq(LVD_IRQn, lvd_irq_handler, 0);
irq_enable(LVD_IRQn);
#ifndef CONFIG_SLEEP
sysctrl_gpio_funcmap_default();
#else
int32 is_dsleep_wakeup(void);
if(!is_dsleep_wakeup()) sysctrl_gpio_funcmap_default();
#endif
pmu_set_deadcode_pending();
mcu_watchdog_feed();
mcu_watchdog_timeout_level(8);
}
#if MPOOL_ALLOC
__init void malloc_init(void)
{
uint32 flags = 0;
#ifdef MEM_TRACE
flags |= SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
#endif
sram_heap.name = "sram";
sysheap_init(&sram_heap, (void *)SYS_HEAP_START, SYS_HEAP_SIZE, flags);
}
__init void malloc_psram_init(void)
{
#ifdef PSRAM_HEAP
uint32 flags = SYSHEAP_FLAGS_MEM_ALIGN_16;
#ifdef MEM_TRACE
flags |= SYSHEAP_FLAGS_MEM_LEAK_TRACE | SYSHEAP_FLAGS_MEM_OVERFLOW_CHECK;
#endif
psram_heap.name = "psram";
sysheap_init(&psram_heap, (void *)psrampool_start, psrampool_end - psrampool_start, flags);
#endif
}
void ota_msg_show()
{
os_printf("[OTA_MSG] OTA_NUM:%d\tota_version:%d\trun_addr:%X\n",pmu_get_boot_code_pos(),get_boot_svn_version(),get_boot_loader_addr());
}
#endif
__init void pre_main(void)
{
sdk_version = SDK_VERSION;
svn_version = SVN_VERSION;
app_version = APP_VERSION;
assert_holdup = ASSERT_HOLDUP;
save_boot_loader_addr();
uint8_t res;
if(NOW_PSRAM > PSRAM_DEF(E_PSRAM)) {
//printf("now_psram:%d\t%d\n",NOW_PSRAM,PSRAM_DEF(E_PSRAM));
res = psram_init(APS1604M_3SQR, (60*1000000),512);
//外部psram初始化,所以需要配置对应的状态
set_psram_status(res);
} else {
//is not ready?
if(!get_psram_status()) {
res = psram_auto_init();
set_psram_status(res);
}
}
#if MPOOL_ALLOC
malloc_init();
malloc_psram_init();
#endif
#ifdef CSKY_OS
csi_kernel_init();
#endif
#ifdef OHOS
LOS_KernelInit();
#endif
dev_init();
device_init();
#ifdef CONFIG_SLEEP
sys_sleepcb_init();
#endif
#ifdef CONFIG_SLEEP
sys_sleepdata_init();
#endif
sysctrl_rst_lmac_phy();
sysctrl_efuse_validity_handle();
ota_msg_show();
VERSION_SHOW();
module_version_show();
sys_reset_show();
os_workqueue_init(&main_wkq, "MAIN", OS_TASK_PRIORITY_NORMAL, 2048);
mainwkq_monitor_init();
os_run_func((os_run_func_t)main, 0, 0, 0);
#ifdef CSKY_OS
csi_kernel_start();
#endif
#ifdef OHOS
LOS_Start();
#endif
}
sdk/chip/txw81x/ticker_api.c
+95
View File
@@ -0,0 +1,95 @@
#include "sys_config.h"
#include "tx_platform.h"
#ifdef TXW80X
#include "txw80x/ticker.h"
#endif
#ifdef TXW81X
#include "txw81x/ticker.h"
#endif
#include "osal/irq.h"
#include "list.h"
#include "dev.h"
#if 0
#define SIMPLE_TIMER0(offset) (*((uint32 *)(0x40015B00 + offset)))
/**
* @brief The tick timer is initialized.
* @param None
* @retval None
* @note Use the lowest priority interrupt.
*/
void hw_timer_init(void)
{
//STMR0_CTL
SIMPLE_TIMER0(0x00) = (4 << 8) | (7 << 0);
//STMR0_CNT
SIMPLE_TIMER0(0x04) = 0;
//STMR0_PR
SIMPLE_TIMER0(0x04) = 0xFFFFFFFF;
}
/**
* @brief get the tick of the timer.
* @param None
* @retval None
*/
uint32 hw_timer_get_tick(uint8 start)
{
uint32 cnt = 0;
uint32_t v = sys_get_sysclk()/1000000;
if(start){
__disable_irq();
//STMR0_CNT
SIMPLE_TIMER0(0x04) = 0;
//TMR_EN
SIMPLE_TIMER0(0x00) |= (1 << 4);
//*(uint32_t *)(HG_GPIOC_BASE+36) |= BIT(7);
__enable_irq();
return 0;
}else{
__disable_irq();
//*(uint32_t *)(HG_GPIOC_BASE+36) &= ~ BIT(7);
//TMR_CNT
cnt = SIMPLE_TIMER0(0x04);
//TMR_EN
SIMPLE_TIMER0(0x00) &= ~(1 << 4);
__enable_irq();
return (16*cnt)/v;
}
}
#endif
/**
* @brief Use the CPU precision delay function
* @param n :
* @retval None
* @note for CK803 : period_count = 3*n+1
*/
__attribute__((noinline, naked)) void __delay_asm(uint32 n)
{
__asm__(" \
delay_asm_L1: \
DECGT32 R0, R0, 1 \n\
BT32 delay_asm_L1 \n\
rts \n\
");
}
/**
* @brief Use the CPU to delay approximately us
* @param n : the number of us to delay
* @retval None
* @note only work for SYS_CLK
*/
void delay_us(uint32 n)
{
uint32 temp = sys_get_sysclk()/1000000*n;
if(temp > 47) {
__delay_asm((temp - 47)/3);
}
}
sdk/chip/txw81x/trap_c.c
+60
View File
@@ -0,0 +1,60 @@
/*
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/******************************************************************************
* @file trap_c.c
* @brief source file for the trap process
* @version V1.0
* @date 12. December 2017
******************************************************************************/
#include "typesdef.h"
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <csi_config.h>
#include <csi_core.h>
#include <csi_kernel.h>
#include "osal/string.h"
#include "osal/task.h"
#include <k_api.h>
extern void csi_kernel_task_dump(k_task_handle_t task_handle, void* stack);
void hgprintf(const char *fmt, ...);
#define trap_err(fmt,...) hgprintf(KERN_EMERG fmt, ##__VA_ARGS__)
void trap_c(uint32_t *regs)
{
int i;
// uint32_t *stack_top;
uint32_t vec = (__get_PSR() & PSR_VEC_Msk) >> PSR_VEC_Pos;
disable_print(0);
trap_err("---------------------------------------------------------------\r\n");
trap_err("CPU Exception: NO.%u\r\n", vec);
for (i = 0; i < 16; i++) {
trap_err("r%d: %08x\t", i, regs[i]);
if ((i % 4) == 3) {
trap_err("\r\n");
}
}
trap_err("r28 : %08x\r\n", regs[16]);
trap_err("epsr: %08x\r\n", regs[17]);
trap_err("epc : %08x\r\n", regs[18]);
csi_kernel_task_dump((k_task_handle_t)g_active_task[0], (void* )regs[14]);
mcu_reset();
}
sdk/chip/txw81x/vectors.S
+139
View File
@@ -0,0 +1,139 @@
/*
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/******************************************************************************
* @file vectors.S
* @brief define default vector handlers. Should use with
* GCC for CSKY Embedded Processors
* @version V1.0
* @date 28. Nove 2017
******************************************************************************/
#include <csi_config.h>
.import trap_c
.section .trap_stack
.align 2
.globl g_trapstackalloc
.global g_trapstackbase
.global g_top_trapstack
g_trapstackalloc:
g_trapstackbase:
.space 512
g_top_trapstack:
.text
/******************************************************************************
* Functions:
* uint32_t __get_PC(uint32_t);
* default exception handler
******************************************************************************/
.global __get_PC
.type __get_PC, %function
__get_PC:
grs r0, __get_PC
jmp r15
/******************************************************************************
* Functions:
* void trap(void);
* default exception handler
******************************************************************************/
.global trap
.type trap, %function
trap:
psrset ee
subi sp, 4
stw r0, (sp)
lrw r0, g_top_trapstack
subi r0, 76
stm r0-r15, (r0)
stw r28, (r0, 64)
ldw r1, (sp)
addi sp, 4
stw sp, (r0, 56) /* save r14 */
mov sp, r0
stw r1, (sp) /* save r0 */
mfcr r1, epsr
stw r1, (sp, 68)
mfcr r1, epc
stw r1, (sp, 72)
jbsr trap_c
.align 2
.weak Default_Handler
.type Default_Handler, %function
Default_Handler:
br trap
.size Default_Handler, . - Default_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.weak \handler_name
.globl \handler_name
.set \handler_name, Default_Handler
.endm
def_irq_handler trap0_handler
def_irq_handler tspend_handler
def_irq_handler USB20DMA_USB11SOF_IRQHandler
def_irq_handler USB20MC_USB11CTL_IRQHandler
def_irq_handler UART0_IRQHandler
def_irq_handler UART1_IRQHandler
def_irq_handler UART2_IRQHandler
def_irq_handler QSPI_IRQHandler
def_irq_handler SPI0_IRQHandler
def_irq_handler SPI1_IRQHandler
def_irq_handler SPI2_IRQHandler
def_irq_handler SPI3_IRQHandler
def_irq_handler TIM0_IRQHandler
def_irq_handler TIM1_IRQHandler
def_irq_handler TIM2_IRQHandler
def_irq_handler TIM3_IRQHandler
def_irq_handler TIM4_IRQHandler
def_irq_handler TIM5_IRQHandler
def_irq_handler TIM6_IRQHandler
def_irq_handler TIM7_IRQHandler
def_irq_handler SDIO_IRQHandler
def_irq_handler SDIO_RST_IRQHandler
def_irq_handler SDHOST_IRQHandler
def_irq_handler LMAC_IRQHandler
def_irq_handler GMAC_IRQHandler
def_irq_handler M2M0_IRQHandler
def_irq_handler M2M1_IRQHandler
def_irq_handler CORET_IRQHandler
def_irq_handler SYSAES_IRQHandler
def_irq_handler CRC_IRQHandler
def_irq_handler ADKEY_IRQHandler
def_irq_handler PD_TMR_IRQHandler
def_irq_handler WKPND_IRQHandler
def_irq_handler PDWKPND_IRQHandler
def_irq_handler LVD_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler SYS_ERR_IRQHandler
def_irq_handler IIS0_IRQHandler
def_irq_handler IIS1_IRQHandler
def_irq_handler GPIOA_IRQHandler
def_irq_handler GPIOB_IRQHandler
def_irq_handler DVP_IRQHandler
def_irq_handler JPG_IRQHandler