easylinux/OpenTXW81X
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pure sdk for main

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This commit is contained in:
divadiow
2025-08-27 09:51:58 +01:00
parent f0d033f1c9
commit 0571416e7c
3283 changed files with 1577720 additions and 1 deletions
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project/BinScript.BinScript
+16
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memset(ibuf, ff);
read(hex, project.hex);
remap(v_ax, 0, v_lx);
memmode(obuf, 32, lit);
write(bin, txw81x_fpv.bin);
reset(ibuf);
reset(obuf);
read(bin, txw81x_fpv.bin);
def16_at(v_param_len, 180);
read(bin, parameter.cfg);
memmode(ibuf, 32, lit);
remap(210, 0, v_param_len);
setbuf16(0, v_param_len);
outrange(0, v_param_len, 10);
write(bin, param.bin);
project/BinScript.exe
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project/BuildBIN.sh
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#!/bin/bash
if [ -e tmp ]; then
files=$(ls tmp)
for f in $files
do
ff=$(cat tmp/$f)
mv -f $ff.bak $ff
done
rm -rf tmp
fi
cp ./Obj/*.elf project.elf
cp ./Lst/*.map project.map
cp ./Obj/*.ihex project.hex
if [ -e parameter.bincfg ]; then
cp -f ./parameter.bincfg parameter.cfg
fi
if [ -e parameter_ui.setcfg ]; then
cp -f ./parameter_ui.setcfg parameter_ui.cfg
fi
[ -e ../sdk/chip/txw81x/loader_compress.bin ] && cp -f ../sdk/chip/txw81x/loader_compress.bin loader_compress.bin
cp parameter.bincfg parameter.cfg
BinScript.exe BinScript.BinScript
makecode.exe
#crc.exe crc.ini
#BinScript.exe BinScript_Bin2Hex.BinScript
project/CSKYFlashProgramerCfg
+49
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{
"DebugServerSetting": {
"UseDDC": true,
"EnableTRST": false,
"EnableDbgSvrLog": false,
"ICECLk": 12000,
"DelayMTCR": 10
},
"FlashProgramSession": {
"CommandType": 0,
"TargetConfig": {
"AlgorithmFile": "../sdk/chip/txw81x/TXW81X_FLASH_ALGORITHM.elf",
"PreScriptFile": "../sdk/chip/txw81x/TXW81X_FLASH_ALGORITHM.init",
"EraseType": 1,
"EraseRangStart": 0,
"EraseRangLength": 4096,
"ConnectType": 0,
"Timeout": 20,
"LogEnable": false,
"ResetAndRun": true,
"ResetType": 0,
"ResetValue": 2882338816,
"RunMode": false,
"CPUSelect": 0
},
"TargetFile": {
"DumpFileType": 1,
"DumpBinFileInfo": {
"FilePath": "C:/dump.bin",
"StartAddress": 0,
"Length": 1048576
},
"DumpHexFileInfo": {
"FilePath": "",
"StartAddress": 0,
"Length": 4096
}
},
"TargetObjectArray": [
{
"Type": 2,
"Verify": true,
"TargetAddr": 0,
"FilePath": "APP.bin",
"Program": true
}
]
}
}
project/CSKYFlashProgramerConsole.bat
+16
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cd /d %~dp0
ECHO OFF
set CDKPath=%1
set CFGPath=%2
"%CDKPath%\CSKY\FlashProgrammer\Bins\CSKYFlashProgramerConsole.exe" -f %CFGPath%
IF %ERRORLEVEL% NEQ 0 (
goto err_exit
)
exit /b 0
:err_exit
exit /b 2
project/atcmd.c
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#include "test_demo/test_demo.h"
#include "sys_config.h"
int32 sys_atcmd_sysdbg(const char *cmd, char *argv[], uint32 argc)
{
extern struct system_status sys_status;
char *arg = argv[0];
if (argc == 2) {
if (os_strcasecmp(arg, "heap") == 0) {
sys_status.dbg_heap = (os_atoi(argv[1]) == 1);
}
if (os_strcasecmp(arg, "top") == 0) {
sys_status.dbg_top = os_atoi(argv[1]);
}
if (os_strcasecmp(arg, "lmac") == 0) {
sys_status.dbg_lmac = (os_atoi(argv[1]) == 1);
}
if (os_strcasecmp(arg, "irq") == 0) {
sys_status.dbg_irq = (os_atoi(argv[1]) == 1);
}
return ATCMD_RESULT_OK;
} else {
return ATCMD_RESULT_ERR;
}
}
static const struct hgic_atcmd static_atcmds[] = {
{ "AT+RST", sys_atcmd_reset },
{ "AT+GOTOBOOT", sys_atcmd_goto_boot },
{ "AT+SYSDBG", sys_atcmd_sysdbg },
{ "AT+LOADDEF", sys_atcmd_loaddef },
{ "AT+REBOOT_TEST", sys_wifi_atcmd_reboot_test_mode },
/*TESTMODE ATCMD*/
{ "AT+BSS_BW", atcmd_bss_bw_hdl },
{ "AT+CCA", at_cmd_cca_hdl },
{ "AT+CFG_RX_AGC", at_cmd_cfg_rx_agc_hdl },
{ "AT+CLR_RX_CNT", atcmd_rx_cnt_clr_hdl },
{ "AT+DBG_LEVEL", atcmd_dbg_level_hdl },
{ "AT+EDCA_AIFS", atcmd_edca_aifs_hdl },
{ "AT+EDCA_CW", atcmd_edca_cw_hdl },
{ "AT+EDCA_TXOP", atcmd_edca_txop_hdl },
{ "AT+TX_FRM_TYPE", atcmd_tx_frm_type_hdl },
{ "AT+TX_GAIN", atcmd_tx_gain_hdl },
{ "AT+GET_RX_CNT", atcmd_rx_cnt_get_hdl },
{ "AT+LO_FREQ", atcmd_lo_freq_hdl },
{ "AT+MAC_ADDR", atcmd_mac_addr_hdl },
{ "AT+PRINT_PERIOD", atcmd_lmac_print_period_hdl },
{ "AT+REG_RD", atcmd_reg_rd_hdl },
{ "AT+REG_WT", atcmd_reg_wt_hdl },
{ "AT+SET_XOSC", atcmd_set_xosc_hdl },
{ "AT+SET_TX_DPD_GAIN", atcmd_set_tx_dpd_gain_hdl },
{ "AT+TEST_START", atcmd_test_start_hdl },
{ "AT+TEST_ADDR", atcmd_test_addr_hdl },
{ "AT+TEMP_EN", atcmd_temp_en_hdl },
{ "AT+TX_CONT", atcmd_tx_cont_hdl },
{ "AT+TX_DELAY", atcmd_tx_delay_hdl },
{ "AT+TX_MCS", atcmd_tx_mcs_hdl },
{ "AT+TX_RF_PWR", atcmd_tx_rf_pwr_hdl },
{ "AT+TX_PHA_AMP", atcmd_tx_pha_amp_hdl },
{ "AT+TX_START", atcmd_tx_start_hdl },
{ "AT+TX_STEP", atcmd_tx_step_hdl },
{ "AT+TX_TRIG", atcmd_tx_trig_hdl },
{ "AT+TX_TYPE", atcmd_tx_type_hdl },
{ "AT+WAVE_DUMP", atcmd_wave_dump_hdl },
{ "AT+MAX_TXCNT", atcmd_max_txcnt_hdl },
{ "AT+PCF_EN", atcmd_pcf_en_hdl },
{ "AT+PCF_CHN", atcmd_pcf_chn_hdl },
#ifdef CONFIG_SLEEP
{ "AT+SLEEP_DBG", atcmd_sleep_dbg_hdl },
{ "AT+SLEEP_ALG", atcmd_sleep_alg_hdl },
{ "AT+SLEEP", atcmd_sleep_hdl },
{ "AT+DTIM", atcmd_dtim_hdl },
#endif
{ "AT+CCA_CERT", atcmd_set_cca_cert_hdl },
{ "AT+SRRC", atcmd_set_srrc_hdl},
{ "AT+JTAG", sys_atcmd_jtag },
{ "AT+SYSCFG", sys_syscfg_dump_hdl },
{ "AT+FWUPG", xmodem_fwupgrade_hdl },
{ "AT+SSID", sys_wifi_atcmd_set_ssid},
{ "AT+KEY", sys_wifi_atcmd_set_key },
{ "AT+ENCRYPT", sys_wifi_atcmd_set_encrypt },
{ "AT+WIFIMODE", sys_wifi_atcmd_set_wifimode },
{ "AT+CHANNEL", sys_wifi_atcmd_set_channel },
{ "AT+APHIDE", sys_wifi_atcmd_aphide },
{ "AT+SCAN", sys_wifi_atcmd_scan },
{ "AT+PAIR", sys_wifi_atcmd_pair },
{ "AT+HWMODE", sys_wifi_atcmd_hwmode },
{ "AT+BLENC", sys_ble_atcmd_blenc },
//{ "AT+PING", sys_atcmd_ping},
//{ "AT+ICMPMNTR", sys_atcmd_icmp_mntr},
//{ "AT+IPERF2", sys_atcmd_iperf2},
{"AT+SAVE_AUDIO",demo_atcmd_save_audio},
{"AT+SAVE_PHOTO",demo_atcmd_save_photo},
{"AT+SAVE_AVI",demo_atcmd_save_avi},
{"AT+SAVE_H264",demo_atcmd_save_h264},
{"AT+OTA",demo_atcmd_sd_ota},
{"AT+PLAY_AUDIO",demon_atcmd_play_audio},
//{"AT+RSO",demo_atcmd_select_resolution},
{ "AT+OSD", demo_atcmd_save_osd},
{"AT+PLAY_MP3",demon_atcmd_play_mp3},
#if BLE_METER_TEST_EN
{"AT+BLE_START", atcmd_ble_start_hdl},
{"AT+BLE_TX", atcmd_ble_tx_hdl},
{"AT+BLE_RX", atcmd_ble_rx_hdl},
{"AT+BLE_TX_DELAY", atcmd_ble_tx_delay_hdl},
{"AT+BLE_CLR_RX_CNT", atcmd_ble_rx_cnt_clr_hdl},
{"AT+BLE_GET_RX_CNT", atcmd_ble_rx_cnt_get_hdl},
{"AT+BLE_RX_TIMEOUT", atcmd_ble_rx_timeout_hdl},
{"AT+BLE_CHAN", atcmd_ble_chan_hdl},
{"AT+BLE_TX_GAIN", atcmd_ble_tx_gain_hdl},
{"AT+WRITE_BLE_TX_GAIN", atcmd_write_ble_tx_gain_hdl},
{"AT+IO_TEST", atcmd_io_test_hdl},
{"AT+GET_IO_TEST_RES", atcmd_io_test_res_get_hdl},
#endif
};
__init void sys_atcmd_init(void)
{
struct atcmd_settings setting;
os_memset(&setting, 0, sizeof(setting));
setting.args_count = ATCMD_ARGS_COUNT;
setting.printbuf_size = ATCMD_PRINT_BUF_SIZE;
setting.static_atcmds = static_atcmds;
setting.static_cmdcnt = ARRAY_SIZE(static_atcmds);
atcmd_uart_init(ATCMD_UARTDEV, 115200, 5, &setting);
}
project/client_code/babymonitor/babyprotocol.c
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project/client_code/babymonitor/babyprotocol.h
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project/crc.exe
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project/device.c
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#include "sys_config.h"
#include "typesdef.h"
#include "list.h"
#include "dev.h"
#include "devid.h"
#include "osal/string.h"
#include "osal/semaphore.h"
#include "osal/mutex.h"
#include "osal/timer.h"
#include "osal/task.h"
#include "hal/uart.h"
#include "hal/i2c.h"
#include "hal/timer_device.h"
#include "hal/pwm.h"
#include "hal/capture.h"
#include "hal/dma.h"
#include "hal/netdev.h"
#include "hal/spi.h"
#include "hal/spi_nor.h"
#include "hal/auadc.h"
#include "hal/audac.h"
#include "lib/ota/fw.h"
#include "lib/syscfg/syscfg.h"
#include "lib/net/ethphy/eth_mdio_bus.h"
#include "lib/net/ethphy/eth_phy.h"
#include "lib/net/ethphy/phy/ip101g.h"
#include "dev/uart/hguart_v2.h"
#include "dev/uart/hguart_v4.h"
#include "dev/sdio/hgsdio20_slave.h"
#include "dev/dma/dw_dmac.h"
#include "dev/gpio/hggpio_v4.h"
#include "dev/dma/hg_m2m_dma.h"
#include "dev/usb/hgusb20_v1_dev_api.h"
#include "dev/emac/hg_gmac_eva_v2.h"
#include "dev/crc/hg_crc.h"
#include "dev/timer/hgtimer_v4.h"
#include "dev/timer/hgtimer_v5.h"
#include "dev/timer/hgtimer_v7.h"
#include "dev/pwm/hgpwm_v0.h"
#include "dev/capture/hgcapture_v0.h"
#include "dev/spi/hgspi_v3.h"
#include "dev/spi/hgspi_xip.h"
#include "dev/adc/hgadc_v0.h"
#include "dev/i2c/hgi2c_v1.h"
#include "dev/sysaes/hg_sysaes_v3.h"
#include "dev/sha/hgsha_v0.h"
#include "dev/i2s/hgi2s_v0.h"
#include "dev/pdm/hgpdm_v0.h"
#include "dev/led/hgled_v0.h"
#include "dev/csi/hgdvp.h"
#include "dev/jpg/hgjpg.h"
#include "dev/tk/hg_touchkey_v2.h"
#include "dev/vpp/hgvpp.h"
#include "dev/prc/hgprc.h"
#include "dev/of/hgof.h"
#include "dev/lcdc/hglcdc.h"
#include "dev/scale/hgscale.h"
#include "dev/xspi/hg_xspi.h"
#include "dev/xspi/hg_xspi_psram.h"
#include "dev/audio/hg_audio_v0.h"
#include "lib/sdhost/sdhost.h"
//#include "drv_usart.h"
#include "device.h"
#include "syscfg.h"
extern const struct hgwphy_ah_cfg nphyahcfg;
extern union _dpd_ram dpd_ram;
extern const uint32 rx_imb_iq_normal[6];
extern const union hgdbgpath_cfg ndbgpathcfg;
extern const union hgrfmipi_cfg nrfmipicfg;
extern struct dma_device *m2mdma;
struct hgusb20_os_dev usb20_os_dev;
struct hgusb20_dev usb20_dev = {
.usb_hw = (void *)HG_USB20_DEVICE_BASE,
.usb_os_msg = &usb20_os_dev,
.ep_irq_num = USB20MC_IRQn,
.dma_irq_num = USB20DMA_IRQn,
//.flags = BIT(HGUSB20_FLAGS_FULL_SPEED),
};
struct hgsdio20_slave sdioslave = {
.hw = (void *)HG_SDIO20_SLAVE_BASE,
.irq_num = SDIO_IRQn,
.rst_irq_num = SDIO_RST_IRQn,
//.block_size = 64,
};
struct hg_crc crc32_module = {
.hw = (void *)HG_CRC32_BASE,
.irq_num = CRC_IRQn,
};
struct hg_sysaes_v3 sysaes = {
.hw = (void *)HG_SYSAES_BASE,
.irq_num = SPACC_PKA_IRQn,
};
struct hgsha_v0 sha = {
.hw = (void *)HG_SHA_BASE,
.irq_hw_num = SPACC_PKA_IRQn,
.irq_num = SHA_VIRTUAL_IRQn,
};
struct hguart_v2 uart0 = {
.hw = HG_UART0_BASE,
.irq_num = UART0_IRQn
};
struct hguart_v2 uart1 = {
.hw = HG_UART1_BASE,
.irq_num = UART1_IRQn,
};
struct hguart_v4 uart4 = {
.hw = HG_UART4_BASE,
.irq_num = UART4_IRQn,
.comm_irq_num = UART45_IRQn,
};
struct hguart_v4 uart5 = {
.hw = HG_UART5_BASE,
.irq_num = UART5_IRQn,
.comm_irq_num = UART45_IRQn,
};
struct hggpio_v4 gpioa = {
.hw = HG_GPIOA_BASE,
.comm_irq_num = GPIOABCE_IRQn,
.irq_num = GPIOA_IRQn,
.pin_num = {PA_0, PA_15},
};
struct hggpio_v4 gpiob = {
.hw = HG_GPIOB_BASE,
.comm_irq_num = GPIOABCE_IRQn,
.irq_num = GPIOB_IRQn,
.pin_num = {PB_0, PB_15},
};
struct hggpio_v4 gpioc = {
.hw = HG_GPIOC_BASE,
.comm_irq_num = GPIOABCE_IRQn,
.irq_num = GPIOC_IRQn,
.pin_num = {PC_0, PC_15},
};
struct hggpio_v4 gpioe = {
.hw = HG_GPIOE_BASE,
.comm_irq_num = GPIOABCE_IRQn,
.irq_num = GPIOE_IRQn,
.pin_num = {PE_0, PE_15},
};
struct mem_dma_dev mem_dma = {
.hw = (void *)M2M_DMA_BASE,
.irq_num = M2M0_IRQn,
};
struct hg_gmac_eva_v2 gmac = {
.hw = HG_GMAC_BASE,
.irq_num = GMAC_IRQn,
.tx_buf_size = 4 * 1024,
.rx_buf_size = 8 * 1024,
.modbus_devid = HG_ETH_MDIOBUS0_DEVID,
.phy_devid = HG_ETHPHY0_DEVID,
.mdio_pin = PIN_GMAC_RMII_MDIO,
.mdc_pin = PIN_GMAC_RMII_MDC,
};
struct hgtimer_v4 timer0 = {
.hw = TIMER0_BASE,
.irq_num = TIM0_IRQn,
};
struct hgtimer_v4 timer1 = {
.hw = TIMER1_BASE,
.irq_num = TIM1_IRQn,
};
struct hgtimer_v4 timer2 = {
.hw = TIMER2_BASE,
.irq_num = TIM2_IRQn,
};
struct hgtimer_v4 timer3 = {
.hw = TIMER3_BASE,
.irq_num = TIM3_IRQn,
};
struct hgtimer_v7 simtimer0 = {
.hw = SIMPLE_TIMER0_BASE,
.irq_num = STMR012345_IRQn,
};
struct hgtimer_v5 led_timer0 = {
.hw = LED_TIMER0_BASE,
.irq_num = LED_TMR_IRQn,
};
struct hgpwm_v0 pwm = {
.channel[0] = (void *) &timer0,
.channel[1] = (void *) &timer1,
.channel[2] = (void *) &timer2,
.channel[3] = (void *) &timer3,
.channel[4] = (void *) &simtimer0,
};
struct hgcapture_v0 capture = {
.channel[0] = (void *) &timer0,
.channel[1] = (void *) &timer1,
};
struct hgadc_v0 adc = {
.hw = ADKEY_BASE,
.irq_num = ADKEY01_IRQn,
};
struct hgcqspi cqspi = {
.hw = (void *)QSPI_BASE,
.irq_num = QSPI_IRQn,
.opened = 0,
};
struct hg_xspi xspi = {
.hw = (void *)HG_OSPI_BASE,
.irq_num = OSPI_IRQn,
.opened = 0,
};
struct hgspi_v3 spi0 = {
.hw = SPI0_BASE,
.irq_num = SPI0_IRQn,
};
struct hgspi_v3 spi1 = {
.hw = SPI1_BASE,
.irq_num = SPI1_IRQn,
};
struct hgspi_v3 spi2 = {
.hw = SPI2_BASE,
.irq_num = SPI2_IRQn,
};
struct hgspi_xip spi7 = {
.hw = QSPI_BASE,
};
struct hgi2c_v1 iic1 = {
.hw = IIC1_BASE,
.irq_num = SPI1_IRQn,
};
struct hgi2c_v1 iic2 = {
.hw = IIC2_BASE,
.irq_num = SPI2_IRQn,
};
//struct hgi2c iic3 = {
// .hw = IIC3_BASE,
// .irq_num = SPI3_IRQn,
//};
struct hgdvp dvp = {
.hw = DVP_BASE,
.irq_num = DVP_IRQn,
};
struct hgjpg jpg0 = {
.hw = JPG0_BASE,
#ifdef FPGA_SUPPORT
.thw = MJPEG0_TAB_BASE,
#else
.thw = MJPEG0_TAB_BASE,
#endif
.irq_num = MJPEG01_IRQn,
};
struct hgjpg jpg1 = {
.hw = JPG1_BASE,
#ifdef FPGA_SUPPORT
.thw = MJPEG1_TAB_BASE,
#else
.thw = MJPEG1_TAB_BASE,
#endif
.irq_num = MJPEG01_IRQn,
};
struct hgvpp vpp = {
.hw = VPP_BASE,
.irq_num = VPP_IRQn,
};
struct hgprc prc = {
.hw = PRC_BASE,
.irq_num = PRC_IRQn,
};
struct hgscale scale1 = {
.hw = SCALE1_BASE,
.irq_num = SCALE1_IRQn,
};
struct hgscale scale2 = {
.hw = SCALE2_BASE,
.irq_num = SCALE2_IRQn,
};
struct hgscale scale3 = {
.hw = SCALE3_BASE,
.irq_num = SCALE3_IRQn,
};
struct hglcdc lcdc = {
.hw = LCDC_BASE,
.irq_num = LCD_IRQn,
};
struct hgof of = {
.hw = OF_BASE,
};
struct hgsdh sdh = {
.hw = SDHOST_BASE,
.irq_num = SDHOST_IRQn,
};
struct hgi2s_v0 i2s0 = {
.hw = HG_IIS0_BASE,
.irq_num = IIS0_IRQn,
};
struct hgi2s_v0 i2s1 = {
.hw = HG_IIS1_BASE,
.irq_num = IIS1_IRQn,
};
struct hgpdm_v0 pdm = {
.hw = HG_PDM_BASE,
.irq_num = PDM_IRQn,
};
struct ethernet_mdio_bus mdio_bus0;
//
struct ethernet_phy_device ethernet_phy0 = {
.addr = 0x01,
.drv = &ip101g_driver,
};
struct hg_audio_v0 auadc = {
.hw = AUDIO_BASE,
.irq_num = AUDIO_SUBSYS1_IRQn,
.p_comm = (void *)&auadc.comm_dat,
.dev_type = AUDIO_TYPE_AUADC,
};
struct hg_audio_v0 audac = {
.hw = AUDIO_BASE,
.irq_num = AUDIO_SUBSYS2_IRQn,
.p_comm = (void *)&auadc.comm_dat,
.dev_type = AUDIO_TYPE_AUDAC,
};
struct hg_audio_v0 aufade = {
.hw = AUDIO_BASE,
.irq_num = 0,
.p_comm = (void *)&auadc.comm_dat,
.dev_type = AUDIO_TYPE_AUFADE,
};
struct hg_audio_v0 aualaw = {
.hw = AUDIO_BASE,
.irq_num = AUALAW_IRQn,
.p_comm = (void *)&auadc.comm_dat,
.dev_type = AUDIO_TYPE_AUALAW,
};
struct hg_audio_v0 auvad = {
.hw = AUDIO_BASE,
.irq_num = AUVAD_IRQn,
.p_comm = (void *)&auadc.comm_dat,
.dev_type = AUDIO_TYPE_AUVAD,
};
struct hg_audio_v0 aueq = {
.p_comm = (void *)&auadc.comm_dat,
.dev_type = AUDIO_TYPE_AUEQ,
};
#ifdef PSRAM_EN
struct spi_nor_flash flash0 = {
.spidev = (struct spi_device *)&spi0,
.spi_config = {12000000, SPI_CLK_MODE_0, SPI_WIRE_NORMAL_MODE, 0},
.vendor_id = 0,
.product_id = 0,
.size = 0x200000, /* Special External-Flash Size */
.block_size = 0x10000,
.sector_size = 0x1000,
.page_size = 256,
.mode = SPI_NOR_NORMAL_SPI_MODE,
};
#else
struct spi_nor_flash flash0 = {
.spidev = (struct spi_device *)&spi7,
.spi_config = {12000000, SPI_CLK_MODE_0, SPI_WIRE_NORMAL_MODE, 0},
.vendor_id = 0,
.product_id = 0,
.size = 0x200000, /* Special External-Flash Size */
.block_size = 0x10000,
.sector_size = 0x1000,
.page_size = 4096,
.mode = SPI_NOR_XIP_MODE,
};
#endif
extern uint32_t get_flash_cap();
void device_init(void)
{
extern void *console_handle;
uint32_t flash_size = get_flash_cap();
if (flash_size > 0) {
flash0.size = flash_size;
}
hggpio_v4_attach(HG_GPIOA_DEVID, &gpioa);
hggpio_v4_attach(HG_GPIOB_DEVID, &gpiob);
hggpio_v4_attach(HG_GPIOC_DEVID, &gpioc);
hggpio_v4_attach(HG_GPIOE_DEVID, &gpioe);
hgi2s_v0_attach(HG_IIS0_DEVID, &i2s0);
hgi2s_v0_attach(HG_IIS1_DEVID, &i2s1);
//hguart_v3_attach(HG_UART4_DEVID, &uart4);
//hguart_v3_attach(HG_UART5_DEVID, &uart5);
//hgspi_v2_attach(HG_SPI5_DEVID, &spi5);
//hgspi_v2_attach(HG_SPI6_DEVID, &spi6);
hgpdm_v0_attach(HG_PDM0_DEVID, &pdm);
//hgled_v0_attach(HG_LED0_DEVID, &led);
//hgtimer_v4_attach(HG_TIMER0_DEVID, &timer0);
//hgtimer_v4_attach(HG_TIMER1_DEVID, &timer1);
//hgtimer_v5_attach(HG_LED_TIMER0_DEVID, &led_timer0);
//hgtimer_v6_attach(HG_SUPTMR0_DEVID, &super_timer0);
hgpwm_v0_attach(HG_PWM0_DEVID, &pwm);
//hgcapture_v0_attach(HG_CAPTURE0_DEVID, &capture);
//hgadc_v0_attach(HG_ADC1_DEVID, &adc1);
hgadc_v0_attach(HG_ADC0_DEVID, &adc);
hguart_v2_attach(HG_UART0_DEVID, &uart0);
hguart_v2_attach(HG_UART1_DEVID, &uart1);
hguart_v4_attach(HG_UART4_DEVID, &uart4);
#ifdef MACBUS_SDIO
//hgsdio20_slave_attach(HG_SDIOSLAVE_DEVID, &sdioslave);
#endif
hg_m2m_dma_dev_attach(HG_M2MDMA_DEVID, &mem_dma);
m2mdma = (struct dma_device *)&mem_dma;
#ifdef ROM_FUNC_ENABLE
/* excute again because mrom function not define func dev_register*/
dev_register(HG_WPHY_DEVID, (struct dev_obj *)&wphy);
#endif
#if USB_EN
#if USB_HOST_EN
hgusb20_host_attach(HG_USBDEV_DEVID, &usb20_dev);
#else
hgusb20_dev_attach(HG_USBDEV_DEVID, &usb20_dev);
#endif
#endif
//hguart_attach(HG_UART0_DEVID, &uart0);
#if DVP_EN
hgdvp_attach(HG_DVP_DEVID, &dvp);
#endif
#if JPG_EN
hgjpg_attach(HG_JPG0_DEVID, &jpg0);
hgjpg_attach(HG_JPG1_DEVID, &jpg1);
#endif
#if PRC_EN
hgprc_attach(HG_PRC_DEVID, &prc);
#endif
#if OF_EN
hgof_attach(HG_OF_DEVID, &of);
#endif
#if SCALE_EN
hgscale1_attach(HG_SCALE1_DEVID, &scale1);
hgscale2_attach(HG_SCALE2_DEVID, &scale2);
hgscale3_attach(HG_SCALE3_DEVID, &scale3);
#endif
#if LCD_EN
hglcdc_attach(HG_LCDC_DEVID,&lcdc);
#endif
#if VPP_EN
hgvpp_attach(HG_VPP_DEVID, &vpp);
#endif
#if SDH_EN
hgsdh_attach(HG_SDIOHOST_DEVID, &sdh);
#endif
hgpwm_v0_attach(HG_PWM0_DEVID, &pwm);
// hgtimer_v4_attach(HG_TIMER0_DEVID, &timer0);
#if PWM_EN
hgtimer_v4_attach(HG_TIMER0_DEVID, &timer0);
hgtimer_v4_attach(HG_TIMER1_DEVID, &timer1);
hgtimer_v4_attach(HG_TIMER2_DEVID, &timer2);
hgtimer_v4_attach(HG_TIMER3_DEVID, &timer3);
hgtimer_v7_attach(HG_SIMTMR0_DEVID, &simtimer0);
hgpwm_v0_attach(HG_PWM0_DEVID, &pwm);
hgcapture_v0_attach(HG_CAPTURE0_DEVID, &capture);
#endif
// hg_gmac_v2_attach(HG_ETH_GMAC_DEVID, &gmac);
hg_crc_attach(HG_CRC_DEVID, &crc32_module);
hg_sysaes_v3_attach(HG_HWAES0_DEVID, &sysaes);
hgsha_v0_attach(HG_SHA_DEVID, &sha);
// hgtimer_attach(HG_TIMER0_DEVID, &timer0);
// hgtimer_attach(HG_TIMER1_DEVID, &timer1);
// hgtimer_attach(HG_TIMER2_DEVID, &timer2);
// hgtimer_attach(HG_TIMER3_DEVID, &timer3);
// hgtimer_attach(HG_TIMER4_DEVID, &timer4);
// hgtimer_attach(HG_TIMER5_DEVID, &timer5);
// hgtimer_attach(HG_TIMER6_DEVID, &timer6);
// hgtimer_attach(HG_TIMER7_DEVID, &timer7);
hgspi_v3_attach(HG_SPI0_DEVID, &spi0);
//hgspi_v3_attach(HG_SPI1_DEVID, &spi1);
hgspi_xip_attach(HG_SPI7_DEVID, &spi7);
// hgspi_v1_attach(SPI3_DEVID, &spi3);
spi_nor_attach(&flash0, HG_FLASH0_DEVID);
// hgi2c_v1_attach(HG_I2C0_DEVID, &iic0);
hgspi_v3_attach(HG_SPI1_DEVID, &spi1);
hgi2c_v1_attach(HG_I2C2_DEVID, &iic2);
// hgi2c_attach(HG_I2C3_DEVID, &iic3);
//hgcqspi_attach(HG_QSPI_DEVID, &cqspi);
eth_mdio_bus_attach(HG_ETH_MDIOBUS0_DEVID, &mdio_bus0);
eth_phy_attach(HG_ETHPHY0_DEVID, &ethernet_phy0);
hg_audio_v0_attach(HG_AUADC_DEVID, &auadc);
hg_audio_v0_attach(HG_AUDAC_DEVID, &audac);
hg_audio_v0_attach(HG_AUVAD_DEVID, &auvad);
hg_audio_v0_attach(HG_AUALAW_DEVID, &aualaw);
hg_audio_v0_attach(HG_AUEQ_DEVID, &aueq);
hg_audio_v0_attach(HG_AUFADE_DEVID, &aufade);
uart_open((struct uart_device *)&uart0, 921600);
console_handle = (void*)&uart0;
//hg_gmac_v2_attach(HG_GMAC_DEVID, &gmac);
#if UART_FLY_CTRL_EN
uart_open((struct uart_device *)&uart0, 115200);
#endif
#ifdef CONFIG_SLEEP
hg_xspi_attach(HG_XSPI_DEVID, &xspi);
#endif
#ifdef LMAC_BGN_PCF
if(dev_get(HG_TIMER3_DEVID)){
os_printf("PCF_error: timer3 used\r\n");
}else{
hgtimer_v4_attach(HG_TIMER3_DEVID, &timer3);
}
#endif
#ifdef LMAC_BGN_RAW
if(dev_get(HG_TIMER3_DEVID)){
os_printf("RAW_error: timer3 used\r\n");
}else{
hgtimer_v4_attach(HG_TIMER3_DEVID, &timer3);
}
#endif
extern void device_burst_set(void);
device_burst_set();
}
void device_burst_set(void)
{
//ll_sysctrl_dma2ahb_m2m1_wr_lmac_wave_wr_priority_switch(1);
ll_sysctrl_dma2ahb_osd_enc_rd_lmac_wave_rd_priority_switch(1);
ll_sysctrl_dma2ahb_pri_switch(0xE00);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_LMAC_WAVE_RD, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_LMAC_WAVE_WR, DMA2AHB_BURST_SIZE_32);
//ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_MJPEG1_SCALE2_YUV_WR, DMA2AHB_BURST_SIZE_64);
//ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_MJPEG1_RD, DMA2AHB_BURST_SIZE_64);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_M2M0_RD, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_M2M0_WR, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_M2M1_RD, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_M2M1_WR, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_SCALE3_Y_WR, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_SCALE3_U_WR, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_SCALE3_V_WR, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_LCD_ROTATE_RD, DMA2AHB_BURST_SIZE_16);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_OSD_ENC_RD, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_OSD_ENC_WR, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_burst_set(DMA2AHB_BURST_CH_OSD0_RD, DMA2AHB_BURST_SIZE_32);
ll_sysctrl_dma2ahb_select(DMA2AHB_BURST_OBJ_OSPI);
}
struct gpio_device *gpio_get(uint32 pin)
{
if (pin >= gpioa.pin_num[0] && pin <= gpioa.pin_num[1]) {
return (struct gpio_device *)&gpioa;
} else if (pin >= gpiob.pin_num[0] && pin <= gpiob.pin_num[1]) {
return (struct gpio_device *)&gpiob;
} else if (pin >= gpioc.pin_num[0] && pin <= gpioc.pin_num[1]) {
return (struct gpio_device *)&gpioc;
} else if (pin >= gpioe.pin_num[0] && pin <= gpioe.pin_num[1]) {
return (struct gpio_device *)&gpioe;
}
return NULL;
}
int32 syscfg_info_get(struct syscfg_info *pinfo)
{
#if SYSCFG_ENABLE
pinfo->flash1 = &flash0;
pinfo->flash2 = &flash0;
pinfo->size = pinfo->flash1->sector_size;
pinfo->addr1 = pinfo->flash1->size - (2 * pinfo->size);
pinfo->addr2 = pinfo->flash1->size - pinfo->size;
pinfo->erase_mode = SYSCFG_ERASE_MODE_SECTOR;
ASSERT((pinfo->addr1 & ~(pinfo->flash1->sector_size - 1)) == pinfo->addr1);
ASSERT((pinfo->addr2 & ~(pinfo->flash2->sector_size - 1)) == pinfo->addr2);
ASSERT((pinfo->size >= sizeof(struct sys_config)) &&
(pinfo->size == (pinfo->size & ~(pinfo->flash1->sector_size - 1))));
return 0;
#else
return -1;
#endif
}
int32 ota_fwinfo_get(struct ota_fwinfo *pinfo)
{
#if 1
pinfo->flash0 = &flash0;
pinfo->flash1 = &flash0;
pinfo->addr0 = 0;
pinfo->addr1 = flash0.size/2;
return 0;
#else
return -1;
#endif
}
project/device.h
+7
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#ifndef _TXW81X_DEVICE_H_
#define _TXW81X_DEVICE_H_
extern void device_init(void);
#endif
project/fpv_app_umac4.cdkproj
+8447
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project/loader_compress.bin
BIN
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project/main.c
+1387
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project/makecode.exe
BIN
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project/makecode.ini
+75
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@@ -0,0 +1,75 @@
[COMMON]
CodeFile=txw81x_fpv.bin
KeyFilePath=
CodeType=1 ; destination code type: 1(SPI), 2(EFLASH_NVR), 3(EFLASH)
ParamOffset=180 ; code param address Offset
ParamFile=param.bin
MemEndianLE=1 ; code endian : little endian
CPU_ID=0
CHIP_ID=8410 ; chip id
CustomerID=1001 ; customer id, when aes enabled, CustomerID is use to Authorization & code encrypt
Post_Script= merge.bat
[SPI]
CodeCRC16=1 ; spi code crc enable
Flag=5A69 ; fixed
Version=0 ; code version
CodeLoadToSramAddr=18000000 ; code load to sram start address
CodeExeAddr=18000000 ; code run start address
CodeAddrOffset=c00 ; code load from spi flash address Offset >= 1024 + param length
CodeLoadLen=2000 ; code load to sram length
SPI_SIZE=100000 ; spi flash size
SPI_CLK_MHZ=3c ; spi clk : 13Mhz
DriverStrength=0 ; DriverStrength : [0/1/2/3], bigger sign stronger
PLL_SRC_MHZ=28 ;
PLL_EN=1 ;
DebugInfoEn=0 ;
AesEnable=0 ; aes encrypt enable
; advance config
ReadCmd=EB ; spi read cmd index : normal(03)/fast(0B)/dual(3B)/quad(6B)/QPI(EB)
ReadCmdDummy=6 ; dummy clk
ClockMode=0 ; clock mode [0,3]
SampleDelay=55AA ; 16bit sample delay cnt in spi_clk_divor
WireModeWhenCmd=1 ; wire mode : [1/2/4], 6 for 3wire mode
WireModeWhenAddr=4 ; wire mode : [1/2/4], 6 for 3wire mode
WireModeWhenData=4 ; wire mode : [1/2/4], 6 for 3wire mode
WireMode4Select=0 ; 4wire mode : D2/D3 io select[0,2]
WireMode4En=1 ; 4wire mode enable[0,1]
SpecSquenceEn=1 ; spec cmd squence before cmd read, eg.use for dual/quad cmd
SpecSquenceNumbers=4 ; spec cmd squence (format: cmd + dummy + data_lens + data) numbers
SpecSquence0=06000000 ; spec cmd "write enable "
SpecSquence1=0100020002 ; spec cmd "qual mode enable for winbond "
SpecSquence2=31000102 ; spec cmd "qual mode enable for winbond "
SpecSquence3=05800101 ; spec cmd "wait busy "
SpecSquence4=38000000 ; spec cmd "QPI enable"
SpecSquence5=C0000133 ; spec cmd "Set Read Param"
[EFLASH_NVR]
CRC32_EN=1 ; code crc32 enable
[EFLASH]
CHIP_ID=5002 ; chip id
EXE_ADDR=10006000 ; code run start address
CODE_COPIES=2 ; code copies
CODE_LEN=8000 ; code length
CRC32_EN=1 ; code crc32 enable
NVR0_EW_EN=1 ; nvr0 erase & program enable
NVR1_EW_EN=1 ; nvr1 erase & program enable
NVR2_EW_EN=1 ; nvr2 erase & program enable
MAIN_EW_EN_BITMAP=FFFFFFFF ; main erase & program enable : bitmap to all main array
EXTERNAL_KEY_DIS=1 ; external key disable : 1(interal key), 0(external key)
EXTERNAL_KEY=0 ; external key
USERDATA_AREA_CNT=2 ; user data area size
UART_BOOT_EN=1 ; uart boot enable
NVR_CODE_BAK_EN=0 ; nvr code bak enable
NVR_CODE_BAK_SECTOR_ADDR=120 ; nvr code bak addr
UART_BOOT_PIN_SEL=13 ; uart boot pin select
SWD_Remaping_en=0 ; swd remapping enable
SYS_MCLR_EN=1 ; mclr pin enable
SYS_SWD_EN=1 ; swd enable
SYS_SWD_IO_PU_EN=1 ; swd io default pull-up enable 1:enable, 0:pull-down
MAIN_CODE_CRC32_HWCHECK_EN=1 ; main code crc32 chip verify enable
project/makecode_post.bat
+18
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cd /d %~dp0
set dirname=%1
set dirname=%dirname:~0,-4%
if not exist bakup md bakup
if not exist bakup\%dirname% md bakup\%dirname%
copy .\Obj\*.elf bakup\%dirname%\
copy .\Lst\*.map bakup\%dirname%\
copy makedis.bat bakup\%dirname%\
del /q/f loader.bin
del /q/f code512.bin
del /q/f param.bin
del /q/f program.bin
del /q/f project_merge.bin
project/merge.bat
+26
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cd /d %~dp0
set dirname=%1
set dirname2=%dirname:~0,-4%
del /q/f APP.bin
copy %dirname% program.bin
copy %dirname% APP.bin
if exist .\script\xz.exe (
BinScript.exe real_code.BinScript
.\script\xz.exe -kfz -0 realcode.bin
.\script\compress.exe APP.bin loader_compress.bin compress.bin APP_compress.bin
copy APP_compress.bin %dirname2%_compress.bin
)
set dirname=%dirname:~0,-4%
set dirname=%dirname%_%date:~0,4%%date:~5,2%%date:~8,2%%time:~0,2%%time:~3,2%%time:~6,2%
if not exist bakup md bakup
if not exist bakup\%dirname% md bakup\%dirname%
copy Lst\* bakup\%dirname%\
copy project.map bakup\%dirname%\
project/parameter.bincfg
BIN
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project/parameter.cfg
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project/prebuild.sh
+3
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#!/bin/bash
rm -f Obj/common_common.o
psramCFG/lua.exe psramCFG/gen_psram_cfg.lua psramCFG/
project/precompile.sh
+5
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#!/bin/bash
[ ! -f precompile.exe ] && cp -v ../../../../tools/precompile/Debug/precompile.exe precompile.exe
mkdir -p tmp
precompile.exe ${ProjectPath} $1
exit 0
project/project_config.h
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project/psramCFG/gen_psram_cfg.lua
+39
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@@ -0,0 +1,39 @@
local base_path = arg[1]
local file_table = {}
local select_name = nil
local file = io.open("psram_cfg.h","rb")
local buf
for line in file:lines() do
match_str = string.match(line,"[%s]*PSRAM_DEF%((.*)%)")
--解析是否为需要的文件名
if match_str ~= nil then
file_table[match_str] = true
--解析是否为选中的文件名
else
match_str = string.match(line,"[%s]*PSRAM_SELECT%((.*)%)")
if match_str ~= nil then
select_name = match_str
end
end
end
file:close()
if select_name ~= nil then
filename = base_path .. "parameter-" .. select_name .. ".bincfg"
print(filename)
--将文件写入到parameter.bincfg中,外部拷贝该文件到project目录下
file = io.open(filename,"rb")
if file ~= nil then
buf = file:read("*a")
file:close()
file = io.open("parameter.bincfg","wb")
file:write(buf)
file:close()
print("config psram file success:",filename)
else
print("config psram file err,maybe this is extern psram")
end
end
project/psramCFG/lua.dll
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project/psramCFG/lua.exe
BIN
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project/psramCFG/parameter-16MByte.bincfg
BIN
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project/psramCFG/parameter-16MByte_ui.setcfg
+379
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[COMMON]
version=V1.0.0
itemNum=47
[ITEM1]
offset=0
name=total_size
type=uint16
size=1
input=800
storage=0008
[ITEM2]
offset=2
name=magic_num
type=uint16
size=1
input=1A2B
storage=2B1A
[ITEM3]
offset=4
name=fn
type=uint8
size=1
input=0
storage=00
[ITEM4]
offset=5
name=size
type=uint8
size=1
input=4
storage=04
[ITEM5]
offset=6
name=version
type=uint32
size=1
input=98
storage=98000000
[ITEM6]
offset=10
name=fn_loader
type=uint8
size=1
input=2
storage=02
[ITEM7]
offset=11
name=size
type=uint8
size=1
input=68
storage=68
[ITEM8]
offset=12
name=ospi_attr
type=uint8
size=1
input=3D
storage=3D
[ITEM9]
offset=13
name=ospi_attr_tx_delay
type=uint8
size=1
input=a
storage=0A
[ITEM10]
offset=14
name=opsi_attr_phy_init
type=uint8
size=1
input=e4
storage=E4
[ITEM11]
offset=15
name=opsi_attr_adjust
type=uint8
size=1
input=F
storage=0F
[ITEM12]
offset=16
name=io_cs
type=uint16
size=1
input=0
storage=0000
[ITEM13]
offset=18
name=io_clk_p
type=uint16
size=1
input=0
storage=0000
[ITEM14]
offset=20
name=io_clk_n
type=uint16
size=1
input=0
storage=0000
[ITEM15]
offset=22
name=io_dqs
type=uint16
size=1
input=0
storage=0000
[ITEM16]
offset=24
name=io_dm
type=uint16
size=1
input=0
storage=0000
[ITEM17]
offset=26
name=io_rst
type=uint16
size=1
input=0
storage=0000
[ITEM18]
offset=28
name=io_d0
type=uint16
size=1
input=0
storage=0000
[ITEM19]
offset=30
name=io_d1
type=uint16
size=1
input=0
storage=0000
[ITEM20]
offset=32
name=io_d2
type=uint16
size=1
input=0
storage=0000
[ITEM21]
offset=34
name=io_d3
type=uint16
size=1
input=0
storage=0000
[ITEM22]
offset=36
name=io_d4
type=uint16
size=1
input=0
storage=0000
[ITEM23]
offset=38
name=io_d5
type=uint16
size=1
input=0
storage=0000
[ITEM24]
offset=40
name=io_d6
type=uint16
size=1
input=0
storage=0000
[ITEM25]
offset=42
name=io_d7
type=uint16
size=1
input=0
storage=0000
[ITEM26]
offset=44
name=PE16CON
type=uint32
size=1
input=0x40000101
storage=01010040
[ITEM27]
offset=48
name=OSPI_MAP_CTL0
type=uint32
size=1
input=0xbcde6645
storage=4566DEBC
[ITEM28]
offset=52
name=OSPI_MAP_CTL1
type=uint32
size=1
input=0xFFFF789a
storage=9A78FFFF
[ITEM29]
offset=56
name=NEW_ADD_CONFIG0
type=uint32
size=1
input=0x39ee001a
storage=1A00EE39
[ITEM30]
offset=60
name=NEW_ADD_CONFIG1
type=uint32
size=1
input=0x07104a28
storage=284A1007
[ITEM31]
offset=64
name=psram_attr0
type=uint32
size=1
input=0xc040a020
storage=20A040C0
[ITEM32]
offset=68
name=psram_attr1
type=uint32
size=1
input=0x01016287
storage=87620101
[ITEM33]
offset=72
name=psram_attr2
type=uint32
size=1
input=0x00040020
storage=20000400
[ITEM34]
offset=76
name=psram_attr3
type=uint32
size=1
input=0xa0938d1b
storage=1B8D93A0
[ITEM35]
offset=80
name=psram_attr4
type=uint32
size=1
input=0x000005c0
storage=C0050000
[ITEM36]
offset=84
name=psram_attr5
type=uint32
size=1
input=00500000
storage=00005000
[ITEM37]
offset=88
name=psram_attr6
type=uint32
size=1
input=0xF00400
storage=0004F000
[ITEM38]
offset=92
name=reset_num
type=uint8
size=1
input=1
storage=01
[ITEM39]
offset=93
name=reset_daley
type=uint8
size=1
input=7
storage=07
[ITEM40]
offset=94
name=reset_cmd1
type=uint16
size=1
input=0bff
storage=FF0B
[ITEM41]
offset=96
name=reset_cmd2
type=uint16
size=1
input=0bff
storage=FF0B
[ITEM42]
offset=98
name=reset_cmd345678
type=uint8[]
size=12
input=0
storage=000000000000000000000000
[ITEM43]
offset=110
name=init_num
type=uint8
size=1
input=2
storage=02
[ITEM44]
offset=111
name=init_daley
type=uint8
size=1
input=7
storage=07
[ITEM45]
offset=112
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project/psramCFG/parameter-2MByte.bincfg
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project/psramCFG/parameter-4MByte.bincfg
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project/psramCFG/parameter-4MByteV2.bincfg
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project/psramCFG/parameter-4MByte_dri0_240M.bincfg
BIN
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project/psramCFG/parameter-4MByte_ui.setcfg
+371
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input=0bff
storage=FF0B
[ITEM41]
offset=96
name=reset_cmd2
type=uint16
size=1
input=0bff
storage=FF0B
[ITEM42]
offset=98
name=reset_cmd345678
type=uint8[]
size=12
input=0
storage=000000000000000000000000
[ITEM43]
offset=110
name=init_num
type=uint8
size=1
input=1
storage=01
[ITEM44]
offset=111
name=init_daley
type=uint8
size=1
input=7
storage=07
[ITEM45]
offset=112
name=init_opt1
type=uint8[]
size=3
input=140000
storage=140000
[ITEM46]
offset=115
name=init_opt2~7
type=uint8[]
size=21
input=0
storage=000000000000000000000000000000000000000000
project/psramCFG/parameter-8MByte.bincfg
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project/psramCFG/parameter-8MByte_240M.bincfg
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project/psramCFG/parameter-8MByte_240M_ui.setcfg
+379
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@@ -0,0 +1,379 @@
[COMMON]
version=V1.0.0
itemNum=47
[ITEM1]
offset=0
name=total_size
type=uint16
size=1
input=800
storage=0008
[ITEM2]
offset=2
name=magic_num
type=uint16
size=1
input=1A2B
storage=2B1A
[ITEM3]
offset=4
name=fn
type=uint8
size=1
input=0
storage=00
[ITEM4]
offset=5
name=size
type=uint8
size=1
input=4
storage=04
[ITEM5]
offset=6
name=version
type=uint32
size=1
input=98
storage=98000000
[ITEM6]
offset=10
name=fn_loader
type=uint8
size=1
input=2
storage=02
[ITEM7]
offset=11
name=size
type=uint8
size=1
input=68
storage=68
[ITEM8]
offset=12
name=ospi_attr
type=uint8
size=1
input=3D
storage=3D
[ITEM9]
offset=13
name=ospi_attr_tx_delay
type=uint8
size=1
input=a
storage=0A
[ITEM10]
offset=14
name=opsi_attr_phy_init
type=uint8
size=1
input=e4
storage=E4
[ITEM11]
offset=15
name=opsi_attr_adjust
type=uint8
size=1
input=F
storage=0F
[ITEM12]
offset=16
name=io_cs
type=uint16
size=1
input=0
storage=0000
[ITEM13]
offset=18
name=io_clk_p
type=uint16
size=1
input=0
storage=0000
[ITEM14]
offset=20
name=io_clk_n
type=uint16
size=1
input=0
storage=0000
[ITEM15]
offset=22
name=io_dqs
type=uint16
size=1
input=0
storage=0000
[ITEM16]
offset=24
name=io_dm
type=uint16
size=1
input=0
storage=0000
[ITEM17]
offset=26
name=io_rst
type=uint16
size=1
input=0
storage=0000
[ITEM18]
offset=28
name=io_d0
type=uint16
size=1
input=0
storage=0000
[ITEM19]
offset=30
name=io_d1
type=uint16
size=1
input=0
storage=0000
[ITEM20]
offset=32
name=io_d2
type=uint16
size=1
input=0
storage=0000
[ITEM21]
offset=34
name=io_d3
type=uint16
size=1
input=0
storage=0000
[ITEM22]
offset=36
name=io_d4
type=uint16
size=1
input=0
storage=0000
[ITEM23]
offset=38
name=io_d5
type=uint16
size=1
input=0
storage=0000
[ITEM24]
offset=40
name=io_d6
type=uint16
size=1
input=0
storage=0000
[ITEM25]
offset=42
name=io_d7
type=uint16
size=1
input=0
storage=0000
[ITEM26]
offset=44
name=PE16CON
type=uint32
size=1
input=0x40000101
storage=01010040
[ITEM27]
offset=48
name=OSPI_MAP_CTL0
type=uint32
size=1
input=0x7654fe89
storage=89FE5476
[ITEM28]
offset=52
name=OSPI_MAP_CTL1
type=uint32
size=1
input=0xFFFFdcba
storage=BADCFFFF
[ITEM29]
offset=56
name=NEW_ADD_CONFIG0
type=uint32
size=1
input=0x39ee001a
storage=1A00EE39
[ITEM30]
offset=60
name=NEW_ADD_CONFIG1
type=uint32
size=1
input=0x07104a28
storage=284A1007
[ITEM31]
offset=64
name=psram_attr0
type=uint32
size=1
input=0xc040a020
storage=20A040C0
[ITEM32]
offset=68
name=psram_attr1
type=uint32
size=1
input=0x01016276
storage=76620101
[ITEM33]
offset=72
name=psram_attr2
type=uint32
size=1
input=0x00040020
storage=20000400
[ITEM34]
offset=76
name=psram_attr3
type=uint32
size=1
input=0xa0938d17
storage=178D93A0
[ITEM35]
offset=80
name=psram_attr4
type=uint32
size=1
input=0x000005c0
storage=C0050000
[ITEM36]
offset=84
name=psram_attr5
type=uint32
size=1
input=00500000
storage=00005000
[ITEM37]
offset=88
name=psram_attr6
type=uint32
size=1
input=0xF00400
storage=0004F000
[ITEM38]
offset=92
name=reset_num
type=uint8
size=1
input=1
storage=01
[ITEM39]
offset=93
name=reset_daley
type=uint8
size=1
input=7
storage=07
[ITEM40]
offset=94
name=reset_cmd1
type=uint16
size=1
input=0bff
storage=FF0B
[ITEM41]
offset=96
name=reset_cmd2
type=uint16
size=1
input=0bff
storage=FF0B
[ITEM42]
offset=98
name=reset_cmd345678
type=uint8[]
size=12
input=0
storage=000000000000000000000000
[ITEM43]
offset=110
name=init_num
type=uint8
size=1
input=2
storage=02
[ITEM44]
offset=111
name=init_daley
type=uint8
size=1
input=7
storage=07
[ITEM45]
offset=112
name=init_opt1
type=uint8[]
size=3
input=170000
storage=170000
[ITEM46]
offset=115
name=init_opt2
type=uint8[]
size=3
input=A00400
storage=A00400
[ITEM47]
offset=118
name=init_opt3~7
type=uint8[]
size=18
input=0
storage=000000000000000000000000000000000000
project/psramCFG/parameter-8MByte_ui.setcfg
+379
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[COMMON]
version=V1.0.0
itemNum=47
[ITEM1]
offset=0
name=total_size
type=uint16
size=1
input=800
storage=0008
[ITEM2]
offset=2
name=magic_num
type=uint16
size=1
input=1A2B
storage=2B1A
[ITEM3]
offset=4
name=fn
type=uint8
size=1
input=0
storage=00
[ITEM4]
offset=5
name=size
type=uint8
size=1
input=4
storage=04
[ITEM5]
offset=6
name=version
type=uint32
size=1
input=98
storage=98000000
[ITEM6]
offset=10
name=fn_loader
type=uint8
size=1
input=2
storage=02
[ITEM7]
offset=11
name=size
type=uint8
size=1
input=68
storage=68
[ITEM8]
offset=12
name=ospi_attr
type=uint8
size=1
input=3D
storage=3D
[ITEM9]
offset=13
name=ospi_attr_tx_delay
type=uint8
size=1
input=a
storage=0A
[ITEM10]
offset=14
name=opsi_attr_phy_init
type=uint8
size=1
input=e4
storage=E4
[ITEM11]
offset=15
name=opsi_attr_adjust
type=uint8
size=1
input=F
storage=0F
[ITEM12]
offset=16
name=io_cs
type=uint16
size=1
input=0
storage=0000
[ITEM13]
offset=18
name=io_clk_p
type=uint16
size=1
input=0
storage=0000
[ITEM14]
offset=20
name=io_clk_n
type=uint16
size=1
input=0
storage=0000
[ITEM15]
offset=22
name=io_dqs
type=uint16
size=1
input=0
storage=0000
[ITEM16]
offset=24
name=io_dm
type=uint16
size=1
input=0
storage=0000
[ITEM17]
offset=26
name=io_rst
type=uint16
size=1
input=0
storage=0000
[ITEM18]
offset=28
name=io_d0
type=uint16
size=1
input=0
storage=0000
[ITEM19]
offset=30
name=io_d1
type=uint16
size=1
input=0
storage=0000
[ITEM20]
offset=32
name=io_d2
type=uint16
size=1
input=0
storage=0000
[ITEM21]
offset=34
name=io_d3
type=uint16
size=1
input=0
storage=0000
[ITEM22]
offset=36
name=io_d4
type=uint16
size=1
input=0
storage=0000
[ITEM23]
offset=38
name=io_d5
type=uint16
size=1
input=0
storage=0000
[ITEM24]
offset=40
name=io_d6
type=uint16
size=1
input=0
storage=0000
[ITEM25]
offset=42
name=io_d7
type=uint16
size=1
input=0
storage=0000
[ITEM26]
offset=44
name=PE16CON
type=uint32
size=1
input=0x40000101
storage=01010040
[ITEM27]
offset=48
name=OSPI_MAP_CTL0
type=uint32
size=1
input=0x7654fe89
storage=89FE5476
[ITEM28]
offset=52
name=OSPI_MAP_CTL1
type=uint32
size=1
input=0xFFFFdcba
storage=BADCFFFF
[ITEM29]
offset=56
name=NEW_ADD_CONFIG0
type=uint32
size=1
input=0x39ee001a
storage=1A00EE39
[ITEM30]
offset=60
name=NEW_ADD_CONFIG1
type=uint32
size=1
input=0x07104a28
storage=284A1007
[ITEM31]
offset=64
name=psram_attr0
type=uint32
size=1
input=0xc040a020
storage=20A040C0
[ITEM32]
offset=68
name=psram_attr1
type=uint32
size=1
input=0x01016254
storage=54620101
[ITEM33]
offset=72
name=psram_attr2
type=uint32
size=1
input=0x00040020
storage=20000400
[ITEM34]
offset=76
name=psram_attr3
type=uint32
size=1
input=0xa0938d0f
storage=0F8D93A0
[ITEM35]
offset=80
name=psram_attr4
type=uint32
size=1
input=0x000005c0
storage=C0050000
[ITEM36]
offset=84
name=psram_attr5
type=uint32
size=1
input=00500000
storage=00005000
[ITEM37]
offset=88
name=psram_attr6
type=uint32
size=1
input=0xA00400
storage=0004A000
[ITEM38]
offset=92
name=reset_num
type=uint8
size=1
input=1
storage=01
[ITEM39]
offset=93
name=reset_daley
type=uint8
size=1
input=7
storage=07
[ITEM40]
offset=94
name=reset_cmd1
type=uint16
size=1
input=0bff
storage=FF0B
[ITEM41]
offset=96
name=reset_cmd2
type=uint16
size=1
input=0bff
storage=FF0B
[ITEM42]
offset=98
name=reset_cmd345678
type=uint8[]
size=12
input=0
storage=000000000000000000000000
[ITEM43]
offset=110
name=init_num
type=uint8
size=1
input=2
storage=02
[ITEM44]
offset=111
name=init_daley
type=uint8
size=1
input=7
storage=07
[ITEM45]
offset=112
name=init_opt1
type=uint8[]
size=3
input=0f0000
storage=0f0000
[ITEM46]
offset=115
name=init_opt2
type=uint8[]
size=3
input=c00400
storage=c00400
[ITEM47]
offset=118
name=init_opt3~7
type=uint8[]
size=18
input=0
storage=000000000000000000000000000000000000
project/psramCFG/parameter-NONE.bincfg
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project/psramCFG/parameter-NONE_ui.setcfg
+43
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@@ -0,0 +1,43 @@
[COMMON]
version=V1.0.0
itemNum=5
[ITEM1]
offset=0
name=total_size
type=uint16
size=1
input=800
storage=0008
[ITEM2]
offset=2
name=magic_num
type=uint16
size=1
input=1A2B
storage=2B1A
[ITEM3]
offset=4
name=fn
type=uint8
size=1
input=0
storage=00
[ITEM4]
offset=5
name=size
type=uint8
size=1
input=4
storage=04
[ITEM5]
offset=6
name=version
type=uint32
size=1
input=98
storage=98000000
project/psram_cfg.h
+32
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@@ -0,0 +1,32 @@
#ifndef __PSRAM_CFG
#define __PSRAM_CFG
/**********************************************************************************
该文件主要为了配置psram的
————PSRAM_DEF:定义了psram初始化的文件名,内部会进行psram的初始化
————PSRAM_SELECT:是选择了哪个psram的参数文件信息,所以要从PSRAM_DEF中选择
____E_PSRAM:这个定义代表是外部psram,请用E开头来代表,新增加外部的psram定义
添加到后面
注意:该文件只要修改PSRAM_SELECT的值,其他不要修改,不然可能会生成失败
***********************************************************************/
#define PSRAM_DEF(name) psrammode##name
#define PSRAM_SELECT(name) NOW_PSRAM = psrammode##name
enum psram_cfg_enum
{
PSRAM_DEF(NONE),
PSRAM_DEF(2MByte),
PSRAM_DEF(4MByte),
PSRAM_DEF(4MByte_dri0_240M),
PSRAM_DEF(4MByteV2),
PSRAM_DEF(8MByte),
PSRAM_DEF(8MByte_240M),
PSRAM_DEF(16MByte),
PSRAM_DEF(E_PSRAM),
PSRAM_DEF(E2MByte),
PSRAM_SELECT(8MByte),
};
#endif
project/script.7z
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project/sys_config.h
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#ifndef __SDK_SYS_CONFIG_H__
#define __SDK_SYS_CONFIG_H__
#include "project_config.h"
#define SYS_CACHE_ENABLE 1
#define PROJECT_TYPE PRO_TYPE_FPV
#ifndef SYSCFG_ENABLE
#define SYSCFG_ENABLE 1
#endif
#ifndef MPOOL_ALLOC
#define MPOOL_ALLOC 1
#endif
#ifndef TXWSDK_POSIX
#define TXWSDK_POSIX
#endif
#define __ram __at_section(".ram.text")
#define __dsleep_text __at_section(".dsleep.text")
#define __dsleep_date __at_section(".dsleep.data")
#define SRAM_POOL_START (srampool_start)
#define SRAM_POOL_SIZE (srampool_end - srampool_start)
#define SYS_FACTORY_PARAM_SIZE 2048
#ifndef SYS_HEAP_SIZE
#define SYS_HEAP_SIZE (SRAM_POOL_SIZE)
#endif
#ifndef WIFI_RX_BUFF_SIZE
#define WIFI_RX_BUFF_SIZE (17*1024)
#endif
#ifndef SYS_HEAP_START
#define SYS_HEAP_START (SRAM_POOL_START)
#endif
#ifndef SKB_POOL_SIZE
#define SKB_POOL_SIZE (30*1024)
#endif
//#define WIFI_SINGLE_DEV
#ifndef DEFAULT_SYS_CLK
#define DEFAULT_SYS_CLK 240000000UL //options: <= 180Mhz
#endif
#ifndef ATCMD_UARTDEV
#define ATCMD_UARTDEV HG_UART0_DEVID
#endif
#define LWIP_NETIF_REMOVE_CALLBACK 1
#define TCPIP_THREAD_PRIO OS_TASK_PRIORITY_BELOW_NORMAL+2
#ifdef PSRAM_HEAP
#define TCPIP_MBOX_SIZE 128
#define DEFAULT_UDP_RECVMBOX_SIZE 64
#define DEFAULT_TCP_RECVMBOX_SIZE 64
#define DEFAULT_ACCEPTMBOX_SIZE 16
//#define MEM_LIBC_MALLOC 1
//#define MEMP_MEM_MALLOC 1
#define MEM_SIZE 80*1024
#define MEMP_NUM_PBUF 40
#define MEMP_NUM_NETCONN 16
#define MEMP_NUM_NETBUF 64
#define MEMP_NUM_UDP_PCB 8
#define MEMP_NUM_TCP_PCB 16
#define MEMP_NUM_TCP_SEG 320
#define PBUF_POOL_SIZE 80
#define TCP_SND_BUF (40 * TCP_MSS)
#define TCP_WND (40 * TCP_MSS)
#endif
#ifndef DCDC_EN
#define DCDC_EN 0 //是否使能DCDC功能。选错会导致芯片重启
#endif
#ifndef WIFI_FEM_CHIP
#define WIFI_FEM_CHIP LMAC_FEM_NONE //FEM芯片类型。LMAC_FEM_NONE以外的值会进行对应的FEM初始化
#endif
#ifndef WIFI_TEMPERATURE_COMPESATE_EN
#define WIFI_TEMPERATURE_COMPESATE_EN 1 //是否使能温度补偿
#endif
#ifndef WIFI_FREQ_OFFSET_TRACK_MODE
#define WIFI_FREQ_OFFSET_TRACK_MODE LMAC_FREQ_OFFSET_TRACK_ALWAYS_ON //默认一直打开频偏跟踪功能
#endif
#ifndef WIFI_HIGH_PRIORITY_TX_MODE_EN
#define WIFI_HIGH_PRIORITY_TX_MODE_EN 0 //是否使能无线高优线发送模式
#endif
#ifndef WIFI_MODULE_80211W_EN
#define WIFI_MODULE_80211W_EN 1 //是否使能802.11w功能
#endif
#ifndef BLE_UUID_128
#define BLE_UUID_128 1
#endif
#ifndef BLE_METER_TEST_EN
#define BLE_METER_TEST_EN 0 //是否使能BLE量产测试命令
#endif
//---dsleep test start------
#ifndef WIFI_PSALIVE_SUPPORT
#define WIFI_PSALIVE_SUPPORT 0
#endif
#ifndef SYS_APP_DSLEEP_TEST
#define SYS_APP_DSLEEP_TEST 0
#endif
#ifndef SYS_APP_UDPKALIVE_TEST
#define SYS_APP_UDPKALIVE_TEST 0
#endif
//---sleep test end------
#endif
project/syscfg.c
+388
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#include "sys_config.h"
#include "typesdef.h"
#include "list.h"
#include "dev.h"
#include "devid.h"
#include "osal/string.h"
#include "osal/semaphore.h"
#include "osal/mutex.h"
#include "osal/irq.h"
#include "osal/task.h"
#include "osal/sleep.h"
#include "osal/timer.h"
#include "hal/gpio.h"
#include "hal/uart.h"
#include "hal/netdev.h"
#include "lib/common/common.h"
#include "lib/umac/umac.h"
#include "lib/syscfg/syscfg.h"
#include "lib/atcmd/libatcmd.h"
#include "lwip/ip_addr.h"
#include "lwip/netdb.h"
#include "syscfg.h"
#include "osal/work.h"
#include "lib/common/dsleepdata.h"
#ifdef CONFIG_SLEEP
#include "lib/lmac/lmac_dsleep.h"
#endif
#ifndef QC_STA_NAME
#define QC_STA_NAME "BGN_test"
#endif
#ifndef QC_STA_PW
#define QC_STA_PW "12345678"
#endif
#ifndef QC_SCAN_TIME
#define QC_SCAN_TIME 200
#endif
#ifndef QC_SCAN_CNT
#define QC_SCAN_CNT 10
#endif
#ifndef QC_SCAN_CHANNEL
#define QC_SCAN_CHANNEL 0x010
#endif
#define SYSCFG_WIFI_MODE(mode) ((mode) == WIFI_MODE_STA ? "sta" : ((mode) == WIFI_MODE_AP ? "ap" : "apsta"))
struct sys_config sys_cfgs = {
.cfg_ver = CFG_VERSION_NUM,
.default_wifi_mode = WIFI_MODE_AP,
.channel = CHANNEL_DEFAULT,
.beacon_int = 100,
.dtim_period = 1,
.bss_max_idle = 300,
.key_mgmt = WPA_KEY_MGMT_NONE,
.ipaddr = IP_ADDR_DEFAULT,
.netmask = NET_MASK_DEFAULT,
.gw_ip = GW_IP_DEFAULT,
.dhcpd_startip = DHCP_START_IP_DEFAULT,
.dhcpd_endip = DHCP_END_IP_DEFAULT,
.dhcpd_lease_time = 3600,
.dhcpd_en = 1,
.dhcpc_en = 1,
.ble_pair_status = 0,//ble 默认是0,没有配网,设置为1的时候,代表已经配过网络
.wireless_paircode = 0,
.net_pair_switch = 0,
};
uint32 syscfg_key_mgmt_get(void){
return (sys_cfgs.key_mgmt != WPA_KEY_MGMT_NONE);
}
int32 syscfg_save(void)
{
return syscfg_write(&sys_cfgs, sizeof(sys_cfgs));
}
void syscfg_save_AP_msg(uint8_t *bssid,uint8_t station_channel,struct ieee80211_bss_wpadata *bss_data)
{
//原来参数一样,需要重新保存
if(memcmp(bssid,sys_cfgs.bssid,6) == 0 && station_channel == sys_cfgs.station_channel && memcmp(bss_data,&sys_cfgs.bss_data,sizeof(struct ieee80211_bss_wpadata)) == 0)
{
return;
}
else
{
memcpy(sys_cfgs.bssid,bssid,6);
sys_cfgs.station_channel = station_channel;
memcpy(&sys_cfgs.bss_data,bss_data,sizeof(struct ieee80211_bss_wpadata));
syscfg_save();
return;
}
}
extern uint8 sta_ps[8][6];
void syscfg_dump(void)
{
_os_printf("SYSCFG\r\n");
_os_printf(" mode:%s, channel:%d, key_mgmt:%x\r\n",
SYSCFG_WIFI_MODE(sys_cfgs.wifi_mode), sys_cfgs.channel, sys_cfgs.key_mgmt);
_os_printf(" bssid:"MACSTR", mac:"MACSTR"\r\n", MAC2STR(sys_cfgs.bssid), MAC2STR(sys_cfgs.mac));
_os_printf(" ssid:%s, passwd:%s\r\n", sys_cfgs.ssid, sys_cfgs.passwd);
_os_printf(" bss_max_idle:%d, beacon_int:%d, ack_tmo:%d, dtim_period:%d\r\n",
sys_cfgs.bss_max_idle, sys_cfgs.beacon_int, sys_cfgs.ack_tmo, sys_cfgs.dtim_period);
}
#ifdef CONFIG_UMAC4
void qc_wifi_config(void)
{
wifi_create_station(QC_STA_NAME,QC_STA_PW,WPA_KEY_MGMT_PSK);
}
int32 wifi_qc_scan(uint8 ifidx)
{
int32 ret = 0;
uint8 bss_num = 0;
uint8 *bss_data;
struct hgic_bss_info* bss_map;
struct ieee80211_scandata scan_param;
bss_data = malloc(32*sizeof(struct hgic_bss_info));
scan_param.chan_bitmap = QC_SCAN_CHANNEL;
scan_param.scan_time = QC_SCAN_TIME;
scan_param.scan_cnt = QC_SCAN_CNT;
ieee80211_scan(ifidx,1,&scan_param);
//ieee80211_scan(ifidx,0,NULL);
os_sleep_ms(QC_SCAN_TIME*QC_SCAN_CNT+10);
ret = ieee80211_get_bsslist((struct hgic_bss_info *)bss_data, 32, 1);
for (bss_num = 0;bss_num < 32;bss_num++) {
bss_map = (struct hgic_bss_info *)(bss_data + bss_num*sizeof(struct hgic_bss_info));
os_printf("[%d]===>%s\r\n",bss_num,bss_map->ssid);
if (! strcasecmp( (const char *)bss_map->ssid, QC_STA_NAME ) ) {
free(bss_data);
return 1;
}
}
free(bss_data);
return 0;
}
int get_rssi_msg(uint8_t *sta,char* ifname)
{
int ret = - 70;
struct ieee80211_stainfo stainfo;
if(sys_cfgs.wifi_mode == WIFI_MODE_STA) {
ret = ieee80211_conf_get_stainfo(WIFI_MODE_STA,0,NULL,&stainfo);
if (ret == 0) {
ret = stainfo.rssi;
} else {
ret = -70;
}
}
return ret;
}
void wifi_create_ap(char *ssid,char *password,int key_mode,int channel)
{
uint8 key[32];
ieee80211_conf_set_channel(WIFI_MODE_AP, channel);
ieee80211_conf_set_ssid(WIFI_MODE_AP, (uint8*)ssid);
ieee80211_conf_set_keymgmt(WIFI_MODE_AP, key_mode);
if (key_mode != WPA_KEY_MGMT_NONE) {
wpa_passphrase((uint8*)ssid, password, key);
ieee80211_conf_set_psk(WIFI_MODE_AP, key);
ieee80211_conf_set_passwd(WIFI_MODE_AP, password);
}
}
void wifi_create_station(char *ssid,char *password,int key_mode)
{
uint8 key[32];
ieee80211_conf_set_ssid(WIFI_MODE_STA, (uint8*)ssid);
ieee80211_conf_set_keymgmt(WIFI_MODE_STA, key_mode);
if (key_mode != WPA_KEY_MGMT_NONE) {
wpa_passphrase((uint8*)ssid, password, key);
ieee80211_conf_set_psk(WIFI_MODE_STA, key);
ieee80211_conf_set_passwd(WIFI_MODE_STA, password);
}
}
int32 wificfg_flush(uint8 ifidx)
{
ieee80211_conf_set_mac(ifidx, sys_cfgs.mac);
//station的时候,全信道扫描
if(WIFI_MODE_STA == ifidx)
{
if(sys_cfgs.station_channel)
{
ieee80211_bss_add_manualAP(sys_cfgs.ssid,sys_cfgs.bssid,sys_cfgs.station_channel,IEEE80211_BAND_2GHZ,&sys_cfgs.bss_data);
}
ieee80211_conf_set_channel(ifidx, 0);
}
else
{
ieee80211_conf_set_channel(ifidx, sys_cfgs.channel);
}
ieee80211_conf_set_beacon_int(ifidx, sys_cfgs.beacon_int);
ieee80211_conf_set_dtim_int(ifidx, sys_cfgs.dtim_period);
ieee80211_conf_set_bss_max_idle(ifidx, sys_cfgs.bss_max_idle);
ieee80211_conf_set_ssid(ifidx, sys_cfgs.ssid);
ieee80211_conf_set_keymgmt(ifidx, sys_cfgs.key_mgmt);
ieee80211_conf_set_psk(ifidx, sys_cfgs.psk);
ieee80211_conf_set_passwd(ifidx, sys_cfgs.passwd);
ieee80211_conf_set_psdata_cnt(ifidx,40);
if(ifidx == WIFI_MODE_AP){
if(sys_cfgs.channel==0 && sys_status.channel){
ieee80211_conf_set_channel(ifidx, sys_status.channel);
}else{
ieee80211_conf_set_channel(ifidx, sys_cfgs.channel);
}
}
return 0;
}
void sta_ps_mode_enter(uint16 aid)
{
}
void sta_ps_mode_exit(uint16 aid)
{
}
void aid_to_mac(uint16 aid, uint8* mac)
{
struct ieee80211_stainfo stainfo;
ieee80211_conf_get_stainfo(WIFI_MODE_AP,aid,NULL,&stainfo);
memcpy(mac,stainfo.addr,6);
}
#else
//hgics configs.
struct umac_config umac_cfg;
struct umac_config *sys_get_umaccfg()
{
struct umac_config *cfg = &umac_cfg;
int hg0_sz = 0;
uint8 channel = 0 ;
cfg->bss_bw = 8;
cfg->tx_mcs = 7;
cfg->primary_chan = 1;
cfg->chan_cnt = 2;
cfg->chan_list[0] = 9020;
cfg->chan_list[1] = 9100;
if (sys_cfgs.wifi_mode == WIFI_MODE_STA) {
hg0_sz += (int)os_sprintf(cfg->hg0, "update_config=1\n" \
"network={\n" \
"proto=WPA RSN\n"\
"key_mgmt=WPA-PSK\n" \
"pairwise=TKIP CCMP\n" \
"group=TKIP CCMP\n" \
);
hg0_sz += (int)os_sprintf(&cfg->hg0[hg0_sz], "ssid=\"%s\"\n", "BGN_test");
hg0_sz += (int)os_sprintf(&cfg->hg0[hg0_sz], "psk=\"%s\"\n", "12345678");
hg0_sz += (int)os_strcpy(&cfg->hg0[hg0_sz], "}\n");
_os_printf("cfg->hg0:%s\r\n", cfg->hg0);
} else {
hg0_sz += (int)os_sprintf(cfg->hg0, "country_code=CN\n");
hg0_sz += (int)os_sprintf(&cfg->hg0[hg0_sz], "ssid=%s\n", sys_cfgs.ssid);
if (sys_cfgs.channel == 0) {
} else {
channel = sys_cfgs.channel;
}
hg0_sz += (int)os_sprintf(&cfg->hg0[hg0_sz], "channel=%d\n", channel);
if (sys_cfgs.key_mgmt == WPA_KEY_MGMT_NONE) {
hg0_sz += (int)os_strcpy(&cfg->hg0[hg0_sz],
"wpa=0\n" \
"hw_mode=g\n"\
);
} else {
hg0_sz += (int)os_sprintf(&cfg->hg0[hg0_sz], "wpa_passphrase=%s\n", sys_cfgs.key);
hg0_sz += (int)os_strcpy(&cfg->hg0[hg0_sz],
"wpa=2\n" \
"wpa_key_mgmt=WPA-PSK\n" \
"wpa_pairwise=CCMP\n" \
"hw_mode=g\n"\
"ieee80211n=1\n" \
"ht_capab=\n"\
);
}
}
return cfg;
}
//save hgics configs into system.
int sys_save_umaccfg(struct umac_config *cfg)
{
return 0;
}
void sta_ps_mode_enter(char *addr)
{
}
void sta_ps_mode_exit(char *addr)
{
}
void aid_to_mac(uint16 aid, uint8* mac)
{
}
#endif
void syscfg_set_default_val()
{
sysctrl_efuse_mac_addr_calc(sys_cfgs.mac);
if (IS_ZERO_ADDR(sys_cfgs.mac)) {
os_random_bytes(sys_cfgs.mac, 6);
sys_cfgs.mac[0] &= 0xfe;
os_printf("use random mac "MACSTR"\r\n", MAC2STR(sys_cfgs.mac));
}
os_sprintf(sys_cfgs.ssid,"%s%02x%02x%02x",SSID_DEFAULT,sys_cfgs.mac[5],sys_cfgs.mac[4],sys_cfgs.mac[3]);
os_sprintf(sys_cfgs.passwd,"%s","12345678");
#ifdef CONFIG_UMAC4
wpa_passphrase(sys_cfgs.ssid, sys_cfgs.passwd, sys_cfgs.psk);
#else
os_strcpy(sys_cfgs.key, "12345678");
#endif
}
uint8 get_sys_cfgs_ble_pair_status()
{
return sys_cfgs.ble_pair_status;
}
#ifdef CONFIG_SLEEP
int32 wificfg_set_wkupdata_mask(uint8 ifidx, uint8 offset, uint8 *mask, uint32 mask_len)
{
uint8 len = mask_len > (LMAC_WKDATA_SIZE/8) ? (LMAC_WKDATA_SIZE/8) : mask_len;
struct lmac_wkdata_param *wkdata = sys_sleepdata_request(SYSTEM_SLEEPDATA_ID_WKDATA, sizeof(
struct lmac_wkdata_param));
os_printf("%s:%d\r\n", __func__, __LINE__);
if(wkdata){
wkdata->count = LMAC_WKDATA_COUNT;
wkdata->wkdata_size = LMAC_WKDATA_SIZE;
wkdata->data[0].offset = offset;//offset from ether hdr
os_memset(wkdata->data[0].mask, 0, sizeof(wkdata->data[0].mask));
os_memcpy(wkdata->data[0].mask, mask, len);
os_printf(KERN_NOTICE"set wkdata mask, offset=%d \r\n", wkdata->data[0].offset);
return RET_OK;
}
return -ENOTSUPP;
}
int32 wificfg_set_wakeup_data(uint8 ifidx, uint8 *data, uint32 data_len)
{
uint8 len = data_len > LMAC_WKDATA_SIZE ? LMAC_WKDATA_SIZE : data_len;
struct lmac_wkdata_param *wkdata = sys_sleepdata_request(SYSTEM_SLEEPDATA_ID_WKDATA, sizeof(
struct lmac_wkdata_param));
os_printf("%s:%d\r\n", __func__, __LINE__);
if(wkdata){
wkdata->count = LMAC_WKDATA_COUNT;
wkdata->wkdata_size = LMAC_WKDATA_SIZE;
wkdata->data[0].wkdata_len = len;
os_memcpy(wkdata->data[0].wkdata, data, len);
os_printf(KERN_NOTICE"set wkdata, len=%d \r\n", len);
return RET_OK;
}
return -ENOTSUPP;
}
int32 wificfg_set_wkdata_svr_ip(uint8 ifidx, uint32 svr_ip)
{
struct lmac_wkdata_param *wkdata = sys_sleepdata_request(SYSTEM_SLEEPDATA_ID_WKDATA, sizeof(
struct lmac_wkdata_param));
os_printf("%s:%d\r\n", __func__, __LINE__);
if(wkdata){
wkdata->count = LMAC_WKDATA_COUNT;
wkdata->wkdata_size = LMAC_WKDATA_SIZE;
wkdata->data[0].sip = svr_ip;
os_printf(KERN_NOTICE"set wkdata sip="IPSTR"\r\n", IP2STR_N(svr_ip));
return RET_OK;
}
return -ENOTSUPP;
}
#endif
project/syscfg.h
+73
View File
@@ -0,0 +1,73 @@
#ifndef _PROJECT_SYSCFG_H_
#define _PROJECT_SYSCFG_H_
#include "lib/umac/ieee80211.h"
#define CFG_VERSION_NUM 0x0103
enum WIFI_WORK_MODE {
WIFI_MODE_NONE = 0,
WIFI_MODE_STA,
WIFI_MODE_AP,
WIFI_MODE_APSTA,
};
struct system_status {
uint32 dhcpc_done: 1,
wifi_connected: 1,
dbg_heap: 1,
dbg_top: 2,
dbg_lmac: 1,
dbg_umac: 1,
dbg_irq: 1,
reset_wdt: 1,
upgrading: 1,
pair_success: 1;
uint8 channel;
};
struct sys_config {
uint16 magic_num, crc;
uint16 size, cfg_ver, rev2;
///////////////////////////////////////
uint8 wifi_hwmode, default_wifi_mode;
uint8 wifi_mode, bss_bw, tx_mcs, channel;
uint8 bssid[6], mac[6];
uint8 ssid[32];
uint8 psk[32];
char passwd[PASSWD_MAX_LEN+1];
uint16 bss_max_idle, beacon_int;
uint16 ack_tmo, dtim_period;
uint32 key_mgmt;
uint32 dhcpc_en:1, dhcpd_en:1, ap_hide:1, xxxxxx: 29;
uint32 ipaddr, netmask, gw_ip;
uint32 dhcpd_startip, dhcpd_endip, dhcpd_lease_time;
uint32 user_param1,user_param2;
uint32 dsleep_test_cfg[4];
uint16 wireless_paircode;
struct ieee80211_bss_wpadata bss_data;
uint8 ble_pair_status;
uint8 net_pair_switch;
uint8 station_channel;
};
extern struct sys_config sys_cfgs;
extern struct system_status sys_status;
void syscfg_set_default_val(void);
int32 wificfg_flush(uint8 ifidx);
void syscfg_check(void);
void syscfg_dump(void);
uint8 get_sys_cfgs_ble_pair_status();
void wifi_create_station(char *ssid,char *password,int key_mode);
void wifi_create_ap(char *ssid,char *password,int key_mode,int channel);
void syscfg_save_AP_msg(uint8_t *bssid,uint8_t station_channel,struct ieee80211_bss_wpadata *bss_data);
#endif
project/syscfg_factory.h
+28
View File
@@ -0,0 +1,28 @@
#ifndef __SYSCFG_FACTORY_H__
#define __SYSCFG_FACTORY_H__
#ifdef SYS_FACTORY_PARAM_SIZE
extern const uint16_t sys_factory_param[SYS_FACTORY_PARAM_SIZE / 2];
#endif
struct syscfg_fact {
uint16_t wnb_chan_list[16];
uint8_t wnb_bss_bw, wnb_tx_mcs, wnb_encrypt, wnb_forward;
uint16_t wnb_freq_start, wnb_freq_end;
uint32_t wnb_customer_id;
uint16_t wnb_ether_type;
uint8_t wnb_tx_power;
};
static inline struct syscfg_fact *syscfg_fact_params(void)
{
#ifdef SYS_FACTORY_PARAM_SIZE
ASSERT(sizeof(struct syscfg_fact) <= (SYS_FACTORY_PARAM_SIZE - 4));
if (sys_factory_param[1] == 0x1a2b) {
return (struct syscfg_fact *)(&sys_factory_param[2]);
}
#endif
return NULL;
}
#endif
project/utilities/aft_build.sh
+9
View File
@@ -0,0 +1,9 @@
#!/bin/bash
cp -f ./Obj/txw4101.ihex project.hex
cp -f ../../../../../tools/makecode/BinScript.exe BinScript.exe
cp -f ../../../../../tools/makecode/crc.exe crc.exe
cp -f ../../../../../tools/makecode/makecode.exe makecode.exe
BinScript.exe BinScript.BinScript
makecode.exe
project/utilities/flashinit
+20
View File
@@ -0,0 +1,20 @@
# See More In CDK help
#
# download bin [verify=yes/no] address=hex number <filename>
# [verify=yes/no]：选择是否对download的文件进行verify操作；可选，如果不写，则默认使用工程配置中的Flash配置中的Verify选项的值
# address：设置bin文件烧录的起始地址，必须为16进制数据；
# <filename>：文件名称，这里支持CDK的内部变量格式的写法；
#
set *(unsigned int *)0x40013004=0xdddd
set *(unsigned int *)0x4002602C=0x3fac87e4
set *(unsigned int *)0x40020008=0x00000000
set *(unsigned int *)0x40020008=0x00000000
set *(unsigned int *)0x40020008=0xFFFFFFFF
set *(unsigned int *)0x40020188=0x00000000
#set $psr=0x80000000
##download
download bin verify=yes address=0 $(ProjectPath)APP.bin
project/utilities/gcc_csky.ld
+297
View File
@@ -0,0 +1,297 @@
/*
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/******************************************************************************
* @file gcc_csky.ld
* @brief csky linker file
* @version V1.0
* @date 02. June 2017
******************************************************************************/
MEMORY
{
SRAM0 : ORIGIN = 0x20041000 , LENGTH = 0x2c00 /*SRAM0 16 - 4KB - 1k*/
SRAM : ORIGIN = 0x20000004 , LENGTH = 0x3fffc /* on-chip SRAM 288KB */
/* SRAM : ORIGIN = 0x38000000 , LENGTH = 0x400000 */
FLASH : ORIGIN = 0x18000000 , LENGTH = 0x200000
PSRAM : ORIGIN = 0x38000000 , LENGTH = 0x400000
}
__heap_size = 0x11000;
PROVIDE (__ram_end = 0x20040000);
PROVIDE (__heap_end = 0x20040000);
PROVIDE (__sleep_data_start = 0x20040004);
PROVIDE (__sleep_data_stop = 0x20040a00);
PROVIDE (__psram_heap_end = 0x38400000);
REGION_ALIAS("REGION_TEXT", FLASH);
REGION_ALIAS("REGION_RODATA", FLASH);
REGION_ALIAS("REGION_DATA", SRAM);
REGION_ALIAS("REGION_BSS", SRAM);
REGION_ALIAS("REGION_INIT", SRAM);
REGION_ALIAS("REGION_PSRAM_HEAP", PSRAM);
REGION_ALIAS("REGION_NOLOAD_PSRAM", PSRAM);
REGION_ALIAS("REGION_DATA2", SRAM);
REGION_ALIAS("REGION_OTA_VMA", SRAM);
REGION_ALIAS("REGION_TEXT2", SRAM);
REGION_ALIAS("REGION_DSLEEP", SRAM0);
ENTRY(Reset_Handler)
SECTIONS
{
.text : AT(ADDR(.text)) {
. = ALIGN(0x4) ;
__code_start = .;
KEEP(*startup.o(.vectors))
KEEP(*(SYS_PARAM))
__stext = . ;
*(.text)
*(.text*)
*(.text.*)
*(INIT.TXT)
*(INIT.TXT.*)
*(.gnu.warning)
*(.stub)
*(.gnu.linkonce.t*)
*(.glue_7t)
*(.glue_7)
*(.jcr)
KEEP (*(.init*))
KEEP (*(.fini))
. = ALIGN (4) ;
PROVIDE(__ctbp = .);
*(.call_table_data)
*(.call_table_text)
. = ALIGN(0x10) ;
__etext = . ;
} > REGION_TEXT
.rodata : {
. = ALIGN(0x4) ;
__srodata = .;
*(.rdata)
*(.rdata*)
*(.rdata1)
*(.rdata.*)
*(.rodata)
*(.rodata1)
*(.rodata*)
*(.rodata.*)
*(.rodata.str1.4)
*(INIT.RO)
*(INIT.RO.*)
. = ALIGN(0x4) ;
__modver_start = .;
KEEP(*(.modver))
__modver_end = .;
. = ALIGN(0x4) ;
__CTOR_LIST__ = . ;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
KEEP(*(SORT(.ctors)))
LONG(0)
__CTOR_END__ = . ;
__DTOR_LIST__ = . ;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
KEEP(*(SORT(.dtors)))
LONG(0)
__DTOR_END__ = . ;
. = ALIGN(0x4) ;
} > REGION_RODATA
.dsleep : {
__data0_start__ = . ;
__dsleep_start = .;
*(.dsleep.*)
. = ALIGN(0x4) ;
__dsleep_end = .;
__data0_end__ = . ;
} > REGION_DSLEEP AT>REGION_RODATA
_data0_lma_start = LOADADDR(.dsleep);
_data0_lma_end = LOADADDR(.dsleep) + SIZEOF(.dsleep);
.data : {
. = ALIGN(0x04) ;
__sdata = . ;
__data_start__ = . ;
data_start = . ;
*(INIT.DAT)
*(INIT.DAT.*)
*(.got.plt)
*(.got)
*(.gnu.linkonce.r*)
*(.bobj)
*(.data)
*(.data*)
*(.data1)
*(.data.*)
*(.gnu.linkonce.d*)
*(.data1)
*(.gcc_except_table)
*(.gcc_except_table*)
__start_init_call = .;
*(.initcall.init)
__stop_init_call = .;
__start_cmd = .;
*(.bootloaddata.cmd)
. = ALIGN(4) ;
__stop_cmd = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(__libc_atexit)
*(__libc_subinit)
*(__libc_subfreeres)
*(.note.ABI-tag)
*(.ram.text)
. = ALIGN(0x4) ;
__edata = .;
__data_end__ = .;
} > REGION_DATA AT>REGION_RODATA
_data_lma_start = LOADADDR(.data);
_data_lma_end = LOADADDR(.data) + SIZEOF(.data);
.no_init (NOLOAD) : {
*(.irq_stack);
*(.trap_stack);
*(.no_init);
} > REGION_BSS
.ota : {
. = ALIGN(0x4) ;
_ota_vma_start = . ;
KEEP (*(.otacode))
_ota_vma_end = . ;
} > REGION_OTA_VMA AT > REGION_RODATA
_ota_lma_start = LOADADDR(.ota);
_ota_lma_end = LOADADDR(.ota) + SIZEOF(.ota);
.iis : AT(LOADADDR(.ota) + SIZEOF(.ota)) {
. = ALIGN(0x4) ;
iis_start = .;
KEEP (*(.iiscode))
} > REGION_OTA_VMA
_iis_start = LOADADDR(.iis);
_iis_end = LOADADDR(.iis) + SIZEOF(.iis);
__code_end = LOADADDR(.iis) + SIZEOF(.iis);
.bss : {
. = ALIGN(0x4) ;
__sbss = ALIGN(0x4) ;
__bss_start__ = . ;
*(.dynsbss)
*(.sbss.ota)
*(.sbss)
*(.sbss.*)
*(.scommon)
*(.dynbss)
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(0x4) ;
__ebss = . ;
__end = . ;
end = . ;
__bss_end__ = .;
} > REGION_BSS
._user_heap : {
. = ALIGN(0x4) ;
__heap_start = .;
} > REGION_BSS
._pdata_w (NOLOAD): {
*(.psram.data)
*(.psram.src)
} > REGION_NOLOAD_PSRAM
.psram_heap : {
. = ALIGN(0x16) ;
__psram_heap_start = .;
} > REGION_PSRAM_HEAP
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > REGION_BSS
.gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } > REGION_BSS
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
.gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
.eh_frame_hdr : { *(.eh_frame_hdr) }
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
}
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
}
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
PROVIDE_HIDDEN (__fini_array_end = .);
}
.junk 0 : { *(.rel*) *(.rela*) }
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.debug_pubtypes 0 : { *(.debug_pubtypes) }
.debug_ranges 0 : { *(.debug_ranges) }
.gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}
/* ROM Functions */
/* ASSERT(DEFINED(ROM_FUNC_ENABLE), "please disable ROM Functions in ld file") */
/* ASSERT(ADDR(.text) < 0x20000068, "ROM Functions data area conflict!!!")*/
INPUT(romcode.ld)
project/utilities/gcc_csky_qspiboot.ld
+193
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/*
* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/******************************************************************************
* @file gcc_csky.ld
* @brief csky linker file
* @version V1.0
* @date 02. June 2017
******************************************************************************/
MEMORY
{
I-SRAM : ORIGIN = 0x0 , LENGTH = 0x80000 /* I-SRAM 128KB */
D-SRAM : ORIGIN = 0x20000000 , LENGTH = 0x80000 /* D-SRAM 512KB */
O-SRAM : ORIGIN = 0x50000000 , LENGTH = 0x800000 /* off-chip SRAM 8MB */
FLASH : ORIGIN = 0x18000000 , LENGTH = 0x200000 /* MCP FLASH 2MB */
SRAM : ORIGIN = 0x20002000 , LENGTH = 0x46000 /* on-chip SRAM 288KB */
LMAC_BUF : ORIGIN = 0x20051000 , LENGTH = 18*1024 /* on-chip SRAM 18KB */
}
__heap_size = 0x11000;
PROVIDE (__ram_end = 0x20048000);
PROVIDE (__heap_end = 0x20048000);
REGION_ALIAS("REGION_TEXT", FLASH);
REGION_ALIAS("REGION_RODATA", FLASH);
REGION_ALIAS("REGION_DATA", SRAM);
REGION_ALIAS("REGION_BSS", SRAM);
ENTRY(Reset_Handler)
SECTIONS
{
.text : AT(ADDR(.text)) {
. = ALIGN(0x4) ;
KEEP(*startup.o(.vectors))
KEEP(*(SYS_PARAM))
*(.dsleep_data)
__stext = . ;
*(.text)
*(.text*)
*(.text.*)
*(.gnu.warning)
*(.stub)
*(.gnu.linkonce.t*)
*(.glue_7t)
*(.glue_7)
*(.jcr)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN (4) ;
PROVIDE(__ctbp = .);
*(.call_table_data)
*(.call_table_text)
. = ALIGN(0x10) ;
__etext = . ;
} > REGION_TEXT
.rodata : {
. = ALIGN(0x4) ;
__srodata = .;
*(.rdata)
*(.rdata*)
*(.rdata1)
*(.rdata.*)
*(.rodata)
*(.rodata1)
*(.rodata*)
*(.rodata.*)
*(.rodata.str1.4)
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
. = ALIGN(0x4) ;
__erodata = .;
} > REGION_RODATA
.data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)){
. = ALIGN(0x4) ;
__sdata = . ;
__data_start__ = . ;
data_start = . ;
*(.got.plt)
*(.got)
*(.gnu.linkonce.r*)
*(.data)
*(.data*)
*(.data1)
*(.data.*)
*(.gnu.linkonce.d*)
*(.data1)
*(.gcc_except_table)
*(.gcc_except_table*)
__start_init_call = .;
*(.initcall.init)
__stop_init_call = .;
__start_cmd = .;
*(.bootloaddata.cmd)
. = ALIGN(4) ;
__stop_cmd = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
*(__libc_atexit)
*(__libc_subinit)
*(__libc_subfreeres)
*(.note.ABI-tag)
. = ALIGN(0x4) ;
__edata = .;
__data_end__ = .;
} > REGION_DATA
__dsleep_ro_start__ = LOADADDR(.rodata) + SIZEOF(.rodata) + SIZEOF(.data);
.dsleep : AT(__dsleep_ro_start__) {
__dsleep_code_start__ = .;
KEEP(*(.dsleep_vector))
*(.dsleep_txt)
*(.lmac_dsleep_txt)
*(.wphy_dsleep_txt)
*(.rf_digicali_dsleep_txt)
__dsleep_code_end__ = .;
} > LMAC_BUF
.dsleep_buf (NOLOAD) : {
*(.dsleep_stack)
*(.lmac_dsleep_data)
*(.wphy_dsleep_data)
*(.rf_digicali_dsleep_data)
} > LMAC_BUF
/* 当.dsleep的代码是放到sram，则在bss之前需要预留.dsleep加载代码的空间 */
.fill_dsleep_code (NOLOAD) : {
. = . + (((__dsleep_ro_start__ & 0x20000000) == 0x20000000) ? SIZEOF(.dsleep) : 0);
} > REGION_DATA
.no_init (NOLOAD) : {
*(.stack);
*(.no_init);
} > REGION_BSS
.bss : {
. = ALIGN(0x4) ;
__sbss = ALIGN(0x4) ;
__bss_start__ = . ;
*(.dynsbss)
*(.sbss)
*(.sbss.*)
*(.scommon)
*(.dynbss)
*(.bss)
*(.bss.*)
*(COMMON)
. = ALIGN(0x4) ;
__ebss = . ;
__end = . ;
end = . ;
__bss_end__ = .;
} > REGION_BSS
._user_heap : {
. = ALIGN(0x4) ;
__heap_start = .;
} > REGION_BSS
._pdata_w 0x28800000 (NOLOAD): {
*(.psram.src)
}
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}
/* ROM Functions */
/* ASSERT(DEFINED(ROM_FUNC_ENABLE), "please disable ROM Functions in ld file") */
/* ASSERT(ADDR(.text) < 0x20000068, "ROM Functions data area conflict!!!")*/
/* INPUT(romcode.ld) */
project/utilities/gdb.init
+2
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# watchdog close : WDT->WDTKEY
set *(unsigned int *)0x40015004=0xdddd
project/utilities/gdb_flash_24Mhz.init
+76
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#set breakpoint always-inserted on
# watchdog close : WDT->WDTKEY
set *(unsigned int *)0x40015004=0xdddd
# sysctrl writable : SYSCTRL->SYS_KEY
set *(unsigned int *)0x40020000=0x3fac87e4
# sysclk = osc : SYSCTRL->CLK_CON0
set *(unsigned int *)0x40020044=0x00000009
set *(unsigned int *)0x40020048=0x00000000
# ROM Writable : SYSCTRL->SYS_CON3[4]
set *(unsigned int *)0x40020010=0x08000010
#set *(unsigned int *)0x00000000=0x180000E8
# MONITOR disable : SYSMNT CTRL
set *(unsigned int *)0x40021300=0x0
set *(unsigned int *)0x40021308=0x1
# CQSPI IO MAP: GPIOB->PUPL/H
set *(unsigned int *)0x40020B10=0x00111111
set *(unsigned int *)0x40020B14=0x00000000
# CQSPI IO MAP : GPIOB->MODE
set *(unsigned int *)0x40020B00=0x00000000
# CQSPI IO MAP : SYSCTRL->QSPI_MAP_CON
set *(unsigned int *)0x40020184=0x00053A21
# QSPI clk(96Mhz source) : QSPI->CONFIG
#set *(unsigned int *)0x40000000=0x00F90081
set *(unsigned int *)0x40000000=0x80883881
# QSPI clk(96Mhz source) : QSPI->CONFIG
#READ_DATA_CAPTURE
set *(unsigned int *)0x40000010=0x00000003
# QSPI DELAY: QSPI->DEV_DELAY
set *(unsigned int *)0x4000000C=0x02020202
# QSPI write protect low addr : QSPI->WRITE_PROT_L
set *(unsigned int *)0x40000050=0x00000000
# QSPI write protect high addr : QSPI->WRITE_PROT_H
set *(unsigned int *)0x40000054=0x00020000
# QSPI write protect enable : QSPI->WRITE_PROT_CTRL
set *(unsigned int *)0x40000058=0x0
# FLASH reset
set *(unsigned int *)0x40000090=0x66000001
set *(unsigned int *)0x40000090=0x99000001
# SPIFLASH write enable : QSPI->FLASH_CMD_CTRL
set *(unsigned int *)0x40000090=0x06000001
# QUAL MODE enable : QSPI->FLASH_CMD_WDATA_L && QSPI->FLASH_CMD_CTRL
set *(unsigned int *)0x400000A8=0x0200
set *(unsigned int *)0x40000090=0x01009001
# QSPI DUAL MODE : QSPI->DEV_RDINSTR_CONFIG
#set *(unsigned int *)0x40000004=0x0801003B
# QSPI QUAL MODE : QSPI->DEV_RDINSTR_CONFIG
set *(unsigned int *)0x40000004=0x0802006B
#READ_DATA_CAPTURE_EXT
# QSPI poll disable
#set *(unsigned int *)0x40000038=0x00014005
# QSPI WEL disable
#set *(unsigned int *)0x40000008=0x00000102
# scramble enable
#set *(unsigned int *)0x40020188=0x80000000
# chip erase : QSPI->FLASH_CMD_CTRL
#set *(unsigned int *)0x40000090=0xC7000001
# delay 4000ms
#shell sleep 7s
#shell ping -c 3 -w 5 android.xx.xxx.com
shell ping -c 10 -i 5 www.google.com
#softreset
#set $chr=0xabcd0009
set $pc=0x18000980
project/utilities/romcode.ld
+18
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memset = 0X00000584;
memcpy = 0X00000624;
memcmp = 0X000006A4;
strcasecmp = 0X0000232C;
strncasecmp = 0X00002370;
ll_qspi_xip_erase = 0X0000680C;
ll_qspi_xip_read = 0X00006854;
ll_qspi_xip_write = 0X00006898;
ll_qspi_xip_opt_enter = 0X00006728;
ll_qspi_xip_opt_exit = 0X0000679C;
ll_qspi_enter_xip_mode = 0X00006180;
ll_qspi_exit_xip_mode = 0X00006204;
ll_qspi_stig = 0X000060D8;
ll_ospi_psram_mrr = 0X00003798;
ll_ospi_psram_mrw = 0X0000380C;
ll_ospi_stig = 0X00003680;
qspi_flash_erase_handle = 0x00002d5c;
ll_qspi_cmd_busy_wait = 0x00006120;
project/utilities/romcode_fpga.ld
+82
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strcat = 0x000018ec;
strchr = 0x00001988;
strcmp = 0x00001668;
strcpy = 0x00001820;
memset = 0x00001740;
memcpy = 0x00001908;
memcmp = 0x0000199c;
memchr = 0x00001ae8;
strcasecmp = 0x00004b4c;
strncasecmp = 0x00004b90;
printf = 0x00001080;
puts = 0x000010b8;
strerror = 0x00002d48;
rand = 0x00001170;
srand = 0x0000118c;
abs = 0x00001290;
fabs = 0x000001a8;
atof = 0x0000150c;
atoi = 0x00001500;
atol = 0x000014f4;
strtol = 0x00001298;
strtoll = 0x00001518;
strtoul = 0x00001198;
strtoull = 0x000013b8;
strtof = 0x000014e8;
strtod = 0x00001b6c;
isupper = 0x00001b04;
isspace = 0x0000106c;
isdigit = 0x00001afc;
isalpha = 0x00001b0c;
SHA1Init = 0x0000ca60;
SHA1Transform = 0x0000bb4c;
SHA1Update = 0x0000ca90;
sha1_vector = 0x0000cbe4;
SHA1Final = 0x0000cb20;
sha256_init = 0x0000cd98;
sha256_done = 0x0000cea8;
sha256_vector = 0x0000cfa0;
sha256_process = 0x0000cde8;
MD5Init = 0x0000b9b0;
MD5Update = 0x0000b9d8;
md5_vector = 0x0000baf4;
MD5Final = 0x0000ba7c;
/**/
hgusb20_intr_dis = 0x00006b50;
hgusb20_int_init_b = 0x00006cdc;
hgusb20_clear_ep = 0x00006dec;
hgusb20_ep0_clrrx_pkt0 = 0x00006cac;
hgusb20_ep0_clr_feature = 0x00006f58;
hgusb20_stall_ep = 0x00006d6c;
hgusb20_ep0_get_status = 0x00006ee0;
hgusb20_ep0_set_feature = 0x00006f9c;
hgusb20_ep0_set_configuration = 0x00007210;
hgusb20_ep0_get_wcid_descriptor = 0x000072dc;
hgusb20_reset2device_mode = 0x00006ab4;
hgusb20_switch_stable_device = 0x00006b40;
hgusb20_ep_set_txrdy = 0x00007914;
hgusb20_ep0_tx = 0x00006c30;
hgusb20_ep_rx_kick = 0x00007814;
hgusb20_ep0_class = 0x000073a8;
hgusb20_ep0_set_address = 0x00007008;
hgusb20_ep_set_rxrdy = 0x00007910;
hgusb20_ep_tx_kick = 0x00007894;
hgusb20_ep0_transfer = 0x00007048;
hgusb20_ep0_descriptor = 0x000070cc;
tbl_usb_language_id = 0x0000df1c;
tbl_usb_str_manufacturer = 0x0000df20;
tbl_winusb_device_descriptor = 0x0000e05c;
tbl_winusb_compatible_id_feature_descriptor = 0x0000e034;
tbl_winusb20_wcidbos = 0x0000e010;
usb_test_packet = 0x0000de50;
usb_test_mode_tbl = 0x0000de48;
tbl_winusb20_wcid_descriptor_set = 0x0000df6c;
tbl_winusb_device_interface_guids = 0x0000e070;
tbl_usb_str_serial_number = 0x0000df4c;
tbl_usb_str_product = 0x0000df30;
tbl_usb_config_all_descriptor_wifi = 0x0000def0;
tbl_usb_config_all_descriptor_gen = 0x0000dee4;
tbl_usb_device_descriptor = 0x0000df08;
project/utilities/romcode_fpga_org.ld
+455
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ll_spi_init = 0x00007ce8;
ll_spi_rx = 0x00007ea8;
ll_uart_txdma_kick = 0x000069f0;
sdio_s_set_ds = 0x000038c8;
sys_aes_init = 0x00007c8c;
disable_wphy_device_cont_tx = 0x00006108;
config_wphy_device_dpd_coef = 0x0000627c;
sys_aes_key_bitlen_sel = 0x00007c68;
ll_simple_spi_init = 0x0000a5e4;
hgusb20_irq_dma = 0x000076b0;
fw_upg_addr = 0x2005247c;
crc16_modbus_calc = 0x00002ecc;
close_wphy = 0x0000ac68;
ll_iic_slave_rx = 0x00008208;
hgusb20_wifi_reset = 0x00007a08;
ll_crc_start = 0x00006a78;
ll_m2m_memcpy = 0x00008278;
os_critical_close = 0x00001b2c;
hgusb20_irq_set = 0x000075f4;
ll_sdio_s_tx_kick = 0x00009264;
uart_s_set_speed = 0x00004208;
get_wphy_device_avg_evm = 0x000060e0;
sdio_s_tx = 0x00003968;
config_phy_tx_norm_mode = 0x0000ad24;
get_wphy_device_gfsk_tx_crc = 0x00006340;
ll_wdt_feed = 0x00006450;
ll_timer_ir_enable = 0x00007be0;
ll_spi_buf_rx = 0x00007f50;
spiflash_boot = 0x00005e34;
ll_clock_syspll_config = 0x0000958c;
ll_clock_hirc_enable = 0x000092e4;
fw_upg_blk_addr = 0x20052480;
ll_uart_init = 0x000067dc;
spi_cfg = 0x0000dd6c;
config_phy_tx_sine_mode = 0x0000ace4;
ll_spi_config = 0x00007d04;
hgwphy_bgn_attach = 0x0000b044;
qspi_flash_port_deinit = 0x00004d4c;
usb20 = 0x2004768c;
ll_sys_clock_globle_set = 0x0000aab4;
ll_m2m_memset = 0x0000829c;
sdio_boot = 0x20052468;
ll_tk_stop = 0x0000a5d4;
hgusb20_dev_reset = 0x00006e98;
ll_gpio_iomap_output_config = 0x00006488;
get_wphy_device_rx_gain_para = 0x000062f0;
ll_sdio_s_irq_config = 0x000091d0;
ll_iic_master_tx = 0x0000810c;
ll_simple_uart_init = 0x0000a660;
ll_clock_set_sys_clk_src = 0x00009338;
ll_sys_clock_init = 0x0000aa70;
config_dpd = 0x0000ae68;
ll_gmac_get_tx_frame_status = 0x00008c28;
ll_qspi_controller_init = 0x00009198;
errno = 0x200524d0;
open_wphy = 0x0000aba0;
hgusb20_dev_init = 0x00006d04;
ll_qspi_set_prefetch = 0x000090ec;
ll_gpio_pull_config = 0x000065fc;
get_wphy_avg_evm = 0x0000ad5c;
ll_spi_dma_start = 0x00007df8;
uart_s_rx = 0x00004270;
CORE_SEC_OPT = 0x000092a0;
trig_calc_bk_noise = 0x0000af8c;
spi_boot = 0x20052674;
freq_offset_sign_ext = 0x0000b030;
sys_aes_start = 0x00007ca8;
ll_tk_ch_kick = 0x0000a5c8;
ll_iic_master_rx = 0x00008144;
spi_s_tx = 0x00003dd0;
enable_auto_sig_err_rst = 0x0000ae54;
qspi_flash_poweroff = 0x00004e1c;
fwinfo_check_fwinfo_hdr = 0x0000444c;
hgusb20_irq_handler_set = 0x000075d4;
ll_iic_master_buf_tx = 0x00008194;
ll_spi_dma_config = 0x00007dd0;
config_wphy_device_en_gfsk_wphy = 0x0000632c;
sys_aes_get_pending = 0x00007c78;
atcmd_fwupg = 0x0000d790;
ll_m2m_dma_init = 0x00008220;
fw_upg_prepare = 0x00004488;
spiflash_read = 0x00005a2c;
ll_qspi_set_write_protect = 0x000090ac;
ll_tk_config = 0x0000a4f4;
sys_aes_set_irq = 0x00007c2c;
ll_gmac_start = 0x00008600;
crc16_modbus_cfg = 0x0000d720;
ll_iis_disable = 0x00008408;
hgusb20_ep0_func = 0x00007468;
ll_clock_test_clk_en = 0x000092c4;
ll_iic_irq_config = 0x0000803c;
get_wphy_device_rx_gfsk_gain_para = 0x00006304;
ll_gpio_analog_config = 0x00006468;
hgusb20_dev_rx = 0x000047f4;
ll_suptmr_deinit = 0x00009e44;
ll_qspi_cmd_quad_enable = 0x00008df0;
crc32_calc = 0x00002ef0;
ll_gmac_init = 0x00008480;
qspi_flash_power_reset = 0x00004e44;
disable_wphy = 0x0000ab6c;
xmodem_receive = 0x00004a14;
ll_iic_master_buf_rx = 0x000081d8;
config_wphy_device_cca_th = 0x000061a0;
adj_gain_value = 0x0000ae78;
ll_gmac_send_frame = 0x000089f8;
ll_ir_timer_irq_config = 0x00007a78;
get_wphy_err_code = 0x0000ad68;
ll_led_timer_deinit = 0x00009d18;
uart_s_tx = 0x00004240;
ll_iis_soft_rst = 0x00008410;
stdout = 0x20052420;
boot = 0x200524d8;
ll_crc_init = 0x00006a14;
ll_spi_set_wire_mode = 0x00007e04;
get_wphy_device_gfsk_rx_crc = 0x00006358;
ll_simple_spi_deinit = 0x0000a5ec;
ll_gmac_irq_config = 0x0000857c;
config_phy_tx_waveform_mode = 0x0000b010;
ll_timer_deinit = 0x00007a14;
sdio_slave_init = 0x00003c5c;
enable_wphy_device = 0x00006090;
ll_crc_deinit = 0x00006a30;
usb_irq_ids = 0x200524a4;
ll_simple_uart_irq_config = 0x0000a678;
ll_clock_set_apb0_div = 0x00009370;
ll_timer_sync_start = 0x00007bf8;
sdio_port_init = 0x000039cc;
qspi_flash_deinit = 0x00004f90;
config_wphy_device_gfsk_crc_init = 0x00006370;
ll_spi_deinit = 0x00007cf8;
Te0 = 0x0000e7a8;
ll_qspi_cmd_enter_qpi_mode = 0x00008e68;
ll_ir_timer_config = 0x00007b54;
crc32_cfg = 0x0000d73c;
ll_spi_buf_tx = 0x00007ed0;
adj_gfsk_gain_value = 0x0000aeb4;
ll_gmac_config = 0x000084d0;
uart_s_set_ds = 0x00004220;
config_cca_th = 0x0000ae18;
cfg_wphy_gfsk_ch = 0x0000af7c;
hgusb20_irq = 0x00007714;
ll_uart_deinit = 0x000067f0;
spiflash_init = 0x00005820;
cfg_wphy_gfsk_crc_init = 0x0000af6c;
get_wphy_device_tx_psdu_crc = 0x00006218;
ll_suptmr_comm_config = 0x00009e5c;
spiflash_deinit = 0x0000592c;
spi_s_rx_len_exp = 0x20052478;
ll_gmac_setup_send_frame = 0x00008a74;
ll_gpio_iomap_input_config = 0x000064d8;
ll_iic_dma_config = 0x000080d0;
disable_rx_agc = 0x0000ade0;
disable_auto_sig_err_rst = 0x0000ae40;
disable_gfsk_wphy = 0x0000af20;
config_wphy_device_gfsk_ch = 0x00006384;
sdio_s_rx = 0x00003978;
ll_tk_sf_kick = 0x0000a5a8;
ll_spi_irq_config = 0x00007d78;
hgusb20_init = 0x000075a8;
sys_aes_set_mode = 0x00007c40;
adjust_wphy_device_gain_value = 0x000062a4;
ll_tk_deinit = 0x0000a4ac;
get_rx_freq_offset = 0x0000ad88;
config_phy_tx_tri_mode = 0x0000ad04;
config_wphy_device_tx_tri_mode = 0x000061c0;
hgusb20_bot_reset = 0x00006e5c;
sdio_rx_len_exp = 0x20052470;
Td0 = 0x0000e2a8;
ll_sdio_s_rx_kick = 0x00009294;
ll_led_timer_init = 0x00009d0c;
os_critical_enter = 0x00001b24;
fw_upg_program = 0x000044cc;
ll_timer_ir_set_code_0 = 0x00007bf0;
sdio_s_set_speed = 0x0000395c;
ll_gpio_pin_lock_config = 0x0000678c;
ll_clock_exosc_enable = 0x0000930c;
uart_s_xfer_done = 0x20052488;
soft_dereset_phy = 0x0000ab2c;
ll_timer_ir_disable = 0x00007be8;
sys_aes_set_block_num = 0x00007c20;
ll_uart_work_mode_change = 0x00006a00;
ll_qspi_cmd_device_reset = 0x00008f34;
stdin = 0x20052440;
ll_spi_tx = 0x00007e6c;
enable_rx_agc = 0x0000adf4;
ll_spi_set_clock_mode = 0x00007e40;
delay_ms_systick = 0x0000a9a8;
qspi_flash_port_init = 0x00004ca8;
ll_uart_dma_config = 0x000069b0;
ll_gmac_get_rx_frame_status = 0x00008c40;
enable_gfsk_wphy = 0x0000aef4;
SysTickCnt = 0x200524bc;
ll_gpio_iomap_inout_config = 0x00006578;
get_wphy_scrambler_init = 0x0000ad44;
enable_wphy_cont_tx = 0x0000ab70;
ll_timer_config = 0x00007ab8;
qspi_flash_init = 0x00004e74;
ll_iic_dma_start = 0x00008100;
ll_timer_irq_config = 0x00007a18;
ll_timer_start = 0x00007bd0;
ll_crc_stop = 0x00006aac;
ll_led_config = 0x00009b94;
hgusb20_wifi_init = 0x00007940;
ll_sdio_s_config = 0x000091d8;
sdio_interrupt_handle = 0x00003b98;
ll_led_timer_irq_config = 0x00009d94;
ll_qspi_set_clk = 0x00009124;
get_wphy_device_err_code = 0x00006130;
ll_iis_dma_config = 0x000083ec;
spi_base_pins = 0x0000dd34;
get_rx_gain_para = 0x0000ae90;
hgusb20_wifi_ep_init = 0x00007944;
qspi_flash_poweron = 0x00004df4;
ll_gmac_mdio_read = 0x00008830;
ll_crc_config = 0x00006a34;
hgusb20_ep0_clrrx_contious = 0x00006c80;
os_critical_exit = 0x00001b28;
ll_iis_config = 0x000082d8;
get_wphy_device_scrambler_init = 0x000060b0;
hgusb20_ep0_get_descriptor = 0x00007118;
ll_qspi_cmd_release_power_down = 0x00008f9c;
ll_gmac_mdio_write = 0x00008648;
adjust_wphy_device_gfsk_gain_value = 0x000062bc;
crc16_xmodem = 0x000049e4;
ll_timer_init = 0x00007a10;
disable_wphy_device = 0x000060a0;
crc8_calc = 0x00002ea8;
config_wphy_device_tx_sine_mode = 0x000061b0;
ll_tk_init = 0x0000a490;
delay_us = 0x0000a92c;
_ctype = 0x0000dc34;
ll_gmac_deinit = 0x00008544;
disable_wphy_cont_tx = 0x0000ab80;
enable_wphy_device_auto_sig_err_rst = 0x00006240;
ll_gmac_stop = 0x00008610;
disable_wphy_device_auto_sig_err_rst = 0x00006254;
rijndaelKeySetupEnc = 0x0000d034;
get_tx_psdu_crc16 = 0x0000ab64;
ll_iic_slave_tx = 0x00008214;
config_wphy_rx_max_gain_state = 0x00006190;
ll_suptmrx_config = 0x00009f9c;
ll_m2m_dma_config = 0x00008264;
ll_m2m_dma_irq_config = 0x00008268;
ll_uart232_config = 0x00006878;
delay_ms = 0x0000a94c;
hgusb20_ep0_request = 0x00007424;
ll_wdt_stop = 0x00006458;
close_wphy_device = 0x0000600c;
open_wphy_device = 0x00005ffc;
uart_s_boot = 0x0000452c;
hgusb20_dev_tx = 0x000047d0;
atcmd_bootl = 0x0000d788;
cp_mode = 0x00002e70;
get_wphy_device_rx_freq_offset = 0x000062d8;
soft_reset_wphy_device = 0x000061e0;
config_wphy_device_dpd = 0x00006268;
soft_dereset_wphy_device = 0x000061f0;
ll_wdt_start = 0x00006440;
ll_wdt_config = 0x000063f0;
ll_suptmr_init = 0x00009df8;
ll_uart_rxdma_kick = 0x000069e0;
ll_clock_sys_clk_select = 0x000093a0;
Td4s = 0x0000e6a8;
get_wphy_device_tx_crc = 0x00006118;
sdio_s_func1_cis = 0x200475d0;
ll_clock_test_clk_sel = 0x000092d0;
spi_s_set_speed = 0x00003e44;
ll_iis_init = 0x000082c0;
ll_iic_init = 0x00007fbc;
config_wphy_device_low_pwr_th = 0x00006230;
ll_iic_deinit = 0x00007fc8;
ll_iis_irq_config = 0x000083c4;
ll_iis_deinit = 0x000082cc;
sys_clock_cfg = 0x200524a8;
flash_memory_init = 0x00004348;
cfg_phy_tx_gain = 0x0000ac5c;
ll_gmac_allow_send_frame = 0x000089e4;
ll_gpio_afio_config = 0x00006594;
ll_m2m_dma_deinit = 0x00008258;
ll_gpio_ospeed_config = 0x000067a4;
ll_wdt_deinit = 0x00006430;
os_critical_open = 0x00001b20;
sys_aes_set_key = 0x00007c0c;
hgusb20_config_desc_prepare = 0x00006b68;
dev_register = 0x00006398;
ll_led_init = 0x00009b6c;
get_wphy_avg_power = 0x0000ad50;
stderr = 0x20052400;
ll_ir_timer_dma_config = 0x00007ba0;
ll_clock_usb_clk_en = 0x000096e8;
ll_timer_stop = 0x00007bd8;
ll_qspi_cmd_busy_wait = 0x00008d0c;
ll_clock_is_exist = 0x00009408;
enable_wphy = 0x0000b00c;
spi_s_set_ds = 0x00003e50;
config_rx_max_gain_state = 0x0000ae08;
enable_wphy_device_cont_tx = 0x000060f8;
fputc = 0x0000a72c;
config_wphy_device_tx_norm_mode = 0x000061d0;
ll_simple_uart_config = 0x0000a6bc;
spi_rx_buf = 0x000059dc;
get_rx_gfsk_gain_para = 0x0000aed0;
ll_tk_irq_config = 0x0000a4b0;
get_wphy_device_agc_info = 0x00006148;
hgsdio20_s_func1_cis = 0x0000e12c;
ll_tk_data = 0x0000a5dc;
qspi_flash_bootload_code = 0x000053f8;
get_wphy_device_avg_power = 0x000060c8;
ll_timer_ir_set_code_1 = 0x00007bf4;
aes_decrypt_encrypt = 0x00004bf8;
ll_simple_spi_irq_config = 0x0000a5f4;
spi_s_rx = 0x00003e04;
config_wphy_device_dis_gfsk_wphy = 0x00006318;
ll_spi_set_sample_delay = 0x00007e50;
sdio_s_dummy_buf = 0x2004759c;
ll_gmac_receive_frame = 0x00008b34;
config_wphy_device_rx_gain_tab = 0x00006180;
ll_led_timer_config = 0x00009d24;
ll_qspi_cmd_write_enable = 0x00008dac;
enable_wphy_device_rx_agc = 0x00006170;
ll_clock_usbpll_config = 0x000095e4;
hgsdio20_s_speed_list = 0x0000e164;
ll_uart_irq_config = 0x000067f8;
sys_aes_set_key_src = 0x00007c54;
ll_clock_syspll_set = 0x00009450;
ll_simple_spi_config = 0x0000a60c;
soft_reset_phy = 0x0000ab44;
ll_gmac_has_received_frame = 0x000089ac;
get_wphy_gfsk_tx_crc = 0x0000af4c;
ll_wdt_init = 0x000063ec;
ll_qspi_cmd_exit_qpi_mode = 0x00008ee0;
ll_tk_scan_kick = 0x0000a5bc;
ll_crc_wait_done_pending = 0x00006a9c;
hgusb20_dev_set_speed = 0x000047c4;
config_low_pwr_th = 0x0000afe4;
ll_qspi_cmd_flash_64kb_erase = 0x00008fe0;
ll_gmac_get_setup_frame_status = 0x00008c10;
hgsdio20_s_func0_cis = 0x0000e118;
config_wphy_device_tx_gain = 0x00006290;
spiflash_bootloader = 0x00005c08;
ll_uart485_config = 0x00006940;
ll_tk_hw_kick = 0x0000a59c;
crc8_itu_cfg = 0x0000d758;
strlen = 0x000017e0;
__cskyvprintfprintf = 0x0000109c;
get_rx_psdu_crc16 = 0x0000ab5c;
hgusb20_init_globle = 0x00006ab0;
sdio_s_func0_cis = 0x200475bc;
get_wphy_device_rx_psdu_crc = 0x00006200;
get_wphy_device_info = 0x0000601c;
sys_aes_clear_pending = 0x00007c80;
hgusb20_dev_set_ds = 0x000047c0;
rcons = 0x0000eba8;
ll_gmac_delay = 0x0000846c;
get_wphy_tx_crc = 0x0000ab90;
fputs = 0x00001124;
cfg_dpd_coef = 0x0000ac30;
ll_qspi_cmd_issue = 0x00008c50;
spi_read_cfg_nor = 0x0000dd8c;
ll_crc_continue = 0x00006a84;
ll_clock_set_sys_clk_div = 0x00009358;
get_wphy_gfsk_rx_crc = 0x0000af5c;
ll_iic_config = 0x00007fd4;
ll_simple_uart_deinit = 0x0000a66c;
get_bk_noise = 0x0000af9c;
__jpeg_htable = 0x0000fc00;
get_wphy_agc_info = 0x0000ad7c;
hgusb20_wifi_xfer_reset = 0x000077e4;
debug_select_interface = 0x0000a704;
ll_spi_get_wire_mode = 0x00007e64;
hgusb20_ep0_standard = 0x00007250;
disable_wphy_device_rx_agc = 0x00006160;
sys_reset = 0x0000a988;
ll_iis_enable = 0x000083fc;
ll_clock_set_apb1_div = 0x00009388;
ll_led_deinit = 0x00009b80;
qspi_flash_boot = 0x0000551c;
config_rx_gain_tab = 0x0000afb8;
get_core_clock = 0x0000a9bc;
project/utilities/romcode_org.ld
+458
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@@ -0,0 +1,458 @@
ll_spi_init = 0x00007d6c;
hgusb20_intr_dis = 0x00006bd4;
ll_spi_rx = 0x00007f2c;
strcpy = 0x00001820;
ll_uart_txdma_kick = 0x00006a74;
sdio_s_set_ds = 0x00003a14;
hgusb20_clear_ep = 0x00006e70;
sys_aes_init = 0x00007d10;
fabs = 0x000001a8;
disable_wphy_device_cont_tx = 0x0000618c;
config_wphy_device_dpd_coef = 0x00006300;
sys_aes_key_bitlen_sel = 0x00007cec;
ll_simple_spi_init = 0x0000a674;
hgusb20_irq_dma = 0x00007734;
fw_upg_addr = 0x2005247c;
crc16_modbus_calc = 0x00003018;
close_wphy = 0x0000adb0;
ll_iic_slave_rx = 0x0000828c;
hgusb20_wifi_reset = 0x00007a8c;
ll_crc_start = 0x00006afc;
ll_m2m_memcpy = 0x000082fc;
os_critical_close = 0x00001b2c;
hgusb20_irq_set = 0x00007678;
printf = 0x00001080;
stdout = 0x20052420;
ll_sdio_s_tx_kick = 0x000092f0;
hgusb20_ep0_clrrx_pkt0 = 0x00006d30;
uart_s_set_speed = 0x000042b4;
get_wphy_device_avg_evm = 0x00006164;
tbl_usb_language_id = 0x0000e06c;
sdio_s_tx = 0x00003ab4;
config_phy_tx_norm_mode = 0x0000ae6c;
get_wphy_device_gfsk_tx_crc = 0x000063c4;
ll_wdt_feed = 0x000064d4;
ll_timer_ir_enable = 0x00007c64;
ll_spi_buf_rx = 0x00007fd4;
spiflash_boot = 0x00005eb8;
md5_vector = 0x0000bc3c;
ll_clock_syspll_config = 0x0000961c;
ll_clock_hirc_enable = 0x00009370;
fw_upg_blk_addr = 0x20052480;
ll_uart_init = 0x00006860;
tbl_usb_str_manufacturer = 0x0000e070;
spi_cfg = 0x0000debc;
strerror = 0x00002d48;
config_phy_tx_sine_mode = 0x0000ae2c;
ll_spi_config = 0x00007d88;
hgwphy_bgn_attach = 0x0000b18c;
qspi_flash_port_deinit = 0x00004df8;
usb20 = 0x2004768c;
ll_sys_clock_globle_set = 0x0000abfc;
ll_m2m_memset = 0x00008320;
hgusb20_ep0_clr_feature = 0x00006fdc;
sdio_boot = 0x20052468;
ll_tk_stop = 0x0000a664;
hgusb20_dev_reset = 0x00006f1c;
ll_gpio_iomap_output_config = 0x0000650c;
get_wphy_device_rx_gain_para = 0x00006374;
ll_sdio_s_irq_config = 0x0000925c;
atol = 0x000014f4;
ll_iic_master_tx = 0x00008190;
ll_simple_uart_init = 0x0000a6f0;
hgusb20_stall_ep = 0x00006df0;
tbl_winusb_device_descriptor = 0x0000e1ac;
ll_clock_set_sys_clk_src = 0x000093c4;
ll_sys_clock_init = 0x0000abb8;
hgusb20_ep0_get_status = 0x00006f64;
config_dpd = 0x0000afb0;
SHA1Update = 0x0000cbd8;
ll_gmac_get_tx_frame_status = 0x00008cac;
ll_qspi_controller_init = 0x00009224;
sha256_init = 0x0000cee0;
errno = 0x200524d0;
open_wphy = 0x0000ace8;
hgusb20_dev_init = 0x00006d88;
ll_qspi_set_prefetch = 0x00009170;
ll_gpio_pull_config = 0x00006680;
tbl_winusb_compatible_id_feature_descriptor = 0x0000e184;
get_wphy_avg_evm = 0x0000aea4;
ll_spi_dma_start = 0x00007e7c;
uart_s_rx = 0x0000431c;
CORE_SEC_OPT = 0x0000932c;
trig_calc_bk_noise = 0x0000b0d4;
sha256_done = 0x0000cff0;
spi_boot = 0x20052674;
freq_offset_sign_ext = 0x0000b178;
sys_aes_start = 0x00007d2c;
SHA1Init = 0x0000cba8;
ll_tk_ch_kick = 0x0000a658;
ll_iic_master_rx = 0x000081c8;
spi_s_tx = 0x00003e8c;
enable_auto_sig_err_rst = 0x0000af9c;
qspi_flash_poweroff = 0x00004ec8;
fwinfo_check_fwinfo_hdr = 0x000044f8;
hgusb20_irq_handler_set = 0x00007658;
ll_iic_master_buf_tx = 0x00008218;
ll_spi_dma_config = 0x00007e54;
config_wphy_device_en_gfsk_wphy = 0x000063b0;
memcpy = 0x00001908;
hgusb20_ep0_set_feature = 0x00007020;
sys_aes_get_pending = 0x00007cfc;
atcmd_fwupg = 0x0000d8e0;
ll_m2m_dma_init = 0x000082a4;
fw_upg_prepare = 0x00004534;
tbl_winusb20_wcidbos = 0x0000e160;
spiflash_read = 0x00005ab0;
ll_qspi_set_write_protect = 0x00009130;
puts = 0x000010b8;
hgusb20_ep0_set_configuration = 0x00007294;
ll_tk_config = 0x0000a584;
sys_aes_set_irq = 0x00007cb0;
hgusb20_ep0_get_wcid_descriptor = 0x00007360;
ll_gmac_start = 0x00008684;
crc16_modbus_cfg = 0x0000d870;
ll_iis_disable = 0x0000848c;
hgusb20_ep0_func = 0x000074ec;
ll_clock_test_clk_en = 0x00009350;
ll_iic_irq_config = 0x000080c0;
get_wphy_device_rx_gfsk_gain_para = 0x00006388;
hgusb20_reset2device_mode = 0x00006b38;
ll_gpio_analog_config = 0x000064ec;
hgusb20_ep0_descriptor = 0x00007150;
hgusb20_dev_rx = 0x000048a0;
ll_suptmr_deinit = 0x00009ed4;
strtoll = 0x00001518;
ll_qspi_cmd_quad_enable = 0x00008e74;
crc32_calc = 0x0000303c;
ll_gmac_init = 0x00008504;
qspi_flash_power_reset = 0x00004ef0;
disable_wphy = 0x0000acb4;
xmodem_receive = 0x00004ac0;
strtoul = 0x00001198;
ll_iic_master_buf_rx = 0x0000825c;
config_wphy_device_cca_th = 0x00006224;
adj_gain_value = 0x0000afc0;
ll_gmac_send_frame = 0x00008a7c;
ll_ir_timer_irq_config = 0x00007afc;
hgusb20_switch_stable_device = 0x00006bc4;
get_wphy_err_code = 0x0000aeb0;
ll_led_timer_deinit = 0x00009da8;
uart_s_tx = 0x000042ec;
ll_iis_soft_rst = 0x00008494;
isspace = 0x0000106c;
boot = 0x200524d8;
ll_crc_init = 0x00006a98;
ll_spi_set_wire_mode = 0x00007e88;
get_wphy_device_gfsk_rx_crc = 0x000063dc;
ll_simple_spi_deinit = 0x0000a67c;
ll_gmac_irq_config = 0x00008600;
config_phy_tx_waveform_mode = 0x0000b158;
ll_timer_deinit = 0x00007a98;
sdio_slave_init = 0x00003d18;
enable_wphy_device = 0x00006114;
ll_crc_deinit = 0x00006ab4;
usb_irq_ids = 0x200524a4;
usb_test_mode_tbl = 0x0000df98;
hgusb20_ep_set_txrdy = 0x00007998;
strncasecmp = 0x00004c3c;
ll_simple_uart_irq_config = 0x0000a708;
sha256_vector = 0x0000d0e8;
ll_clock_set_apb0_div = 0x000093fc;
ll_timer_sync_start = 0x00007c7c;
MD5Final = 0x0000bbc4;
sdio_port_init = 0x00003b18;
hgusb20_ep0_tx = 0x00006cb4;
qspi_flash_deinit = 0x0000503c;
config_wphy_device_gfsk_crc_init = 0x000063f4;
ll_spi_deinit = 0x00007d7c;
tbl_winusb20_wcid_descriptor_set = 0x0000e0bc;
tbl_winusb_device_interface_guids = 0x0000e1c0;
Te0 = 0x0000e8f8;
ll_qspi_cmd_enter_qpi_mode = 0x00008eec;
ll_ir_timer_config = 0x00007bd8;
strtol = 0x00001298;
crc32_cfg = 0x0000d88c;
usb_test_packet = 0x0000dfa0;
ll_spi_buf_tx = 0x00007f54;
adj_gfsk_gain_value = 0x0000affc;
ll_gmac_config = 0x00008554;
uart_s_set_ds = 0x000042cc;
config_cca_th = 0x0000af60;
cfg_wphy_gfsk_ch = 0x0000b0c4;
hgusb20_irq = 0x00007798;
ll_uart_deinit = 0x00006874;
spiflash_init = 0x000058a4;
tbl_usb_str_serial_number = 0x0000e09c;
cfg_wphy_gfsk_crc_init = 0x0000b0b4;
get_wphy_device_tx_psdu_crc = 0x0000629c;
strtod = 0x00001b6c;
ll_suptmr_comm_config = 0x00009eec;
spiflash_deinit = 0x000059b0;
spi_s_rx_len_exp = 0x20052478;
ll_gmac_setup_send_frame = 0x00008af8;
ll_gpio_iomap_input_config = 0x0000655c;
atof = 0x0000150c;
ll_iic_dma_config = 0x00008154;
disable_rx_agc = 0x0000af28;
disable_auto_sig_err_rst = 0x0000af88;
disable_gfsk_wphy = 0x0000b068;
config_wphy_device_gfsk_ch = 0x00006408;
sdio_s_rx = 0x00003ac4;
ll_tk_sf_kick = 0x0000a638;
strcat = 0x000018ec;
ll_spi_irq_config = 0x00007dfc;
hgusb20_init = 0x0000762c;
sys_aes_set_mode = 0x00007cc4;
adjust_wphy_device_gain_value = 0x00006328;
tbl_usb_str_product = 0x0000e080;
ll_tk_deinit = 0x0000a53c;
sha256_process = 0x0000cf30;
get_rx_freq_offset = 0x0000aed0;
config_phy_tx_tri_mode = 0x0000ae4c;
tbl_usb_config_all_descriptor_wifi = 0x0000e040;
config_wphy_device_tx_tri_mode = 0x00006244;
hgusb20_bot_reset = 0x00006ee0;
sdio_rx_len_exp = 0x20052470;
Td0 = 0x0000e3f8;
ll_sdio_s_rx_kick = 0x00009320;
ll_led_timer_init = 0x00009d9c;
os_critical_enter = 0x00001b24;
fw_upg_program = 0x00004578;
ll_timer_ir_set_code_0 = 0x00007c74;
sdio_s_set_speed = 0x00003aa8;
ll_gpio_pin_lock_config = 0x00006810;
ll_clock_exosc_enable = 0x00009398;
uart_s_xfer_done = 0x20052488;
soft_dereset_phy = 0x0000ac74;
ll_timer_ir_disable = 0x00007c6c;
sys_aes_set_block_num = 0x00007ca4;
ll_uart_work_mode_change = 0x00006a84;
memchr = 0x00001ae8;
ll_qspi_cmd_device_reset = 0x00008fb8;
stdin = 0x20052440;
ll_spi_tx = 0x00007ef0;
enable_rx_agc = 0x0000af3c;
ll_spi_set_clock_mode = 0x00007ec4;
delay_ms_systick = 0x0000aae8;
qspi_flash_port_init = 0x00004d54;
rand = 0x00001170;
ll_uart_dma_config = 0x00006a34;
ll_gmac_get_rx_frame_status = 0x00008cc4;
enable_gfsk_wphy = 0x0000b03c;
SysTickCnt = 0x200524bc;
ll_gpio_iomap_inout_config = 0x000065fc;
get_wphy_scrambler_init = 0x0000ae8c;
enable_wphy_cont_tx = 0x0000acb8;
ll_timer_config = 0x00007b3c;
isupper = 0x00001b04;
qspi_flash_init = 0x00004f20;
ll_iic_dma_start = 0x00008184;
ll_timer_irq_config = 0x00007a9c;
ll_timer_start = 0x00007c54;
ll_crc_stop = 0x00006b30;
ll_led_config = 0x00009c24;
hgusb20_wifi_init = 0x000079c4;
ll_sdio_s_config = 0x00009264;
sdio_interrupt_handle = 0x00003c54;
ll_led_timer_irq_config = 0x00009e24;
ll_qspi_set_clk = 0x000091a8;
strcasecmp = 0x00004bf8;
get_wphy_device_err_code = 0x000061b4;
ll_iis_dma_config = 0x00008470;
spi_base_pins = 0x0000de84;
get_rx_gain_para = 0x0000afd8;
hgusb20_wifi_ep_init = 0x000079c8;
qspi_flash_poweron = 0x00004ea0;
ll_gmac_mdio_read = 0x000088b4;
ll_crc_config = 0x00006ab8;
hgusb20_ep0_clrrx_contious = 0x00006d04;
os_critical_exit = 0x00001b28;
ll_iis_config = 0x0000835c;
get_wphy_device_scrambler_init = 0x00006134;
memcmp = 0x0000199c;
hgusb20_ep0_get_descriptor = 0x0000719c;
ll_qspi_cmd_release_power_down = 0x00009020;
ll_gmac_mdio_write = 0x000086cc;
adjust_wphy_device_gfsk_gain_value = 0x00006340;
crc16_xmodem = 0x00004a90;
isalpha = 0x00001b0c;
ll_timer_init = 0x00007a94;
disable_wphy_device = 0x00006124;
crc8_calc = 0x00002ff4;
config_wphy_device_tx_sine_mode = 0x00006234;
ll_tk_init = 0x0000a520;
delay_us = 0x0000aa3c;
_ctype = 0x0000dd84;
hgusb20_ep_rx_kick = 0x00007898;
ll_gmac_deinit = 0x000085c8;
disable_wphy_cont_tx = 0x0000acc8;
enable_wphy_device_auto_sig_err_rst = 0x000062c4;
ll_gmac_stop = 0x00008694;
strtoull = 0x000013b8;
disable_wphy_device_auto_sig_err_rst = 0x000062d8;
rijndaelKeySetupEnc = 0x0000d17c;
get_tx_psdu_crc16 = 0x0000acac;
ll_iic_slave_tx = 0x00008298;
config_wphy_rx_max_gain_state = 0x00006214;
memset = 0x00001740;
ll_suptmrx_config = 0x0000a02c;
ll_m2m_dma_config = 0x000082e8;
ll_m2m_dma_irq_config = 0x000082ec;
ll_uart232_config = 0x000068fc;
delay_ms = 0x0000aa68;
hgusb20_ep0_request = 0x000074a8;
ll_wdt_stop = 0x000064dc;
close_wphy_device = 0x00006090;
open_wphy_device = 0x00006080;
uart_s_boot = 0x000045d8;
srand = 0x0000118c;
hgusb20_dev_tx = 0x0000487c;
atcmd_bootl = 0x0000d8d8;
cp_mode = 0x00002e60;
get_wphy_device_rx_freq_offset = 0x0000635c;
soft_reset_wphy_device = 0x00006264;
config_wphy_device_dpd = 0x000062ec;
soft_dereset_wphy_device = 0x00006274;
ll_wdt_start = 0x000064c4;
ll_wdt_config = 0x00006474;
ll_suptmr_init = 0x00009e88;
ll_uart_rxdma_kick = 0x00006a64;
ll_clock_sys_clk_select = 0x0000942c;
hgusb20_int_init_b = 0x00006d60;
Td4s = 0x0000e7f8;
hgusb20_ep0_class = 0x0000742c;
get_wphy_device_tx_crc = 0x0000619c;
sdio_s_func1_cis = 0x200475d0;
ll_clock_test_clk_sel = 0x0000935c;
hgusb20_ep0_set_address = 0x0000708c;
spi_s_set_speed = 0x00003f00;
ll_iis_init = 0x00008344;
strcmp = 0x00001668;
ll_iic_init = 0x00008040;
config_wphy_device_low_pwr_th = 0x000062b4;
ll_iic_deinit = 0x0000804c;
ll_iis_irq_config = 0x00008448;
ll_iis_deinit = 0x00008350;
sys_clock_cfg = 0x200524a8;
flash_memory_init = 0x000043f4;
cfg_phy_tx_gain = 0x0000ada4;
ll_gmac_allow_send_frame = 0x00008a68;
ll_gpio_afio_config = 0x00006618;
ll_m2m_dma_deinit = 0x000082dc;
ll_gpio_ospeed_config = 0x00006828;
MD5Init = 0x0000baf8;
ll_wdt_deinit = 0x000064b4;
os_critical_open = 0x00001b20;
strtof = 0x000014e8;
sys_aes_set_key = 0x00007c90;
hgusb20_config_desc_prepare = 0x00006bec;
dev_register = 0x0000641c;
ll_led_init = 0x00009bfc;
get_wphy_avg_power = 0x0000ae98;
stderr = 0x20052400;
ll_ir_timer_dma_config = 0x00007c24;
ll_clock_usb_clk_en = 0x00009778;
ll_timer_stop = 0x00007c5c;
ll_qspi_cmd_busy_wait = 0x00008d90;
hgusb20_ep_set_rxrdy = 0x00007994;
ll_clock_is_exist = 0x00009494;
enable_wphy = 0x0000b154;
MD5Update = 0x0000bb20;
spi_s_set_ds = 0x00003f0c;
config_rx_max_gain_state = 0x0000af50;
enable_wphy_device_cont_tx = 0x0000617c;
fputc = 0x0000a810;
config_wphy_device_tx_norm_mode = 0x00006254;
tbl_usb_config_all_descriptor_gen = 0x0000e034;
ll_simple_uart_config = 0x0000a74c;
spi_rx_buf = 0x00005a60;
get_rx_gfsk_gain_para = 0x0000b018;
tbl_usb_device_descriptor = 0x0000e058;
ll_tk_irq_config = 0x0000a540;
get_wphy_device_agc_info = 0x000061cc;
sysctrl_qspi_get_src_clk = 0x0000a794;
hgsdio20_s_func1_cis = 0x0000e27c;
isdigit = 0x00001afc;
SHA1Final = 0x0000cc68;
ll_tk_data = 0x0000a66c;
qspi_flash_bootload_code = 0x000054a4;
get_wphy_device_avg_power = 0x0000614c;
ll_timer_ir_set_code_1 = 0x00007c78;
aes_decrypt_encrypt = 0x00004ca4;
ll_simple_spi_irq_config = 0x0000a684;
spi_s_rx = 0x00003ec0;
config_wphy_device_dis_gfsk_wphy = 0x0000639c;
ll_spi_set_sample_delay = 0x00007ed4;
sdio_s_dummy_buf = 0x2004759c;
ll_gmac_receive_frame = 0x00008bb8;
config_wphy_device_rx_gain_tab = 0x00006204;
ll_led_timer_config = 0x00009db4;
ll_qspi_cmd_write_enable = 0x00008e30;
enable_wphy_device_rx_agc = 0x000061f4;
ll_clock_usbpll_config = 0x00009674;
SHA1Transform = 0x0000bc94;
hgsdio20_s_speed_list = 0x0000e2b4;
ll_uart_irq_config = 0x0000687c;
sys_aes_set_key_src = 0x00007cd8;
ll_clock_syspll_set = 0x000094e0;
ll_simple_spi_config = 0x0000a69c;
soft_reset_phy = 0x0000ac8c;
ll_gmac_has_received_frame = 0x00008a30;
get_wphy_gfsk_tx_crc = 0x0000b094;
ll_wdt_init = 0x00006470;
ll_qspi_cmd_exit_qpi_mode = 0x00008f64;
ll_tk_scan_kick = 0x0000a64c;
atoi = 0x00001500;
ll_crc_wait_done_pending = 0x00006b20;
hgusb20_dev_set_speed = 0x00004870;
config_low_pwr_th = 0x0000b12c;
ll_qspi_cmd_flash_64kb_erase = 0x00009064;
ll_gmac_get_setup_frame_status = 0x00008c94;
hgsdio20_s_func0_cis = 0x0000e268;
config_wphy_device_tx_gain = 0x00006314;
spiflash_bootloader = 0x00005c8c;
ll_uart485_config = 0x000069c4;
ll_tk_hw_kick = 0x0000a62c;
crc8_itu_cfg = 0x0000d8a8;
strlen = 0x000017e0;
__cskyvprintfprintf = 0x0000109c;
get_rx_psdu_crc16 = 0x0000aca4;
hgusb20_init_globle = 0x00006b34;
sdio_s_func0_cis = 0x200475bc;
get_wphy_device_rx_psdu_crc = 0x00006284;
get_wphy_device_info = 0x000060a0;
sys_aes_clear_pending = 0x00007d04;
hgusb20_dev_set_ds = 0x0000486c;
rcons = 0x0000ecf8;
ll_gmac_delay = 0x000084f0;
abs = 0x00001290;
strchr = 0x00001988;
get_wphy_tx_crc = 0x0000acd8;
fputs = 0x00001124;
cfg_dpd_coef = 0x0000ad78;
ll_qspi_cmd_issue = 0x00008cd4;
spi_read_cfg_nor = 0x0000dedc;
hgusb20_ep_tx_kick = 0x00007918;
ll_crc_continue = 0x00006b08;
ll_clock_set_sys_clk_div = 0x000093e4;
get_wphy_gfsk_rx_crc = 0x0000b0a4;
hgusb20_ep0_transfer = 0x000070cc;
ll_iic_config = 0x00008058;
ll_simple_uart_deinit = 0x0000a6fc;
get_bk_noise = 0x0000b0e4;
__jpeg_htable = 0x0000fc00;
get_wphy_agc_info = 0x0000aec4;
hgusb20_wifi_xfer_reset = 0x00007868;
debug_select_interface = 0x0000a7e8;
sha1_vector = 0x0000cd2c;
ll_spi_get_wire_mode = 0x00007ee8;
hgusb20_ep0_standard = 0x000072d4;
disable_wphy_device_rx_agc = 0x000061e4;
sys_reset = 0x0000aac8;
ll_iis_enable = 0x00008480;
ll_clock_set_apb1_div = 0x00009414;
ll_led_deinit = 0x00009c10;
qspi_flash_boot = 0x000055c8;
config_rx_gain_tab = 0x0000b100;
get_core_clock = 0x0000aafc;