Esp32 iram attr (#26)
* changed the version to 201 in the header * added conditional compilation for ESP8266 to add ICACHE_RAM_ATTR to ExternalInterruptHandler changed storage for Micros to unsigned long * some tuning to bit recognition and nested IRQ (STM32)
This commit is contained in:
Franz-Peter
committed by
Alex Shepherd
Alex Shepherd
parent
5cee0d28ed
commit
71bb657e3a
40
NmraDcc.cpp
40
NmraDcc.cpp
@@ -93,7 +93,7 @@
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#define MAX_ONEBITHALF 82
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#define MIN_ONEBITFULL 82
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#define MIN_ONEBITHALF 35
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#define MAX_BITDIFF 18
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#define MAX_BITDIFF 24
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// Debug-Ports
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@@ -217,18 +217,12 @@
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#define MODE_TP2
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#define SET_TP2
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#define CLR_TP2
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//#define MODE_TP2 DDRC |= (1<<2) // A2
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//#define SET_TP2 PORTC |= (1<<2)
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//#define CLR_TP2 PORTC &= ~(1<<2)
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#define MODE_TP3
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#define SET_TP3
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#define CLR_TP3
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#define MODE_TP4
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#define SET_TP4
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#define CLR_TP4
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//#define MODE_TP4 DDRC |= (1<<4) //A4
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//#define SET_TP4 PORTC |= (1<<4)
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//#define CLR_TP4 PORTC &= ~(1<<4)
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#endif
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#ifdef DEBUG_PRINT
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@@ -310,6 +304,8 @@ DCC_PROCESSOR_STATE DccProcState ;
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portMUX_TYPE mux = portMUX_INITIALIZER_UNLOCKED;
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void IRAM_ATTR ExternalInterruptHandler(void)
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#elif defined(ESP8266)
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void ICACHE_RAM_ATTR ExternalInterruptHandler(void)
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#else
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void ExternalInterruptHandler(void)
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#endif
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@@ -340,9 +336,10 @@ void ExternalInterruptHandler(void)
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// Bit evaluation without Timer 0 ------------------------------
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uint8_t DccBitVal;
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static int8_t bit1, bit2 ;
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static word lastMicros;
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static unsigned int lastMicros = 0;
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static byte halfBit, DCC_IrqRunning;
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unsigned int actMicros, bitMicros;
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#ifdef ALLOW_NESTED_IRQ
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if ( DCC_IrqRunning ) {
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// nested DCC IRQ - obviously there are glitches
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// ignore this interrupt and increment glitchcounter
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@@ -353,6 +350,7 @@ void ExternalInterruptHandler(void)
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SET_TP3;
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return; //>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> abort IRQ
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}
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#endif
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SET_TP3;
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actMicros = micros();
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bitMicros = actMicros-lastMicros;
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@@ -364,11 +362,12 @@ void ExternalInterruptHandler(void)
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}
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DccBitVal = ( bitMicros < bitMax );
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lastMicros = actMicros;
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#ifdef debug
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if(DccBitVal) {SET_TP2;} else {CLR_TP2;};
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#endif
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#ifdef ALLOW_NESTED_IRQ
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DCC_IrqRunning = true;
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interrupts(); // time critical is only the micros() command,so allow nested irq's
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#endif
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#ifdef DCC_DEBUG
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DccProcState.TickCount++;
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#endif
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@@ -429,13 +428,10 @@ void ExternalInterruptHandler(void)
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DccRx.BitCount++;
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if( abs(bit2-bit1) > MAX_BITDIFF ) {
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// the length of the 2 halfbits differ too much -> wrong protokoll
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CLR_TP2;
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CLR_TP3;
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DccRx.State = WAIT_PREAMBLE;
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bitMax = MAX_PRAEAMBEL;
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bitMin = MIN_ONEBITFULL;
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DccRx.BitCount = 0;
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SET_TP4;
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#if defined ( __STM32F1__ )
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detachInterrupt( DccProcState.ExtIntNum );
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@@ -562,6 +558,7 @@ void ExternalInterruptHandler(void)
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{
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CLR_TP3;
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DccRx.State = WAIT_PREAMBLE ;
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DccRx.BitCount = 0 ;
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bitMax = MAX_PRAEAMBEL;
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bitMin = MIN_ONEBITFULL;
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#ifdef ESP32
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@@ -591,9 +588,11 @@ void ExternalInterruptHandler(void)
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DccRx.TempByte = 0 ;
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}
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}
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#ifdef ALLOW_NESTED_IRQ
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DCC_IrqRunning = false;
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#endif
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CLR_TP1;
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CLR_TP3;
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DCC_IrqRunning = false;
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}
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void ackCV(void)
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@@ -1355,6 +1354,17 @@ void NmraDcc::pin( uint8_t ExtIntNum, uint8_t ExtIntPinNum, uint8_t EnablePullup
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#if defined ( __STM32F1__ )
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// with STM32F1 the interuptnumber is equal the pin number
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DccProcState.ExtIntNum = ExtIntPinNum;
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// because STM32F1 has a NVIC we must set interuptpriorities
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const nvic_irq_num irqNum2nvic[] = { NVIC_EXTI0, NVIC_EXTI1, NVIC_EXTI2, NVIC_EXTI3, NVIC_EXTI4,
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NVIC_EXTI_9_5, NVIC_EXTI_9_5, NVIC_EXTI_9_5, NVIC_EXTI_9_5, NVIC_EXTI_9_5,
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NVIC_EXTI_15_10, NVIC_EXTI_15_10, NVIC_EXTI_15_10, NVIC_EXTI_15_10, NVIC_EXTI_15_10, NVIC_EXTI_15_10 };
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exti_num irqNum = (exti_num)(PIN_MAP[ExtIntPinNum].gpio_bit);
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// DCC-Input IRQ must be able to interrupt other long low priority ( level15 ) IRQ's
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nvic_irq_set_priority ( irqNum2nvic[irqNum], PRIO_DCC_IRQ);
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// Systic must be able to interrupt DCC-IRQ to always get correct micros() values
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nvic_irq_set_priority(NVIC_SYSTICK, PRIO_SYSTIC);
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#else
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DccProcState.ExtIntNum = ExtIntNum;
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#endif
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@@ -49,10 +49,12 @@
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#ifndef NMRADCC_IS_IN
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#define NMRADCC_IS_IN
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#define NMRADCC_VERSION 200 // Version 2.0.0
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#define NMRADCC_VERSION 201 // Version 2.0.1
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#define MAX_DCC_MESSAGE_LEN 6 // including XOR-Byte
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//#define ALLOW_NESTED_IRQ // uncomment to enable nested IRQ's ( only for AVR! )
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typedef struct
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{
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uint8_t Size ;
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@@ -105,6 +107,9 @@ typedef struct
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#elif defined( __STM32F1__)
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#define MAXCV (EEPROM_PAGE_SIZE/4 - 1) // number of storage places (CV address could be larger
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// because STM32 uses virtual adresses)
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#undef ALLOW_NESTED_IRQ // This is done with NVIC on STM32
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#define PRIO_DCC_IRQ 9
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#define PRIO_SYSTIC 8 // MUST be higher priority than DCC Irq
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#else
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#define MAXCV E2END // the upper limit of the CV value currently defined to max memory.
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#endif
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