Esp32 iram attr (#26)
* changed the version to 201 in the header * added conditional compilation for ESP8266 to add ICACHE_RAM_ATTR to ExternalInterruptHandler changed storage for Micros to unsigned long * some tuning to bit recognition and nested IRQ (STM32)
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committed by
Alex Shepherd
parent
5cee0d28ed
commit
71bb657e3a
@@ -49,10 +49,12 @@
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#ifndef NMRADCC_IS_IN
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#define NMRADCC_IS_IN
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#define NMRADCC_VERSION 200 // Version 2.0.0
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#define NMRADCC_VERSION 201 // Version 2.0.1
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#define MAX_DCC_MESSAGE_LEN 6 // including XOR-Byte
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//#define ALLOW_NESTED_IRQ // uncomment to enable nested IRQ's ( only for AVR! )
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typedef struct
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{
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uint8_t Size ;
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@@ -105,6 +107,9 @@ typedef struct
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#elif defined( __STM32F1__)
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#define MAXCV (EEPROM_PAGE_SIZE/4 - 1) // number of storage places (CV address could be larger
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// because STM32 uses virtual adresses)
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#undef ALLOW_NESTED_IRQ // This is done with NVIC on STM32
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#define PRIO_DCC_IRQ 9
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#define PRIO_SYSTIC 8 // MUST be higher priority than DCC Irq
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#else
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#define MAXCV E2END // the upper limit of the CV value currently defined to max memory.
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#endif
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